From 4495fd600ea9e066ba6fdfe0548eff1aa9ca204d Mon Sep 17 00:00:00 2001 From: Bobbi Webber-Manners Date: Sun, 18 Dec 2022 19:04:38 -0500 Subject: [PATCH] Audited RDMAINRAM/RDCARDRAM is safe. --- applecorn.s | 13 +++++++++++++ auxmem.bytwrd.s | 8 ++++---- auxmem.misc.s | 26 ++------------------------ auxmem.vdu.s | 28 ++++++++++++++-------------- 4 files changed, 33 insertions(+), 42 deletions(-) diff --git a/applecorn.s b/applecorn.s index 11fa5a6..e13214e 100644 --- a/applecorn.s +++ b/applecorn.s @@ -227,6 +227,19 @@ WRTAUX MAC PLP ; Normal service resumed EOM +* Enable reading from main memory (for code running in aux LC) +RDMAIN MAC + PHP + SEI ; Keeps IRQ handler easy + STZ RDMAINRAM ; Read from main memory + EOM + +* Go back to reading from aux (for code running in aux LC) +RDAUX MAC + STZ RDCARDRAM ; Read from aux memory + PLP ; Normal service resumed + EOM + * Manually enable AltZP + Aux LC (for code running in main) * Banks ROM out ALTZP MAC diff --git a/auxmem.bytwrd.s b/auxmem.bytwrd.s index f1b95ec..ee6fa0d 100644 --- a/auxmem.bytwrd.s +++ b/auxmem.bytwrd.s @@ -331,22 +331,22 @@ WORD00 IF MAXLEN-OSTEXT-2 * Y=0 * IRQs are disabled while we access the timers and main memory -WORD01 STA RDMAINRAM ; Read from main mem (IRQs are off) +WORD01 STZ RDMAINRAM ; Read from main mem (IRQs are off) :WORD01LP LDA SYSCLOCK,Y ; Read sys clock in main mem STA (OSCTRL),Y ; Store in buffer in aux mem INY CPY #$05 BCC :WORD01LP - STA RDCARDRAM ; Reads back to aux memory + STZ RDCARDRAM ; Reads back to aux memory RTS -WORD02 STA WRMAINRAM ; Write to main mem (IRQs are off) +WORD02 STZ WRMAINRAM ; Write to main mem (IRQs are off) :WORD02LP LDA (OSCTRL),Y ; Read from buffer in aux mem STA SYSCLOCK,Y ; Store to sys clock in main mem INY CPY #$05 BCC :WORD02LP - STA WRCARDRAM ; Writes back to aux memory + STZ WRCARDRAM ; Writes back to aux memory RTS WORD03 diff --git a/auxmem.misc.s b/auxmem.misc.s index eef2097..1ca2788 100644 --- a/auxmem.misc.s +++ b/auxmem.misc.s @@ -351,9 +351,9 @@ ROMSELOK PLP * Initialize ROMTAB according to user selection in menu ROMINIT STZ MAXROM ; One sideways ROM only - STA RDMAINRAM ; Read main mem + >>> RDMAIN ; Read main mem LDA USERSEL ; *TO DO* Should be actual number of ROMs - STA RDCARDRAM ; Read aux mem + >>> RDAUX ; Read aux mem CMP #6 BNE :X1 @@ -380,16 +380,6 @@ GSBRKAUX >>> IENTAUX ; IENTAUX does not do CLI IRQBRKHDLR PHA * Mustn't enable IRQs within the IRQ handler * Do not use WRTMAIN/WRTAUX macros -* LDA RDRAMRD ; Record softswitch state -* STA $90 -* LDA RDRAMWR -* STA $91 -* -* STA WRMAINRAM ; Write to main memory -* STA $45 ; $45=A for ProDOS IRQ handlers -* STA WRCARDRAM ; Write to aux memory -* STA RDCARDRAM ; Read from aux memory - PHX CLD TSX @@ -422,18 +412,6 @@ IRQBRKRET PLY -* LDA $90 ; Restore state of RAMRD -* BMI :S1 -* STA RDMAINRAM -* BRA :S2 -*:S1 STA RDCARDRAM -* -*:S2 LDA $91 ; Restore state of RAMWRT -* BMI :S3 -* STA WRMAINRAM -* BRA :S4 -*:S3 STA WRCARDRAM - *:S4 ; TODO: Pass on to IRQ1V PLX PLA diff --git a/auxmem.vdu.s b/auxmem.vdu.s index 875beee..fb3ec06 100644 --- a/auxmem.vdu.s +++ b/auxmem.vdu.s @@ -399,9 +399,9 @@ GETCHRC JSR CHARADDR ; Find character address BIT VDUBANK BMI GETCHRGS BCC GETCHR6 ; Aux memory - STA RDMAINRAM ; Read main memory + STZ RDMAINRAM ; Read main memory (IRQs off) GETCHR6 LDA (VDUADDR),Y ; Get character - STA RDCARDRAM ; Read aux memory + STZ RDCARDRAM ; Read aux memory TAY ; Convert character AND #$A0 BNE GETCHR7 @@ -414,9 +414,9 @@ GETCHR7 TYA TAX ; X=char GETCHROK RTS GETCHRGS BCC GETCHR8 ; Aux memory - STA RDMAINRAM ; Read main memory + STZ RDMAINRAM ; Read main memory (IRQs off) GETCHR8 LDA [VDUADDR],Y ; Get character - STA RDCARDRAM ; Read aux memory + STZ RDCARDRAM ; Read aux memory TAY ; Convert character AND #$A0 BNE GETCHR9 @@ -812,10 +812,10 @@ DOSCR1LINE INC TXTWINRGT STA (VDUADDR2),Y BRA :SKIPMAIN :MAIN >>> WRTMAIN - STA RDMAINRAM ; Read main memory + STZ RDMAINRAM ; Read main memory (IRQs off) LDA (VDUADDR),Y STA (VDUADDR2),Y - STA RDCARDRAM ; Read aux memory + STZ RDCARDRAM ; Read aux memory >>> WRTAUX :SKIPMAIN INX CPX TXTWINRGT @@ -824,10 +824,10 @@ DOSCR1LINE INC TXTWINRGT :FORTY TXA TAY :L2 >>> WRTMAIN - STA RDMAINRAM ; Read main memory + STZ RDMAINRAM ; Read main memory (IRQs off) LDA (VDUADDR),Y STA (VDUADDR2),Y - STA RDCARDRAM ; Read aux memory + STZ RDCARDRAM ; Read aux memory >>> WRTAUX INY CPY TXTWINRGT @@ -847,20 +847,20 @@ SCR1LINEGS LDX TXTWINLFT STA VDUBANK STA VDUBANK2 >>> WRTMAIN - STA RDMAINRAM ; Read main memory + STZ RDMAINRAM ; Read main memory (IRQs off) LDA [VDUADDR],Y ; Even cols in bank $E1 STA [VDUADDR2],Y - STA RDCARDRAM ; Read aux memory + STZ RDCARDRAM ; Read aux memory >>> WRTAUX BRA :SKIPE0 :E0 LDA #$E0 STA VDUBANK STA VDUBANK2 >>> WRTMAIN - STA RDMAINRAM ; Read main memory + STZ RDMAINRAM ; Read main memory (IRQs off) LDA [VDUADDR],Y ; Odd cols in bank $E0 STA [VDUADDR2],Y - STA RDCARDRAM ; Read aux memory + STZ RDCARDRAM ; Read aux memory >>> WRTAUX :SKIPE0 INX CPX TXTWINRGT @@ -871,10 +871,10 @@ SCR1LINEGS LDX TXTWINLFT LDA #$E0 STA VDUBANK :L2 >>> WRTMAIN - STA RDMAINRAM ; Read main memory + STZ RDMAINRAM ; Read main memory (IRQs off) LDA [VDUADDR],Y STA [VDUADDR2],Y - STA RDCARDRAM ; Read aux memory + STZ RDCARDRAM ; Read aux memory >>> WRTAUX INY CPY TXTWINRGT