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Applecorn
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Audited RDMAINRAM/RDCARDRAM is safe.

This commit is contained in:
Bobbi Webber-Manners 2022-12-18 19:04:38 -05:00
parent 7232b49090
commit 4495fd600e
4 changed files with 33 additions and 42 deletions
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13
applecorn.s
View File

@ -227,6 +227,19 @@ WRTAUX MAC
PLP ; Normal service resumed PLP ; Normal service resumed
EOM EOM
* Enable reading from main memory (for code running in aux LC)
RDMAIN MAC
PHP
SEI ; Keeps IRQ handler easy
STZ RDMAINRAM ; Read from main memory
EOM
* Go back to reading from aux (for code running in aux LC)
RDAUX MAC
STZ RDCARDRAM ; Read from aux memory
PLP ; Normal service resumed
EOM
* Manually enable AltZP + Aux LC (for code running in main) * Manually enable AltZP + Aux LC (for code running in main)
* Banks ROM out * Banks ROM out
ALTZP MAC ALTZP MAC

8
auxmem.bytwrd.s
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@ -331,22 +331,22 @@ WORD00 IF MAXLEN-OSTEXT-2
* Y=0 * Y=0
* IRQs are disabled while we access the timers and main memory * IRQs are disabled while we access the timers and main memory
WORD01 STA RDMAINRAM ; Read from main mem (IRQs are off) WORD01 STZ RDMAINRAM ; Read from main mem (IRQs are off)
:WORD01LP LDA SYSCLOCK,Y ; Read sys clock in main mem :WORD01LP LDA SYSCLOCK,Y ; Read sys clock in main mem
STA (OSCTRL),Y ; Store in buffer in aux mem STA (OSCTRL),Y ; Store in buffer in aux mem
INY INY
CPY #$05 CPY #$05
BCC :WORD01LP BCC :WORD01LP
STA RDCARDRAM ; Reads back to aux memory STZ RDCARDRAM ; Reads back to aux memory
RTS RTS
WORD02 STA WRMAINRAM ; Write to main mem (IRQs are off) WORD02 STZ WRMAINRAM ; Write to main mem (IRQs are off)
:WORD02LP LDA (OSCTRL),Y ; Read from buffer in aux mem :WORD02LP LDA (OSCTRL),Y ; Read from buffer in aux mem
STA SYSCLOCK,Y ; Store to sys clock in main mem STA SYSCLOCK,Y ; Store to sys clock in main mem
INY INY
CPY #$05 CPY #$05
BCC :WORD02LP BCC :WORD02LP
STA WRCARDRAM ; Writes back to aux memory STZ WRCARDRAM ; Writes back to aux memory
RTS RTS
WORD03 WORD03

26
auxmem.misc.s
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@ -351,9 +351,9 @@ ROMSELOK PLP
* Initialize ROMTAB according to user selection in menu * Initialize ROMTAB according to user selection in menu
ROMINIT STZ MAXROM ; One sideways ROM only ROMINIT STZ MAXROM ; One sideways ROM only
STA RDMAINRAM ; Read main mem >>> RDMAIN ; Read main mem
LDA USERSEL ; *TO DO* Should be actual number of ROMs LDA USERSEL ; *TO DO* Should be actual number of ROMs
STA RDCARDRAM ; Read aux mem >>> RDAUX ; Read aux mem
CMP #6 CMP #6
BNE :X1 BNE :X1
@ -380,16 +380,6 @@ GSBRKAUX >>> IENTAUX ; IENTAUX does not do CLI
IRQBRKHDLR PHA IRQBRKHDLR PHA
* Mustn't enable IRQs within the IRQ handler * Mustn't enable IRQs within the IRQ handler
* Do not use WRTMAIN/WRTAUX macros * Do not use WRTMAIN/WRTAUX macros
* LDA RDRAMRD ; Record softswitch state
* STA $90
* LDA RDRAMWR
* STA $91
*
* STA WRMAINRAM ; Write to main memory
* STA $45 ; $45=A for ProDOS IRQ handlers
* STA WRCARDRAM ; Write to aux memory
* STA RDCARDRAM ; Read from aux memory
PHX PHX
CLD CLD
TSX TSX
@ -422,18 +412,6 @@ IRQBRKRET
PLY PLY
* LDA $90 ; Restore state of RAMRD
* BMI :S1
* STA RDMAINRAM
* BRA :S2
*:S1 STA RDCARDRAM
*
*:S2 LDA $91 ; Restore state of RAMWRT
* BMI :S3
* STA WRMAINRAM
* BRA :S4
*:S3 STA WRCARDRAM
*:S4 ; TODO: Pass on to IRQ1V *:S4 ; TODO: Pass on to IRQ1V
PLX PLX
PLA PLA

28
auxmem.vdu.s
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@ -399,9 +399,9 @@ GETCHRC JSR CHARADDR ; Find character address
BIT VDUBANK BIT VDUBANK
BMI GETCHRGS BMI GETCHRGS
BCC GETCHR6 ; Aux memory BCC GETCHR6 ; Aux memory
STA RDMAINRAM ; Read main memory STZ RDMAINRAM ; Read main memory (IRQs off)
GETCHR6 LDA (VDUADDR),Y ; Get character GETCHR6 LDA (VDUADDR),Y ; Get character
STA RDCARDRAM ; Read aux memory STZ RDCARDRAM ; Read aux memory
TAY ; Convert character TAY ; Convert character
AND #$A0 AND #$A0
BNE GETCHR7 BNE GETCHR7
@ -414,9 +414,9 @@ GETCHR7 TYA
TAX ; X=char TAX ; X=char
GETCHROK RTS GETCHROK RTS
GETCHRGS BCC GETCHR8 ; Aux memory GETCHRGS BCC GETCHR8 ; Aux memory
STA RDMAINRAM ; Read main memory STZ RDMAINRAM ; Read main memory (IRQs off)
GETCHR8 LDA [VDUADDR],Y ; Get character GETCHR8 LDA [VDUADDR],Y ; Get character
STA RDCARDRAM ; Read aux memory STZ RDCARDRAM ; Read aux memory
TAY ; Convert character TAY ; Convert character
AND #$A0 AND #$A0
BNE GETCHR9 BNE GETCHR9
@ -812,10 +812,10 @@ DOSCR1LINE INC TXTWINRGT
STA (VDUADDR2),Y STA (VDUADDR2),Y
BRA :SKIPMAIN BRA :SKIPMAIN
:MAIN >>> WRTMAIN :MAIN >>> WRTMAIN
STA RDMAINRAM ; Read main memory STZ RDMAINRAM ; Read main memory (IRQs off)
LDA (VDUADDR),Y LDA (VDUADDR),Y
STA (VDUADDR2),Y STA (VDUADDR2),Y
STA RDCARDRAM ; Read aux memory STZ RDCARDRAM ; Read aux memory
>>> WRTAUX >>> WRTAUX
:SKIPMAIN INX :SKIPMAIN INX
CPX TXTWINRGT CPX TXTWINRGT
@ -824,10 +824,10 @@ DOSCR1LINE INC TXTWINRGT
:FORTY TXA :FORTY TXA
TAY TAY
:L2 >>> WRTMAIN :L2 >>> WRTMAIN
STA RDMAINRAM ; Read main memory STZ RDMAINRAM ; Read main memory (IRQs off)
LDA (VDUADDR),Y LDA (VDUADDR),Y
STA (VDUADDR2),Y STA (VDUADDR2),Y
STA RDCARDRAM ; Read aux memory STZ RDCARDRAM ; Read aux memory
>>> WRTAUX >>> WRTAUX
INY INY
CPY TXTWINRGT CPY TXTWINRGT
@ -847,20 +847,20 @@ SCR1LINEGS LDX TXTWINLFT
STA VDUBANK STA VDUBANK
STA VDUBANK2 STA VDUBANK2
>>> WRTMAIN >>> WRTMAIN
STA RDMAINRAM ; Read main memory STZ RDMAINRAM ; Read main memory (IRQs off)
LDA [VDUADDR],Y ; Even cols in bank $E1 LDA [VDUADDR],Y ; Even cols in bank $E1
STA [VDUADDR2],Y STA [VDUADDR2],Y
STA RDCARDRAM ; Read aux memory STZ RDCARDRAM ; Read aux memory
>>> WRTAUX >>> WRTAUX
BRA :SKIPE0 BRA :SKIPE0
:E0 LDA #$E0 :E0 LDA #$E0
STA VDUBANK STA VDUBANK
STA VDUBANK2 STA VDUBANK2
>>> WRTMAIN >>> WRTMAIN
STA RDMAINRAM ; Read main memory STZ RDMAINRAM ; Read main memory (IRQs off)
LDA [VDUADDR],Y ; Odd cols in bank $E0 LDA [VDUADDR],Y ; Odd cols in bank $E0
STA [VDUADDR2],Y STA [VDUADDR2],Y
STA RDCARDRAM ; Read aux memory STZ RDCARDRAM ; Read aux memory
>>> WRTAUX >>> WRTAUX
:SKIPE0 INX :SKIPE0 INX
CPX TXTWINRGT CPX TXTWINRGT
@ -871,10 +871,10 @@ SCR1LINEGS LDX TXTWINLFT
LDA #$E0 LDA #$E0
STA VDUBANK STA VDUBANK
:L2 >>> WRTMAIN :L2 >>> WRTMAIN
STA RDMAINRAM ; Read main memory STZ RDMAINRAM ; Read main memory (IRQs off)
LDA [VDUADDR],Y LDA [VDUADDR],Y
STA [VDUADDR2],Y STA [VDUADDR2],Y
STA RDCARDRAM ; Read aux memory STZ RDCARDRAM ; Read aux memory
>>> WRTAUX >>> WRTAUX
INY INY
CPY TXTWINRGT CPY TXTWINRGT