From 9da8399e6aa2e7dd1eb30d7038ec75a7991727da Mon Sep 17 00:00:00 2001 From: Bobbi Webber-Manners Date: Mon, 19 Sep 2022 23:42:44 -0400 Subject: [PATCH] Mainmem code shouldn't use WRTMAIN/WRTAUX macros. --- mainmem.misc.s | 4 ++-- mainmem.svc.s | 8 ++++---- 2 files changed, 6 insertions(+), 6 deletions(-) diff --git a/mainmem.misc.s b/mainmem.misc.s index 5a3ce71..2a49cc3 100644 --- a/mainmem.misc.s +++ b/mainmem.misc.s @@ -98,12 +98,12 @@ EXISTS LDA #>> WRTAUX ; Write to Aux mem + STA $C005 ; Write to aux mem :L1 LDA FILEBLK,X STA OSFILECB,X DEX BPL :L1 - >>> WRTMAIN ; Back to Main mem + STA $C004 ; Write to main mem again PLA RTS diff --git a/mainmem.svc.s b/mainmem.svc.s index 49c9f73..176309d 100644 --- a/mainmem.svc.s +++ b/mainmem.svc.s @@ -359,9 +359,9 @@ GBPB >>> ENTMAIN LDA GBPBDAT+1 STA ZPMOS+1 LDA BLKBUF - >>> WRTAUX + STA $C005 ; Write to aux STA (ZPMOS) ; Store byte in aux mem - >>> WRTMAIN + STA $C004 ; Write to main again BRA :UPDCB :WRITE LDA #>> ENTMAIN :ERR :ZERO PLA ; Throw away A >>> ALTZP ; Control block can be in ZP! - >>> WRTAUX + STA $C005 ; Write to aux LDA GBPBAUXCB+0 ; Copy control block back to aux STA $B0+0 ; $B0 in AltZP is temp FS workspace LDA GBPBAUXCB+1 @@ -413,7 +413,7 @@ GBPB >>> ENTMAIN STA ($B0),Y DEY BPL :L2 - >>> WRTMAIN + STA $C004 ; Write to main again >>> MAINZP >>> XF2AUX,OSGBPBRET