Ticket #160: IRQ/BRK hdlr restores GS to speed at Applecorn start.
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applecorn.po
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applecorn.po
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@ -126,6 +126,10 @@ MOSHIGH SEI ; Disable IRQ while initializing
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DEX
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BPL :INITPG2
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LDA $C036 ; GS speed register
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AND #$80 ; Speed bit only
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STA GSSPEED ; In Alt LC for IRQ/BRK hdlr
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JSR ROMINIT ; Build list of sideways ROMs
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JSR KBDINIT ; Returns A=startup MODE
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JSR VDUINIT ; Initialise VDU driver
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@ -205,8 +209,9 @@ BYTE00 BEQ BYTE00A ; OSBYTE 0,0 - generate error
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RTS ; %000x1xxx host type, 'A'pple
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BYTE00A BRK
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DB $F7
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HELLO ASC 'Applecorn MOS 2022-09-22'
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HELLO ASC 'Applecorn MOS 2022-09-23'
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DB $00 ; Unify MOS messages
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GSSPEED DB $00 ; $80 if GS is fast, $00 for slow
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@ -562,9 +562,13 @@ IRQBRKHDLR PHA
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STA $45 ; $45=A for ProDOS IRQ handlers
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BPL :S1 ; If aux write wasn't active, skip
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STA $C005 ; Write to aux memory
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LDA #$80
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TSB $C036 ; For GS: Enable 'fast' speed
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:S1 TXA
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:S1 LDA GSSPEED ; See if GS was set to 2.8MHz
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CMP #$80
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BNE :S2 ; Nope, continue slow
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TSB $C036 ; GS: Enable 'fast' speed
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:S2 TXA
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PHA
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CLD
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TSX
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