diff --git a/applecorn.po b/applecorn.po
index 2dcabf5..4e3b1db 100644
Binary files a/applecorn.po and b/applecorn.po differ
diff --git a/auxmem.init.s b/auxmem.init.s
index e689bcb..57328ee 100644
--- a/auxmem.init.s
+++ b/auxmem.init.s
@@ -126,6 +126,10 @@ MOSHIGH     SEI                              ; Disable IRQ while initializing
             DEX
             BPL   :INITPG2
 
+            LDA   $C036                      ; GS speed register
+            AND   #$80                       ; Speed bit only
+            STA   GSSPEED                    ; In Alt LC for IRQ/BRK hdlr
+
             JSR   ROMINIT                    ; Build list of sideways ROMs
             JSR   KBDINIT                    ; Returns A=startup MODE
             JSR   VDUINIT                    ; Initialise VDU driver
@@ -205,8 +209,9 @@ BYTE00      BEQ   BYTE00A                    ; OSBYTE 0,0 - generate error
             RTS                              ; %000x1xxx host type, 'A'pple
 BYTE00A     BRK
             DB    $F7
-HELLO       ASC   'Applecorn MOS 2022-09-22'
+HELLO       ASC   'Applecorn MOS 2022-09-23'
             DB    $00                        ; Unify MOS messages
+GSSPEED     DB    $00                        ; $80 if GS is fast, $00 for slow
 
 
 
diff --git a/auxmem.misc.s b/auxmem.misc.s
index 127682f..01c3529 100644
--- a/auxmem.misc.s
+++ b/auxmem.misc.s
@@ -562,9 +562,13 @@ IRQBRKHDLR  PHA
             STA   $45                ; $45=A for ProDOS IRQ handlers
             BPL   :S1                ; If aux write wasn't active, skip
             STA   $C005              ; Write to aux memory
-            LDA   #$80
-            TSB   $C036              ; For GS: Enable 'fast' speed
-:S1         TXA
+            
+:S1         LDA   GSSPEED            ; See if GS was set to 2.8MHz
+            CMP   #$80
+            BNE   :S2                ; Nope, continue slow
+            TSB   $C036              ; GS: Enable 'fast' speed
+
+:S2         TXA
             PHA
             CLD
             TSX