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Reset Ensoniq on Ctrl-Reset. Fixes #185.
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applecorn.po
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applecorn.po
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@ -213,7 +213,7 @@ BYTE00 BEQ BYTE00A ; OSBYTE 0,0 - generate error
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RTS ; %000x1xxx host type, 'A'pple
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RTS ; %000x1xxx host type, 'A'pple
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BYTE00A BRK
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BYTE00A BRK
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DB $F7
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DB $F7
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HELLO ASC 'Applecorn MOS 2022-11-03'
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HELLO ASC 'Applecorn MOS 2022-11-04'
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DB $00 ; Unify MOS messages
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DB $00 ; Unify MOS messages
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* TO DO: Move into RAM
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* TO DO: Move into RAM
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GSSPEED DB $00 ; $80 if GS is fast, $00 for slow
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GSSPEED DB $00 ; $80 if GS is fast, $00 for slow
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@ -15,6 +15,7 @@ A2IRQ >>> IENTMAIN ; IENTMAIN does not do CLI
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A2IRQ2 PHP ; Fake things to look like IRQ
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A2IRQ2 PHP ; Fake things to look like IRQ
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JMP (A2IRQV) ; Call Apple II ProDOS ISR
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JMP (A2IRQV) ; Call Apple II ProDOS ISR
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* BRK handler in main memory. Used on Apple IIgs only.
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* BRK handler in main memory. Used on Apple IIgs only.
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GSBRK >>> XF2AUX,GSBRKAUX
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GSBRK >>> XF2AUX,GSBRKAUX
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@ -27,8 +28,14 @@ RESET TSX
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LDA AN1OFF ; AN1 off
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LDA AN1OFF ; AN1 off
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LDA AN2ON ; AN2 on
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LDA AN2ON ; AN2 on
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LDA AN3ON ; AN3 on
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LDA AN3ON ; AN3 on
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JSR RESETHW ; Reset hardware
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>>> XF2AUX,AUXMOS
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>>> XF2AUX,AUXMOS
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RTS
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* Reset hardware
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RESETHW SEC
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JSR IDROUTINE ; See if this is a GS
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BCS :NOTGS
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JSR ENSQINIT ; Initialize Ensoniq
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:NOTGS RTS
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@ -111,12 +111,9 @@ DISCONN LDA MACHID
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STA DEVADR32+1
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STA DEVADR32+1
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DEC DEVCNT
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DEC DEVCNT
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:S1 SEC
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:S1 JSR ROMMENU ; This really needs to happen elsewhere
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JSR IDROUTINE ; See if we have a GS
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BCS :NOTGS
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JSR ENSQINIT ; Initialize Ensoniq
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:NOTGS JSR ROMMENU ; This really needs to happen elsewhere
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JSR RESETHW ; Reset any hardware required
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LDA #<:FDFILE
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LDA #<:FDFILE
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STA OPENPL+1
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STA OPENPL+1
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