mirror of https://github.com/markpmlim/EdAsm.git
1590 lines
45 KiB
ArmAsm
1590 lines
45 KiB
ArmAsm
Name : BB2.S
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End of file : 27,417
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This file was generated using the DiskBrowser utility with minimal editing.
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It is meant for viewing purposes only.
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;=================================================
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; Execute BI commands
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;
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DOTCMD JSR SwapZP
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BIT TXTSET
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BIT TXTPAGE1
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LDA #$00 ;Set to full text screen
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; STA CH
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DB $8D,$24,00 ;This should ensure
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; STA WNDLFT
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DB $8D,$20,00 ; the assembled copy
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; STA WNDTOP
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DB $8D,$22,00 ; is an exact image of
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LDA #40
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; STA WNDWDTH ; the original program
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DB $8D,$21,00
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LDA #24
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; STA WNDBTM
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DB $8D,$23,00
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LDA #23
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; STA CV
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DB $8D,$25,00
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;
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LDA #>SLIN23
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; STA BASL
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DB $8D,$28,00
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LDA #<SLIN23
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; STA BASH
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DB $8D,$29,00
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LDA #CR
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JSR COUT2
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;
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LDY #1 ;Skip the dot
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L0D1D LDA IBuff,Y ;Copy user's input
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STA INBUF-1,Y
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INY
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CPY INPUTLEN
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BNE L0D1D
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;
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LDA #CR ;Append a CR
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STA INBUF-1,Y
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JSR DOSCMD ;Let BI take care of it
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BCC L0D36
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JSR PRINTERR
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;
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L0D36 LDA #$60 ;Flashing cursor
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STA (BASL),Y
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WAITK3 BIT KBD ; while we wait for
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BPL WAITK3 ; a keypress
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STA KBDSTROBE
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JMP WrmStrt
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;=================================================
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; ($0D45) A=$xx, X=$xx, PC=$xxxx
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;
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SETREG JSR Hex2Bin
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BCC L0D4D
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L0D4A JMP InputErr
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;
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L0D4D LDA Z3E ;value
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LDX Z40
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CPX #5
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BEQ SetRate
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CPX #6
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BEQ SetPC
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CPX #7
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BEQ SetCyc
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STA CPURegs,X ;(X)=0-4
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BNE L0D93 ;always
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;
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SetRate STA KBDRate
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STA RATEC
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ROR SW06
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BMI L0D93
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;
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SetPC STA MONPC
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LDA Z3E+1
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STA MONPC+1
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BCS L0D93 ;always
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;
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SetCyc STA CYCLEC
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LDA Z3E+1
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STA CYCLEC+1
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BCS L0D93 ;always
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;=================================================
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; O=A, O=E etc
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;
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SETOPT LDA IBuff,Y
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JSR ToUpper
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LDX #6
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L0D86 CMP OPTSK,X
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BEQ L0D90 ;Got a hit
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DEX
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BPL L0D86
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BMI L0D4A ;always
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;
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L0D90 STX L2100 ;0-6 - Display option
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L0D93 JMP L0922 ;Update SDs & get next cmd
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;=================================================
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; Execute at full speed starting fr specified addr
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; Encoutering a RTS, BRK or BP will force BB to
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; return to cmd level
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; pg 163-164
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;
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GKEY1 LDA Z3E
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STA SVxZ3A
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LDA Z3E+1
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STA SVxZ3A+1
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;
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; G cmd w/o starting addr. The last starting addr
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; specified with a SS,TR or G will be used
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;
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XSUBRCMD EQU *
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BIT MasDSW
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BPL L0DA8
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JSR L0E07 ;Update SDs
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;
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L0DA8 SEC
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ROR ExecSW
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LDX SAVES
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TXS
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JSR SwapZP
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JSR RstRegs
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JSR GoFullSpd ;Execute subrtn
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JSR SavRegs
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JMP WrmStrt ;Back to cmd level
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;
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; J cmd w/o starting addr
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; This cmd could be used to continue executing a program after a BP
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; has forced BB out of Execution Mode. However, no return addr is
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; pushed onto the stack
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;
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JUMPCMD SEC
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ROR ExecSW
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JSR L0E07 ;Update SDs
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JMP L1058
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;
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; Execute code with real break points starting with specified addr
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; A return addr is pushed onto stack
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;
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JKEY1 LDA Z3E
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STA SVxZ3A
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LDA Z3E+1
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STA SVxZ3A+1
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BIT MasDSW ;Update Master Display?
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BPL L0DDB ;No
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JSR L0E07 ;Update SDs
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;
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L0DDB SEC
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ROR ExecSW
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JSR SwapZP
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LDX SAVES
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TXS
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JSR RstRegs
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;
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GoFullSpd JMP (SVxZ3A) ;Exec at full speed
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;=================================================
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; Clear Code Disassembly and Break Point SD
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;
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L0DEC LSR SW13 ;Clear these switches
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LSR RTSSW
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LSR SSSW
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LSR ExecSW
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;
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LDA #10
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STA L2112 ;WndLft
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LDA #39
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STA L2113 ;WndRht
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ASL CodeDSW ;Do we clear CD SD?
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BCC L0E0A ;No (NB. msb=0 at the same time)
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;
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L0E07 JSR L1803 ;Redraw CD SD
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;
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L0E0A ASL BPDSW ;Do we clear BP SD also?
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BCC L0E12 ;No
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JSR L180F ;Clear BP SD
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;
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L0E12 JMP L1719 ;Redraw BP window
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;=================================================
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; ($0E15) Single Step mode with transparent BP's
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;
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; Re-enter into Single Step mode w/o specifying a starting addr
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; BB remembers the last inst it executed b4 leaving trace
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; or single step mode and continues fr the next inst whenever
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; user re-enter trace/single step mode
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;
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SSTEPCMD JSR L0DEC ;Setup & update Code/BP SDs
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SEC
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ROR SSSW
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JSR DSSTEP
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JMP L103D
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;
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SKEY1 JSR L0DEC ;Start fr specified addr
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JSR DSSTEP
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LDA #$80
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STA SSSW
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BNE L0E3E ;always
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;=================================================
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; Trace mode with transparent BP's
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;
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; Re-enter into Trace mode w/o specifying a starting addr
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;
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TRACECMD JSR L0DEC ;Setup & update Code/BP SDs
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JSR DTRACE
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JMP L103D
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;
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TKEY1 JSR L0DEC ;Start fr specified addr
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JSR DTRACE
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;
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; Common code for SS/TR with a specified addr
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;
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L0E3E JSR L1803 ;Clear Code SD
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LDA Z3E ;Addr already converted &
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STA MONPC
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LDA Z3E+1 ; stored here temporarily
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STA MONPC+1
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;
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L0E49 LDY #0
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LDA (MONPC),Y ;Get opcode @ this addr
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BNE L0E75 ;Not a BRK inst
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BIT BRKFLAG ;IN?
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BPL L0E75 ;No
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JSR L18B4 ;Is it in our list of BP's?
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BMI L0E75 ;No
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;
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; Since real BPs are IN, BB will operate as
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; if real BPs are OUT during a TRACE
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;
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L0E59 TXA ;Form an index
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ASL
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ASL
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TAY ; in Y-reg
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LDX #0
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STX TrigSW
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L0E62 LDA L088F,Y ;Get original inst & format
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STA INSTSV,X ; for this BP & store it here
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INY
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INX
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CPX #4
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BNE L0E62
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;
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AND #%000000011 ;Isolate len bits fr the
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STA INSTLEN ; addr mode format bits
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BCS L0E78 ;always
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;
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L0E75 JSR INSDIS ;Get format & length of instr @ PC
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;
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L0E78 LDA #iNOP ;Make sure area is filled
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STA INSTBE+1 ; with $EA in case inst len
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STA INSTBE+2 ; is 1-2 bytes long
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LDY INSTLEN ;Length
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STY L20F2
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LDA INSTFMT ;Format
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STA L20F1
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;
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L0E8C LDA INSTSV,Y ;Move inst to soon-
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STA INSTBE,Y ; -to-be executed area
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DEY
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BPL L0E8C
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;
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BIT MasDSW ;Do we update the Master Display?
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BPL L0EE3 ;No
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;
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LDX CDBar ;Highlight next-to-be-exec inst
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JSR VTABX
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STX Z3E
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LDA #$20 ;ASCII space
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JSR ClrEOLI ;Inverse the scrn line
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JSR INSTDSP
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JSR InvLine
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JSR DMONPC
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;
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LDX L2109
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BMI L0EE3 ;-1 -> no-yet-to-be-executed inst
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STX Z3E+1 ;1 -> 2 yet-to-be-executed inst displayed
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JSR SVMONPC
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LDA AdrModSW ;(Is this for the next-to-be-exec inst?)
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PHA
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;
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L0EBE JSR PCADJ
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STA MONPC
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STY MONPC+1
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JSR INSDIS ;Get format & len of instr
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INC Z3E
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LDX Z3E
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JSR VTABX
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JSR ClrEOL
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JSR INSTDSP ;Show disassembled inst
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DEC Z3E+1
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BPL L0EBE ;next yet-to-be-executed-inst
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;
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PLA
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STA AdrModSW
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JSR RSTMONPC
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JSR L1624 ;Copy INSTBE data to INSTSV area
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;
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L0EE3 BIT TrigSW
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BPL L0EF2
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BIT BRKFLAG ;IN?
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BMI L0F3C ;Yes
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JSR L18B4 ;Chk if it's one of ours
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BMI L0F3C ;No hit
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;
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; BB has encountered an inst located @ a BP addr
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;
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L0EF2 LDA #$80
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STA TrigSW
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LDX BPHitM1
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INC BPCntL,X
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BNE L0F02
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INC BPCntH,X
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;
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L0F02 LDA BPTrigL,X ;If trigger = count
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CMP BPCntL,X
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BNE L0F2C
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LDA BPTrigH,X
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CMP BPCntH,X
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BNE L0F2C
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INC BPBrkL,X ; incr BROKE cntr
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BNE L0F1A
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INC BPBrkH,X
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;
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; Stops program execution b4 executing the inst @ the BP addr.
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; BB will highlight the row in the BP SD that corresponds to
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; the breakpoint that was triggered
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;
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L0F1A LDA #$80 ;Flag we have to update BP SD
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STA BPDSW
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ASL ;(A)=0
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STA BPCntL,X ;Clears the count
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STA BPCntH,X
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JSR BELL2
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JMP L1060 ;Back to cmd level
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;
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L0F2C BIT MasDSW
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BPL L0F34
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JSR L173A ;Update BP SD
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;
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L0F34 BIT ExecSW
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BPL L0F3C
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JMP L1058
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;
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; During Trace mode, instead of using the keyboard, user can use
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; Paddle Button 0 to control the tracing. To do this, user
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; must set Btn0SW to $80 b4 entering trace mode.
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; Ref pg 168
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;
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L0F3C BIT Btn0SW ;Use Paddle Button 0 to suspend tracing?
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BPL L0F46 ;No
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BIT BUTN0
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BMI L0F3C ;Loop until paddle 0 is released
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;
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; NB. User's program will never receive any keystroke unless
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; BB's keyboard polling is turned off.
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; To turn off keyboard polling, set (KBDPOLL) to $80+ASCII char.
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; BB will ignore all chars typed at keyboard except this special
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; interrupt char which the user had specified.
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; ref pg 167
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;
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L0F46 BIT KBDPOLL ;Is polling off?
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BPL L0F5B ;No, allow user's program to accept keystroke
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LDA KBD ;Is there a keypress?
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BPL L0F76 ;No
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CMP KBDPOLL ;Yes, is it the interrupt char?
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BNE L0F76 ;No
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STA KBDSTROBE ;Yes, clear keyboard ready flag
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;
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ExitDbg JMP L1060 ;Stop SS/TR & transfer back to BB's cmd level
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;
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L0F5B BIT SSSW
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BPL ChkKS
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L0F60 LDA #$C0 ;Set values for noise generation
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STA IMM2+1
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LDA #$02
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STA IMM3+1
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WAITK5 LDA KBD
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BPL WAITK5
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CMP #SPACE
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BNE ChkKS2
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STA KBDSTROBE
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;
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L0F76 LDA #$10 ;Set sound delay
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STA IMM2+1
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STA IMM3+1
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L0F7E JMP L103D
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;
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; These keystrokes are checked during Single Step or Trace modes
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;
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ChkKS LDA KBD
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BPL L0F7E
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ChkKS2 STA KBDSTROBE
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CMP #ESC ;Did user ask for a ret to cmdline?
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BEQ ExitDbg ;Yes, exit debugging
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CMP #SPACE ;Did user ask for a single step?
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BEQ ExecSS ;yes
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CMP #CR
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BEQ L0FE2
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CMP #'1' ;Did user ask to display primary Apple screen?
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BEQ DTxtPg1
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CMP #'2' ;Did user ask to display secondary Apple screen?
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BEQ DTxtPg2
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JSR ToUpper
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CMP #'T' ;Did user ask to display text screen?
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BEQ DTxtScr
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;
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CMP #'L' ;Did user ask to display lores graphic screen?
|
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BEQ DLoResGr
|
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CMP #'H' ;Did user ask to display hires graphic screen?
|
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BEQ DHiResGr
|
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CMP #'F' ;Did user ask to display full screen graphics?
|
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BEQ DFullGr
|
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CMP #'M' ;Did user ask to display mixed text & graphics?
|
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BEQ DMixGr
|
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;
|
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CMP #'Q' ;Did user ask to turn off the sound?
|
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BEQ SNDOFF
|
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CMP #'S' ;Did user ask to turn on the sound?
|
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BEQ SNDON
|
|
;
|
|
CMP #'R'
|
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BEQ Tr2RTS
|
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;
|
|
CMP #'K' ;key board to adjust trace rate
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BEQ UseKR
|
|
CMP #'P'
|
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BEQ UsePdl0 ;game paddle to adjust trace rate
|
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;
|
|
CMP #'C' ;Did user ask to clear cycle counter?
|
|
BEQ ClrCC
|
|
CMP #CURSR ;Did user ask to skip next instruction?
|
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BNE SkipNxtI
|
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;
|
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STA SSSW
|
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STA SW13 ;Flag "skip next inst"s
|
|
JSR DSSTEP ;Display "SINGLE STEP"
|
|
JMP L123B
|
|
;
|
|
Tr2RTS ROR RTSSW ;Trace until RTS
|
|
JSR DWAIRTS
|
|
;
|
|
; Do trace until BP encountered or end of program
|
|
;
|
|
L0FE2 JSR DTRACE
|
|
LSR SSSW ;Clear SS mode
|
|
BPL SkipNxtI ;always
|
|
;
|
|
ExecSS JSR DSSTEP
|
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SEC
|
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ROR SSSW
|
|
BMI SkipNxtI ;always
|
|
;
|
|
DTxtPg1 STA TXTPAGE1
|
|
BEQ SkipNxtI
|
|
DTxtPg2 STA TXTPAGE2
|
|
BEQ SkipNxtI ;always
|
|
;
|
|
DTxtScr STA TXTSET
|
|
BEQ SkipNxtI
|
|
DLoResGr STA LORES
|
|
STA TXTCLR
|
|
BEQ SkipNxtI
|
|
DHiResGr STA HIRES
|
|
STA TXTCLR
|
|
BEQ SkipNxtI
|
|
DFullGr STA MIXCLR
|
|
BEQ SkipNxtI
|
|
DMixGr STA MIXSET
|
|
BEQ SkipNxtI
|
|
;
|
|
SNDOFF LDA #$00
|
|
SNDON STA SNDSW
|
|
BEQ SkipNxtI
|
|
;
|
|
ClrCC LDA #$00
|
|
STA CYCLEC
|
|
STA CYCLEC+1
|
|
JSR DBBREGS
|
|
BNE SkipNxtI ;always
|
|
;
|
|
; $80 use KBD rate, $00=game paddle to control rate
|
|
;
|
|
UsePdl0 LDA #$00 ;Use paddle
|
|
UseKR STA SW06
|
|
;
|
|
; Skip next inst
|
|
;
|
|
SkipNxtI BIT SSSW ;Single Step?
|
|
BPL L103D ;No
|
|
JMP L0F60
|
|
;
|
|
L103D BIT SNDSW ;Make some noise?
|
|
BPL L1058 ;No
|
|
IMM2 LDX #$C0
|
|
IMM3 LDY #$02
|
|
LDA SPKR
|
|
L1049 INX
|
|
BEQ L1058 ;->done
|
|
NOP
|
|
JMP L1050
|
|
L1050 DEY
|
|
BEQ IMM3
|
|
JMP L1056
|
|
L1056 BNE L1049 ;always
|
|
;
|
|
L1058 BIT AdrModSW ;Is inst valid i.e. opcode defined?
|
|
BMI L1069 ;Yes
|
|
JMP L123B ;->???
|
|
;
|
|
L1060 STA TXTSET ;Exit
|
|
STA TXTPAGE1
|
|
JMP L0922 ;Update SDs & get next cmd
|
|
;
|
|
; NB. (A) may be a random value
|
|
;
|
|
L1069 LDX HSTAKP
|
|
LDY INSTBE ;Get opcode
|
|
BEQ L1060 ;BRK -> back to cmd level
|
|
;
|
|
CPY #iRTI
|
|
BEQ L10AB
|
|
CPY #iRTS
|
|
BEQ L10B2
|
|
CPY #iJMP
|
|
BEQ L10D9
|
|
;
|
|
LDA #$00
|
|
CPY #$6C ;JMP (ABSOLUTE)
|
|
BEQ L10DA
|
|
LDA HXREG
|
|
CPY #$7C ;JMP (ABSOLUTE,X) - new addressing mode
|
|
BEQ L10DA
|
|
;
|
|
CPY #$BA ;TSX
|
|
BEQ L1104
|
|
CPY #$9A ;TXS
|
|
BEQ L110B
|
|
;
|
|
CPY #iJSR
|
|
BEQ L1110
|
|
;
|
|
TYA
|
|
AND #%01011111
|
|
CMP #$5A ;PHY,PLY,PHX,PLX?
|
|
BNE L109E ;No
|
|
JMP L1194
|
|
;
|
|
L109E TYA
|
|
AND #%10011111
|
|
CMP #$08 ;PHP,PLP,PHA,PLA
|
|
BEQ L10A8
|
|
JMP L11F0 ;BR insts
|
|
L10A8 JMP L11B2
|
|
; RTI inst
|
|
L10AB CLC
|
|
INX
|
|
LDA STACK,X
|
|
STA HFLAGS
|
|
; RTS inst
|
|
L10B2 BIT RTSSW ;Wait for RTS?
|
|
BPL L10C1 ;No
|
|
CLC
|
|
ROR RTSSW ;Clear
|
|
JSR L1F98 ;Remove "AWAITING RTS" msg
|
|
JMP ExecSS
|
|
;
|
|
L10C1 INX
|
|
LDA STACK,X ;Get the ret addr
|
|
STA MONPC
|
|
INX
|
|
LDA STACK,X
|
|
STA MONPC+1
|
|
STX HSTAKP
|
|
PHP
|
|
JSR L14C3 ;Update Stack SD
|
|
PLP
|
|
BCC L1101 ;Was RTI inst
|
|
JMP L123B
|
|
;
|
|
; JMP instructions handler
|
|
; If inst is JMP abs, (A) is irrelevant
|
|
;
|
|
L10D9 CLC ;JMP abs
|
|
L10DA TAY ;JMP (abs) or JMP (abs,X)
|
|
LDA INSTBE+1
|
|
LDX INSTBE+2
|
|
STA MONPC
|
|
STX MONPC+1
|
|
BCC L1101 ;JMP abs
|
|
;
|
|
; JMP indirect modes
|
|
; (Y)=0 if JMP (abs)
|
|
; (Y)=(HXREG) if JMP (abs,X)
|
|
;
|
|
JSR SVMONPC
|
|
TYA
|
|
PHA
|
|
JSR SwapZP
|
|
PLA
|
|
CLC
|
|
ADC SVxZ3A
|
|
LDX SVxZ3A+1
|
|
BCC L10FA
|
|
INX
|
|
;
|
|
L10FA JSR L13DD
|
|
STA MONPC
|
|
STX MONPC+1
|
|
L1101 JMP L1242
|
|
;
|
|
L1104 LDA HSTAKP ;TSX
|
|
STA HXREG
|
|
JMP L123B
|
|
;
|
|
L110B LDX HXREG ;TXS
|
|
JMP L11D8
|
|
;
|
|
; NB. We are still in simulation mode
|
|
; This part of the code allows user to
|
|
; execute ProDOS calls in real time
|
|
;
|
|
L1110 LDY INSTBE+2 ;JSR
|
|
LDA INSTBE+1
|
|
BNE L1148 ;Addr is not @ mem page bdry
|
|
BIT XUNDSW ;Allow execution of ProDOS calls?
|
|
BPL L1148 :No
|
|
CPY #$BF ;Is ProDOS Global Page
|
|
BNE L1148 ;No
|
|
;
|
|
LDY #5
|
|
L1123 LDA (MONPC),Y
|
|
STA L113F,Y ;Self-modifying code
|
|
DEY
|
|
CPY #2
|
|
BNE L1123
|
|
;
|
|
LDA MONPC
|
|
CLC
|
|
ADC #3
|
|
STA MONPC
|
|
BCC L1138
|
|
INC MONPC+1
|
|
;
|
|
L1138 TXS
|
|
JSR SwapZP
|
|
JSR RstRegs
|
|
L113F JSR PRODOS8
|
|
DB 0
|
|
DW 0
|
|
JMP L1172
|
|
;
|
|
; This part of the BB's code allows the user to execute code in
|
|
; real time while in Simulation mode. It checks if the instr is
|
|
; within the specified Real Time Code region
|
|
;
|
|
L1148 CPY BARTC+1 ;Is (Y,A) btwn (BARTC)
|
|
BCC L117B
|
|
BNE L1162
|
|
CMP BARTC
|
|
BCC L117B
|
|
;
|
|
CPY EARTC+1 ; and (EARTC)?
|
|
BCC L1162
|
|
BNE L117B
|
|
CMP EARTC
|
|
BCC L1162 ;Yes
|
|
BNE L117B
|
|
;
|
|
; Execute code in real time
|
|
;
|
|
L1162 STY SVxZ3A+1 ;Set up the JMP addr
|
|
STA SVxZ3A
|
|
TXS
|
|
JSR SwapZP
|
|
JSR RstRegs
|
|
JSR GoFullSpd ;xfer control to code
|
|
;
|
|
L1172 JSR SavRegs
|
|
LDX #>BBStack ;Reset BB's stack area $100-$1FF
|
|
TXS
|
|
JMP L1238
|
|
;
|
|
; Simulation mode
|
|
;
|
|
L117B CLC
|
|
JSR PCADJ2 ;(Y,A)-effective addr
|
|
LDX HSTAKP
|
|
PHA
|
|
TYA
|
|
STA STACK,X ;Save (Y) and (A) here
|
|
DEX
|
|
PLA
|
|
STA STACK,X
|
|
DEX
|
|
STX HSTAKP
|
|
JSR L14C3 ;Update Stack SD
|
|
JMP L10D9
|
|
;
|
|
; PHY,PLY,PHX,PLX
|
|
;
|
|
L1194 TYA
|
|
ASL
|
|
AND #%01000000
|
|
BNE L11A4
|
|
BCC L11A0
|
|
LDA HXREG ;PHX
|
|
BCS L11BF ;always
|
|
;
|
|
L11A0 LDA HYREG ;PHY
|
|
BCC L11BF
|
|
;
|
|
L11A4 INX
|
|
LDA STACK,X
|
|
BCC L11AE
|
|
STA HXREG ;PLX
|
|
BCS L11CE ;always
|
|
L11AE STA HYREG ;PLY
|
|
BCC L11CE ;always
|
|
;
|
|
; PHP,PLP,PHA,PLA
|
|
;
|
|
L11B2 TYA
|
|
ASL
|
|
ASL
|
|
BMI L11C6 ;PLP/PLA
|
|
BCC L11BD ;PHP
|
|
LDA HACCUM ;PHA
|
|
BCS L11BF ;always
|
|
;
|
|
L11BD LDA HFLAGS
|
|
L11BF STA STACK,X
|
|
DEX
|
|
JMP L11D8 ;-> adjust SP
|
|
;
|
|
L11C6 INX
|
|
LDA STACK,X
|
|
BCC L11D6 ;PLP
|
|
STA HACCUM ;PLA
|
|
;
|
|
L11CE TAY
|
|
LDA HFLAGS
|
|
PHA
|
|
PLP
|
|
TYA
|
|
PHP
|
|
PLA
|
|
;
|
|
L11D6 STA HFLAGS
|
|
L11D8 STX HSTAKP :NB. Must adjust SP
|
|
JSR L14C3 ;Update stack SD
|
|
JMP L123B
|
|
;=================================================
|
|
; (INSTLEN)=0-1 byte, 1-2 bytes, 2-3 bytes
|
|
; Branch inst should make use of PCADJ3 entry
|
|
; with displacement in (A)
|
|
; Ret
|
|
; (Y,A)-effective addr
|
|
;
|
|
PCADJ SEC
|
|
PCADJ2 LDA INSTLEN ;length
|
|
PCADJ3 LDY MONPC+1
|
|
TAX ;Test displacement sign
|
|
BPL PCADJ4 ; (for relative branch)
|
|
DEY ;Extend -ve by decrementing MONPC+1
|
|
;
|
|
PCADJ4 ADC MONPC
|
|
BCC L11EF
|
|
INY
|
|
L11EF RTS
|
|
;
|
|
; Check if the inst in Y-reg is a branch opcode
|
|
; There are 9 rel branch insts whose opcodes are
|
|
; $10,$30,$50,$70,$90,$B0,$D0,$F0 and $80
|
|
;
|
|
L11F0 CPY #$80 ;If BRA,
|
|
BNE L11F6
|
|
LDA #$10 ; use $10
|
|
L11F6 AND #$1F ;If relative branch, then
|
|
EOR #$14 ; change displacement ..
|
|
CMP #$04
|
|
BNE L1201 ;-> Not a branch inst
|
|
STA INSTBE+1 ; ..to $04 @ this location
|
|
;
|
|
L1201 JSR SwapZP
|
|
JSR RstRegs
|
|
;
|
|
; Next-Instruction-To-Be-Executed
|
|
;
|
|
INSTBE NOP ;Opcode
|
|
NOP ;Lobyte
|
|
NOP ;HiByte
|
|
JMP L1230
|
|
;
|
|
; Relative instructions that actually branch comes here
|
|
;
|
|
CLD
|
|
JSR SwapZP
|
|
JSR PCADJ
|
|
STA MONPC
|
|
STY MONPC+1
|
|
;
|
|
CLC
|
|
LDA INSTSV+1 ;displacement of rel insts
|
|
JSR PCADJ3
|
|
STA MONPC
|
|
LDX #3 ;3 cycles for successful brch
|
|
CPY MONPC+1
|
|
BEQ L1228
|
|
INX
|
|
;
|
|
L1228 STX NumCycles
|
|
STY MONPC+1 ;Addr of next inst
|
|
JMP L1242
|
|
;
|
|
; Instructions that do not involve transfer of
|
|
; control (include those relative insts that
|
|
; did not branch)
|
|
;
|
|
L1230 JSR SavRegs
|
|
LDA #2 ;This is the default
|
|
STA NumCycles
|
|
;
|
|
L1238 JSR SwapZP
|
|
;
|
|
L123B JSR PCADJ
|
|
STA MONPC
|
|
STY MONPC+1 ;Addr of next inst
|
|
;
|
|
; Common code for all instructions
|
|
;
|
|
L1242 BIT MasDSW ;Update Master Display?
|
|
BPL L128B ;No
|
|
;
|
|
LDX CDBar ;Next-to-be-executed
|
|
JSR VTABX
|
|
BIT SW13 ;Was inst skipped?
|
|
BPL L125A
|
|
;
|
|
JSR DSKIP ;Yes
|
|
LSR SW13 ;clear msb
|
|
BPL L1269 ;Always
|
|
;
|
|
L125A JSR DOptions
|
|
JSR InvLine
|
|
JSR DREGS
|
|
JSR L151A ;Update MC SD
|
|
JSR DBBREGS
|
|
;
|
|
L1269 BIT SSSW ;Single Step mode?
|
|
BMI L1288 ;Yes
|
|
;
|
|
LDY KBDRate ;Trace mode
|
|
BIT SW06 ;Are we using the KB rate?
|
|
BMI L1280 ;Yes
|
|
BIT PDL0SW ;Use Paddle 0?
|
|
BPL L1280
|
|
;
|
|
LDX #0 ;Yes
|
|
JSR PREAD2 ;Get a reading fr paddle 0
|
|
L1280 STY RATEC
|
|
INY
|
|
TYA
|
|
JSR WAIT2
|
|
;
|
|
L1288 JSR ScrollUp
|
|
L128B BIT ExecSW ;Executing in full speed?
|
|
BMI L1293
|
|
JMP L0E49 ;No, continue with SS/TR mode
|
|
;
|
|
L1293 JSR SVMONPC
|
|
JMP L0DDB
|
|
;=================================================
|
|
; ($1299) Display relevant info on the right side of inst
|
|
;
|
|
DOptions LDY #30
|
|
LDX L2100 ;Curr display option
|
|
LDA OPTSK,X ;Show Letter
|
|
STA (ScrLoc),Y
|
|
LDA #':'
|
|
INY
|
|
STA (ScrLoc),Y
|
|
CPX #5
|
|
BCS L12B2 ;O=E/O=B
|
|
INY
|
|
LDA CPURegs,X ;Get the register's curr value and display
|
|
JMP DBINSTR ; its contents as a string of 0's and 1'
|
|
;
|
|
L12B2 BNE L12D4 ;-> O=E
|
|
;
|
|
; Display machine code in hex
|
|
;
|
|
L12B4 LDX #-1
|
|
LDY #32 ;offset in scrn line
|
|
L12B8 INX
|
|
LDA INSTSV,X
|
|
JSR PUTHEX
|
|
INY
|
|
CPX INSTLEN
|
|
BNE L12B8
|
|
RTS
|
|
;
|
|
; Branch insts
|
|
;
|
|
L12C6 LDA INSTSV+1 ;Print the displacement
|
|
LDY #34
|
|
JSR PUTHEX
|
|
LDY NumCycles ;# of cycles
|
|
JMP L149F
|
|
;
|
|
; Compute effective addrs/rel branches
|
|
; & instruction cycles - pg 160, 208
|
|
;
|
|
L12D4 LDY INSTBE+1
|
|
LDX INSTBE+2
|
|
LDA INSTBE ;Get opcode
|
|
STA Z40 ;Save here for later
|
|
;
|
|
; The following instructons are handled
|
|
; individually because their bit patterns
|
|
; do not conform to the norm
|
|
;
|
|
CMP #$80
|
|
BEQ L12C6 ;-> BRA
|
|
CMP #$14
|
|
BEQ L1329 ;-> TRB zp
|
|
CMP #$BC
|
|
BEQ L1327 ;-> LDY abs,X
|
|
CMP #$3C
|
|
BEQ L1327 ;-> BIT abs,X
|
|
CMP #$7C
|
|
BNE L12F6
|
|
JMP L13B7 ;-> JMP (abs,X)
|
|
L12F6 CMP #$6C
|
|
BNE L12FD
|
|
JMP L13CD ;-> JMP (abs)
|
|
;
|
|
L12FD AND #%00011111 ;abcd efgh
|
|
STA Z41 ;000d efgh
|
|
CMP #$10
|
|
BEQ L12C6 ;Branch inst
|
|
CMP #$19
|
|
BEQ L135F ;abs,Y inst
|
|
;
|
|
CMP #$14 ;inst involving zp,X and zp,Y
|
|
BEQ L132C ; & the special case TRB zp
|
|
CMP #$15
|
|
BEQ L132C
|
|
CMP #$16
|
|
BEQ L132C
|
|
;
|
|
CMP #$1D ;abs,X inst
|
|
BEQ L1352
|
|
;
|
|
CMP #$01 ;(zp,X) inst - indirect
|
|
BEQ L138E
|
|
CMP #$11 ;(zp),Y inst
|
|
BEQ L1399
|
|
CMP #$12 ;(zp) inst
|
|
BEQ L1386
|
|
CMP #$1E ;abs,X inst
|
|
L1327 BEQ L1352
|
|
L1329 JMP L142C ;Others
|
|
;
|
|
; Instructions involving zp,X zp,Y
|
|
;
|
|
L132C LDX #$00
|
|
LDA Z40 ;Opcode
|
|
AND #%11011111
|
|
CMP #$96
|
|
BEQ L1349 ;LDX zp,Y & STX zp,Y
|
|
;
|
|
TYA ;addr lobyte
|
|
CLC
|
|
ADC HXREG
|
|
LDY #4 ;# of cycles
|
|
PHA
|
|
LDA Z41 ;000d efgh
|
|
CMP #$16
|
|
BNE L1345 ;-> zp,X
|
|
LDY #6 ;# of cycles
|
|
L1345 PLA
|
|
JMP L13FB
|
|
;
|
|
; STX zp,Y/LDX zp,Y
|
|
;
|
|
L1349 TYA ;addr lobyte (zp loc)
|
|
CLC
|
|
ADC HYREG
|
|
LDY #4 ;# of cycles
|
|
JMP L13FB
|
|
;
|
|
; abs,X insts, LDX abs,Y inst
|
|
; BIT abs,X & LDY abs,X
|
|
;
|
|
L1352 LDA Z40 ;Get opcode
|
|
CMP #$BE
|
|
BEQ L135F ;-> LDX abs,Y
|
|
;
|
|
; abs,X insts
|
|
;
|
|
TYA
|
|
CLC
|
|
ADC HXREG
|
|
JMP L1363
|
|
;
|
|
; abs,Y instructions
|
|
;
|
|
L135F TYA ;addr lo
|
|
CLC
|
|
ADC HYREG
|
|
L1363 BCC L1366
|
|
INX
|
|
;
|
|
L1366 PHA ;Save addr lo-byte
|
|
LDA Z40 ;Get opcode
|
|
CMP #$BE
|
|
BEQ L137D ;-> LDX abs,Y
|
|
LDY #5 ;# of cycles
|
|
AND #$F0
|
|
CMP #$90
|
|
BEQ L1382 ;-> STA abs,X/STZ abs,X
|
|
;
|
|
LDY #7 ;# of cycles
|
|
LDA Z41
|
|
CMP #$1E
|
|
BEQ L1382 ;->abs,X shifts insts
|
|
L137D LDY #4 ;# of cyles for
|
|
JSR L1425 ; other abs,X insts
|
|
L1382 PLA
|
|
JMP L13FB
|
|
;
|
|
; (zp) inst
|
|
;
|
|
L1386 TYA ;zp loc
|
|
JSR L140B
|
|
LDY #5 ;# of cycles
|
|
BNE L13FB ;Always
|
|
;
|
|
; (zp,X)
|
|
;
|
|
L138E TYA
|
|
CLC
|
|
ADC HXREG
|
|
JSR L140B
|
|
LDY #6 ;# of cycles
|
|
BNE L13FB ;always
|
|
;
|
|
; (zp),Y inst
|
|
;
|
|
L1399 TYA ;zp loc
|
|
JSR L140B ;(A,X) - ptr
|
|
STX INSTBE+2
|
|
CLC
|
|
ADC HYREG
|
|
BCC L13A6
|
|
INX
|
|
;
|
|
L13A6 PHA
|
|
LDY #6 ;# of cycles
|
|
LDA Z40
|
|
CMP #$91 ;STA (zp),y
|
|
BEQ L13B3
|
|
DEY ;Less 1 cycle
|
|
JSR L1425 ;Cross mem page bdry?
|
|
L13B3 PLA
|
|
JMP L13FB
|
|
;
|
|
; JMP (abs,X)
|
|
;
|
|
L13B7 JSR SwapZP
|
|
LDA INSTBE+1
|
|
CLC
|
|
ADC HXREG
|
|
LDX INSTBE+2
|
|
BCC L13C6
|
|
INX
|
|
L13C6 JSR L13DD
|
|
LDY #6 ;# of cycles
|
|
BNE L13FB ;always
|
|
;
|
|
L13CD JSR SwapZP
|
|
LDA INSTBE+1
|
|
LDX INSTBE+2
|
|
JSR L13DD
|
|
LDY #5 ;# of cycles
|
|
BNE L13FB ;always
|
|
;=================================================
|
|
; Get pointer located in non-zp memory
|
|
; Entry
|
|
; (X,A)=addr
|
|
; Ret
|
|
; (A,X)=pointer
|
|
;
|
|
L13DD STA IMM4+1
|
|
STX IMM4+2
|
|
STX IMM5+2
|
|
CLC
|
|
ADC #1
|
|
STA IMM5+1 ;-> page brdy bug?
|
|
IMM4 LDA $FFFF
|
|
PHA
|
|
IMM5 LDA $FFFF
|
|
PHA
|
|
JSR SwapZP
|
|
PLA
|
|
TAX
|
|
PLA
|
|
RTS
|
|
;=================================================
|
|
; Print addr & # of cycles
|
|
; (Y)=# of cycles
|
|
; (A,X)=addr
|
|
;
|
|
L13FB STY Z43 ;# of cycles
|
|
LDY #32
|
|
PHA
|
|
TXA
|
|
JSR PUTHEX
|
|
PLA
|
|
JSR PUTHEX
|
|
JMP L14A1
|
|
;=================================================
|
|
; Get zp pointer
|
|
; Input
|
|
; (A)=zp location
|
|
; Output
|
|
; (A,X)=pointer stored @ zp loc
|
|
;
|
|
L140B PHA
|
|
JSR SwapZP
|
|
PLA
|
|
TAX
|
|
STX IMM10+1
|
|
INX
|
|
STX IMM11+1
|
|
;
|
|
IMM10 LDA $00 ;zpage locn
|
|
PHA
|
|
IMM11 LDA $00
|
|
PHA ;hi
|
|
JSR SwapZP
|
|
PLA
|
|
TAX
|
|
PLA
|
|
RTS
|
|
;=================================================
|
|
; 1 more cycle if mem page boundary is crossed
|
|
;
|
|
L1425 CPX INSTBE+2
|
|
BEQ L142B
|
|
INY
|
|
L142B RTS
|
|
;=================================================
|
|
; Determine # of cycles for other inst
|
|
; Need to check all 65C02 opcodes are included
|
|
;
|
|
L142C LDY #5 ;Assume 5 cycles
|
|
LDA Z40 ;opcode abcd efgh
|
|
AND #%11100111 ;abc0 0fgh
|
|
CMP #$04
|
|
BNE L143F
|
|
LDA Z40 ;$04,$0C,$14,$1C (TSB,TRB)
|
|
AND #%00001000
|
|
BEQ L149F ;-> TSB/TRB dp
|
|
INY ;-> TSB/TRB abs
|
|
BNE L149F ;always
|
|
;
|
|
L143F LDY #3 ;3 cycle inst
|
|
LDA Z41 ;000d efgh
|
|
CMP #$04
|
|
BEQ L149F ;$24,$44,$64,$84,$A4,$C4,$E4
|
|
CMP #$05
|
|
BEQ L149F ;$05,$25,$45,$65,$85,$A5,$C5,$E5
|
|
;
|
|
LDA Z40 ;Get opcode
|
|
AND #%11011111 ;ab0d efgh
|
|
STA Z42
|
|
CMP #$86
|
|
BEQ L149F ;-> LDX/STX zp
|
|
LDA Z40 ;Get opcode
|
|
CMP #iJMP
|
|
BEQ L149F ;-> JMP abs
|
|
AND #%10111111 ;a0cd efgh
|
|
CMP #$08
|
|
BEQ L149F ;-> $08,$48
|
|
LDA Z40 ;Get opcode
|
|
ASL
|
|
CMP #$B4
|
|
BEQ L149F ;-> PHY/PHX
|
|
;
|
|
INY ;4 cycle inst
|
|
CMP #$F4
|
|
BEQ L149F ;->PLY/PLX
|
|
;
|
|
LDA Z41 ;000d efgh
|
|
CMP #$0D
|
|
BEQ L149F ;-> $0D,$2D,$4D,$6D,$8D,$AD,$CD,$ED
|
|
CMP #$0C
|
|
BEQ L149F ;-> $0C,$2C,$4C,$6C,$8C,$AC,$CC,$EC
|
|
LDA Z42 ;ab0d efgh
|
|
CMP #$8E
|
|
BEQ L149F ;-> $8E,$AE
|
|
LDA Z40 ;Get opcode
|
|
CMP #$9C
|
|
BEQ L149F ;-> STZ abs
|
|
AND #%10111111 ;a0cd efgh
|
|
CMP #$28
|
|
BEQ L149F ;-> $28,$68
|
|
;
|
|
INY ;5 cycle inst
|
|
LDA Z41 ;000d efgh
|
|
CMP #$06 ;$06,$26,$46,$66,$C6,$E6
|
|
BEQ L149F
|
|
;
|
|
INY ;6 cycle inst
|
|
LDA Z40 ;Get opcode
|
|
AND #%10011111
|
|
BEQ L149F ;-> $20,$40,$60
|
|
LDA Z41 ;000d efgh
|
|
CMP #$0E
|
|
BEQ L149F ;-> $0E,$2E,$4E,$6E,$8E,$AE,$CE,$EE
|
|
;
|
|
; On fall thru, instructions not filtered out
|
|
; by the code above will be 2 cycles
|
|
; Print # of cycles
|
|
;
|
|
LDY #2
|
|
L149F STY Z43 ;# of cycles
|
|
L14A1 LDY #37
|
|
LDA #'('
|
|
STA (ScrLoc),Y
|
|
INY
|
|
CLC
|
|
LDA Z43
|
|
ADC #'0'
|
|
STA (ScrLoc),Y
|
|
INY
|
|
LDA #')'
|
|
STA (ScrLoc),Y
|
|
;
|
|
LDA Z43
|
|
CLC
|
|
ADC CYCLEC
|
|
STA CYCLEC
|
|
BCC L14C2
|
|
INC CYCLEC+1
|
|
L14C2 RTS
|
|
;=================================================
|
|
; Show Stack SD
|
|
;
|
|
L14C3 BIT MasDSW
|
|
BPL L1519 ;-> No update
|
|
;
|
|
SEC
|
|
LDA HSTAKP
|
|
SBC L210D ;# of locations above stack ptr
|
|
STA Z40
|
|
;
|
|
LDX #2 ;top of SD-1
|
|
L14D2 INX
|
|
STX Z43
|
|
JSR VTABX
|
|
LDY #1
|
|
LDA #'1'
|
|
STA (ScrLoc),Y ;Show "1xx:"
|
|
INY
|
|
LDA Z40
|
|
TAX
|
|
JSR PUTHEX
|
|
LDA #':'
|
|
STA (ScrLoc),Y
|
|
;
|
|
INY
|
|
INY
|
|
LDA STACK,X
|
|
JSR PUTHEX
|
|
;
|
|
LDA Z43
|
|
CMP StackPBar
|
|
BNE L1510
|
|
;
|
|
LDY #8
|
|
L14FA LDA (ScrLoc),Y ;Hilite stack ptr bar
|
|
AND #$3F
|
|
STA (ScrLoc),Y
|
|
DEY
|
|
BPL L14FA
|
|
;
|
|
CPX #32
|
|
BCS L1510
|
|
;
|
|
; BB's stack area
|
|
;
|
|
LDA #$60 ;Flashing space
|
|
INY ;=1
|
|
STA (ScrLoc),Y
|
|
LDY #8
|
|
STA (ScrLoc),Y
|
|
;
|
|
L1510 INC Z40 ;NB. If -1, (Z40) becomes 0
|
|
LDX Z43
|
|
CPX L210B ;wnd btm of Stack SD
|
|
BCC L14D2 ;Next stack location
|
|
L1519 RTS
|
|
;=================================================
|
|
; Show MemCell SD
|
|
;
|
|
L151A JSR SwapZP
|
|
LDY L2103 ;lst line of MC SD
|
|
LDX #-1
|
|
L1522 INX
|
|
STY ALTYSV
|
|
LDA SLATLO,Y
|
|
STA STOSCR+1 ;Point @ scrn loc
|
|
LDA SLATHI,Y
|
|
STA STOSCR+2
|
|
;
|
|
LDY #$00 ;Show "xxxx:"
|
|
LDA MCAdrH,X
|
|
STA IMM6+2
|
|
STA IMM7+2
|
|
JSR STOHEX
|
|
LDA MCAdrL,X
|
|
STA IMM6+1
|
|
STA IMM7+1
|
|
JSR STOHEX
|
|
LDA #':'
|
|
JSR STOSCR
|
|
;
|
|
IMM6 LDA $FFFF
|
|
PHA
|
|
LDA MCType,X ;Pointer?
|
|
BPL L1569 ;No
|
|
INC IMM7+1 ;mem page bdry bug!
|
|
;
|
|
IMM7 LDA $FFFF
|
|
JSR STOHEX
|
|
PLA
|
|
JSR STOHEX
|
|
BNE L1577 ;always
|
|
;
|
|
L1569 PLA ;Hex
|
|
PHA
|
|
JSR STOHEX
|
|
LDA #SPACE
|
|
JSR STOSCR
|
|
PLA
|
|
JSR STOSCR
|
|
;
|
|
L1577 LDY ALTYSV
|
|
INY
|
|
CPY #22 ;Last line of MC SD?
|
|
BNE L1522 ;No, next mem cell
|
|
JMP SwapZP
|
|
;=================================================
|
|
; Store the hexdec rep of (A) into a mem location
|
|
; esply video mem
|
|
;
|
|
STOHEX PHA
|
|
LSR
|
|
LSR
|
|
LSR
|
|
LSR
|
|
JSR STONYB
|
|
PLA
|
|
AND #$0F
|
|
STONYB ORA #'0' ;hi-bit A2 ASCII
|
|
CMP #'9'+1
|
|
BCC STOSCR
|
|
ADC #$06
|
|
;
|
|
; Store a char into any video mem location
|
|
; User must set up the location b4 calling rtn
|
|
;
|
|
STOSCR STA $FFFF,Y ;Self-modifying code
|
|
INY
|
|
RTS
|
|
;=================================================
|
|
; ($159A)
|
|
; Returns the format and length of the opcode
|
|
; Each opcode is of the form xxxx xxyy
|
|
; Three cases are considered since xxxx xx11 is invalid
|
|
; (1) xxxx xx00
|
|
; (2) xxxx xx10
|
|
; (3) xxxx xx01
|
|
; Case (1) & (2) will lead to
|
|
; (A) = 00xx xxxx with C-bit=bit1 (which is 0 or 1)
|
|
; Case (3) will lead to
|
|
; (A) = 0100 00xx with C-bit=bit2 (which is 0 or 1)
|
|
; The original 01 will be in bit7,6
|
|
; bits5-7 are masked off
|
|
;
|
|
INSDIS LDY #0
|
|
LDA (MONPC),Y ;get opcode
|
|
INSDIS1 LDX #$FC ;%1111 1100
|
|
STX AdrModSW
|
|
LSR ;test bit 0 (A=0xxx xxxy) C-bit=y(bit0)
|
|
BCC L15AB
|
|
ROR ;(A=10xx xxxx) C-bit=y(bit1)
|
|
BCS L15BA ;opcode was xxxx xx11 -> invalid!
|
|
AND #%10000111 ;(A)=1000 0xxx mask bits
|
|
;
|
|
L15AB LSR ;(A)=00xx xxxx or 0100 00xx (on fall thru)
|
|
TAX ;C-bit=bit1 or bit2 (see comments above)
|
|
LDA FMT1,X ;Get format index byte
|
|
BCC L15B6 ;Even, use low nybble
|
|
LSR ;Odd, shift high nybble
|
|
LSR
|
|
LSR
|
|
LSR
|
|
;
|
|
L15B6 AND #$0F ;mask 4-bits
|
|
BNE L15BF
|
|
L15BA LDA #$00 ;Set print format index to 0
|
|
STA AdrModSW
|
|
L15BF TAX
|
|
LDA FMT2,X ;Index into print format table
|
|
STA INSTFMT ;Save for addr field formatting
|
|
AND #%00000011 ;Mask for 2-bit length
|
|
STA INSTLEN ;0-1 byte, 1-2 bytes, 2-3 bytes
|
|
;
|
|
TAY
|
|
L15CC LDA (MONPC),Y ;Save instruction
|
|
STA INSTSV,Y
|
|
DEY
|
|
BPL L15CC
|
|
RTS
|
|
;=================================================
|
|
; ($15D5) Swap 16 zpage locations ($3A-$49)
|
|
; (Y) unchanged
|
|
; (X)=$FF
|
|
;
|
|
SwapZP LDX #15
|
|
L15D7 LDA MONPC,X
|
|
LDY HOLDPZ,X
|
|
STA HOLDPZ,X
|
|
STY MONPC,X
|
|
DEX
|
|
BPL L15D7
|
|
RTS
|
|
;=================================================
|
|
; ($15E5) Save & Restore 6502's regs
|
|
;
|
|
SavRegs PHP
|
|
CLD
|
|
STA SAVEA
|
|
STX SAVEX
|
|
STY SAVEY
|
|
PLA
|
|
STA SAVEP
|
|
RTS
|
|
;
|
|
RstRegs LDA SAVEP
|
|
PHA
|
|
LDA SAVEA
|
|
LDX SAVEX
|
|
LDY SAVEY
|
|
PLP
|
|
RTS
|
|
;=================================================
|
|
SVMONPC LDA MONPC
|
|
STA SVxZ3A
|
|
LDA MONPC+1
|
|
STA SVxZ3A+1
|
|
RTS
|
|
;
|
|
RSTMONPC LDA SVxZ3A
|
|
STA MONPC
|
|
LDA SVxZ3A+1
|
|
STA MONPC+1
|
|
RTS
|
|
;
|
|
CPY2IB LDA SLIN23,Y ;Copy # of chars from cmdln
|
|
STA IBuff-1,Y ; to input buffer
|
|
DEY
|
|
BNE CPY2IB
|
|
RTS
|
|
;=================================================
|
|
; Restore (INSTSV) to that of INSTBE
|
|
;
|
|
L1624 LDA INSTBE
|
|
STA INSTSV
|
|
LDA INSTBE+1
|
|
STA INSTSV+1
|
|
LDA INSTBE+2
|
|
STA INSTSV+2
|
|
;
|
|
LDA L20F1 ;FORMAT of inst BE
|
|
STA INSTFMT
|
|
AND #%00000011
|
|
STA INSTLEN ;len of instruction
|
|
RTS
|
|
;=================================================
|
|
; Update the PC display
|
|
;
|
|
DMONPC LDA #<SLIN01
|
|
STA ScrLoc+1
|
|
LDA #>SLIN01
|
|
STA ScrLoc
|
|
LDY #11 ;scrn line offset
|
|
LDA MONPC+1
|
|
JSR PUTHEX
|
|
LDA MONPC
|
|
JMP PUTHEX
|
|
;=================================================
|
|
; Update regs display
|
|
;
|
|
DREGS LDX #1
|
|
JSR VTABX
|
|
LDY #17 ;display acc
|
|
LDA HACCUM
|
|
JSR PUTHEX
|
|
INY
|
|
LDA HXREG ;display X-reg
|
|
JSR PUTHEX
|
|
;
|
|
INY
|
|
LDA HYREG ;display Y-reg
|
|
JSR PUTHEX
|
|
;
|
|
INY
|
|
LDA HSTAKP ;display stack pointer
|
|
JSR PUTHEX
|
|
;
|
|
INY
|
|
LDA HFLAGS ;display processor flags
|
|
JSR PUTHEX
|
|
INY
|
|
LDA HFLAGS
|
|
JMP DBINSTR ;Display flags as 0s and 1s
|
|
;=================================================
|
|
; ($1680) Display the hexdec rep of (A)
|
|
; (A) - destroyed
|
|
; (Y) - horiz offset into screen line, incr by 1
|
|
; (X) - unchanged
|
|
; SrcLoc set prior to entry
|
|
;
|
|
PUTHEX PHA
|
|
LSR
|
|
LSR
|
|
LSR
|
|
LSR
|
|
JSR PUTNYBZ
|
|
PLA
|
|
PUTNYB AND #$0F ;lower nybble
|
|
PUTNYBZ ORA #'0'
|
|
CMP #'9'+1
|
|
BCC L1693
|
|
ADC #$06
|
|
L1693 STA (ScrLoc),Y
|
|
INY
|
|
RTS
|
|
;=================================================
|
|
; ($1697) Display (A) as a string of ASC 0's and 1's
|
|
; SrcLoc set prior to entry
|
|
;
|
|
DBINSTR LDX #8
|
|
L1699 ASL ;Shift bit into C
|
|
PHA ;Save temporarily for later
|
|
LDA #%01011000
|
|
ROL ;Now shift C into bit0
|
|
STA (ScrLoc),Y ;1011 000c ($B0 or $B1)
|
|
INY
|
|
PLA ;recover
|
|
DEX
|
|
BNE L1699 ;next bit
|
|
RTS
|
|
;=================================================
|
|
; Show numbered line
|
|
; (A) index into table
|
|
; (A) & (X) unchanged
|
|
; (Y) incr by 1
|
|
; SrcLoc set prior to entry
|
|
;
|
|
DNbrdLin STX Z40 ;save (X) temporarily
|
|
TAX
|
|
DEX
|
|
L16AA EQU *
|
|
LDA LinNbrL,X ;Get ASCII line #
|
|
STA (ScrLoc),Y ; & show it
|
|
INY
|
|
LDA LinNbrH,X
|
|
STA (ScrLoc),Y
|
|
INX
|
|
TXA
|
|
LDX Z40
|
|
RTS |