mirror of https://github.com/markpmlim/EdAsm.git
692 lines
22 KiB
ArmAsm
692 lines
22 KiB
ArmAsm
Name : SWEET16.S
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End of file : 16,627
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This file was generated using the DiskBrowser utility with minimal editing.
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It is meant for viewing purposes only.
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;---------------------------------------------------------;
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; Initial source was disassembled with The Flaming Bird ;
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; Disassembler. The Sweet16 code was disassembled with ;
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; the Merlin8 disassembler. Final re-assembly must be ;
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; done with the EdAsm assembler to produce a binary ;
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; image which will be compared against the original ;
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; (c) Phoenix corp. 1992,93 - All rights reserved ;
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;---------------------------------------------------------;
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ORG $D000
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;=================================================
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; SWEET16 code is executed as if it were running on a
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; 16-bit processor with sixteen, internal 16-bit
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; little-endian registers, R0 through R15. Some registers
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; have well-defined functions:
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; R0 is the accumulator.
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; R12 subroutine return address stack
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; R13 stores the result of all comparison operations for
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; branch testing.
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; R14 is the status register.
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; R15 is the program counter.
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; The 16 virtual registers, 32 bytes in total, are located
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; in the zero page of the Apple II's real, physical memory
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; map (at $00-$1F)
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;
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; The carry bit is in the lsb of R14H
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; Negative and Zero "flags" are the given by the contents
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; of the "prior" result register (indexed with X)
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;
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NEWSW16 EQU * ;ENTRY
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STA Z58 ;Preserve the regs
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STX Z59
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STY Z5A
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PHP
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PLA
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STA Z5B
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CLD
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PLA
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STA Reg15 ;Init the SW16 program counter
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PLA ; using the Return Addr
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STA Reg15+1
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LD011 INC Reg15 ;Increment SW16 PC for fetch
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BNE LD017
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INC Reg15+1
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;
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LD017 LDY #0
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SW16BK EQU *-1
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LDA (Reg15),Y ;Fetch the instruction
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AND #$0F ;Mask register specification
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ASL ;Double for 2-byte registers
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TAX ;(X) is used to index the register Rn
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LSR
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EOR (Reg15),Y ;Now we have the opcode ($x0) where x=1-F
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BEQ ToBR ;If zero, then non-reg op or CPIM
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;
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STX Reg14+1 ;Indicate "prior" result register
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LSR ;opcodex2 to LSB's
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LSR
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LSR
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TAY ;To Y-reg for indexing
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LDA LD07F-2,Y
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STA Z5C+1
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LDA LD05F-2,Y
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STA Z5C
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JMP (Z5C) ;Go SW16 REG op rtns
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;
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; Non-register ops are handled here. They include
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; the new ops CPIM, BRL and BSL
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; NB. On entry, Y=0
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;
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ToBR INC Reg15 ;Increment SW16 PC
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BNE ToBR2
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INC Reg15+1
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ToBR2 LDA LD080,X
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STA Z5C+1
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LDA LD060,X
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STA Z5C
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LDA Reg14+1 ;"Prior" result register
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LSR ;Prepare 6502 C-bit for BC, BNC
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LDA Reg14+1
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; AND #%0001_1110
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AND #%00011110
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TAX ;(X)=Index to the "prior" result register
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JMP (Z5C) ;Go non-reg op rtn
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;
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; Control is returned to the 6502 and program execution
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; continues at the location immediately following the RTN
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; instruction. The 6502 registers and status conditions are
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; restored to their original contents (prior to entering
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; SWEET 16 mode).
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;
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SW16RTN LDA Z5B ;Restore the contents of the 6502 regs
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PHA
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LDA Z58
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LDX Z59
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LDY Z5A
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PLP
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LD05C JMP (Reg15) ;Return to 6502 code via SW16 PC
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;
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LD05F DB >SW16SET ;1X
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LD060 DB >SW16RTN ;0
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DB >SW16LD ;2X
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DB >SW16BR ;1
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DB >SW16ST ;3X
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DB >SW16BNC ;2
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DB >SW16LDat ;4X
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DB >SW16BC ;3
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DB >SW16STat ;5X
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DB >SW16BP ;4
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DB >SW16LDDat ;6X
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DB >SW16BM ;5
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DB >SW16STDat ;7X
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DB >SW16BZ ;6
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DB >SW16POP ;8X
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DB >SW16BNZ ;7
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DB >SW16STPat ;9X
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DB >SW16BM1 ;8
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DB >SW16ADD ;AX
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DB >SW16BNM1 ;9
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DB >SW16SUB ;BX
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DB >SW16BK ;A
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DB >SW16POPD ;CX
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DB >SW16RS ;B
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DB >SW16CPR ;DX
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DB >SW16BS ;C
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DB >SW16INR ;EX
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DB >SW16CPIM ;D
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DB >SW16DCR ;FX
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DB >SW16BRL ;E
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DB >LD011 ;Unused
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DB >SW16BSL ;F
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;
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LD07F DB <SW16SET ;1X
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LD080 DB <SW16RTN ;0
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DB <SW16LD ;2X
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DB <SW16BR ;1
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DB <SW16ST ;3X
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DB <SW16BNC ;2
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DB <SW16LDat ;4X
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DB <SW16BC ;3
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DB <SW16STat ;5X
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DB <SW16BP ;4
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DB <SW16LDDat ;6X
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DB <SW16BM ;5
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DB <SW16STDat ;7X
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DB <SW16BZ ;6
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DB <SW16POP ;8X
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DB <SW16BNZ ;7
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DB <SW16STPat ;9X
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DB <SW16BM1 ;8
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DB <SW16ADD ;AX
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DB <SW16BNM1 ;9
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DB <SW16SUB ;BX
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DB <SW16BK ;A
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DB <SW16POPD ;CX
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DB <SW16RS ;B
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DB <SW16CPR ;DX
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DB <SW16BS ;C
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DB <SW16INR ;EX
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DB <SW16CPIM ;D
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DB <SW16DCR ;FX
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DB <SW16BRL ;E
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DB <LD011 ;Unused
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DB <SW16BSL ;F
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;
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; The SW16 accumulator is loaded from Rn and branch
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; conditions set according to the data transferred. The
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; Carry is cleared and the contents of Rn are not changed.
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; Input
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; Rn
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; Output
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; R0 - both bytes
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;
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SW16LD LDA Reg0,X ;Move Rx to R0 (Acc)
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STA Reg0
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LDA Reg0+1,X
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STA Reg0+1
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JMP LD011
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;
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; The SW16 ACC is stored into Rn and branch
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; conditions set according to the data transferred.
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; The carry is cleared and the contents of the ACC
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; are unchanged
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; Input
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; R0
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; Output
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; Rn - both bytes
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;
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SW16ST LDA Reg0 ;Move R0 (Acc) to Rx
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STA Reg0,X
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LDA Reg0+1
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STA Reg0+1,X
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JMP LD011
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;
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; The low byte of ACC is stored into the memory location
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; whose ADDRESS resides in Rn. Branch conditions reflect
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; the 2-byte ACC contents. After the transfer, Rn is
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; incremented by 1.
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; Input
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; Rn - ptr to mem location
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; R0 - lobyte
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; Output
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; Rn = Rn+1
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; R14H = 0 - carry cleared
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;
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SW16STat LDA Reg0
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STA (Reg0,X) ;Store byte indirect
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LDY #0
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STY Reg14+1 ;Indicate R0 is result -ve
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;
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; The contents of Rn are incremented by 1. The carry is
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; cleared and other branch conditions reflect the
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; incremented value.
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;
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SW16INR INC Reg0,X ;Increment Rx
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BNE LD0C3
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INC Reg0+1,X
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LD0C3 JMP LD011
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;
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; The lobyte of the SW16 ACC is loaded from the memory
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; location whose ADDRESS resides in Rn and ACC hi-byte
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; is zeroed. Branch conditions reflect the final contents
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; of the ACC which will always be positive and never
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; minus 1. The Carry is cleared and after the transfer,
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; Rn is incremented by 1.
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; Input
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; Rn - ptr to mem location
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; Output
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; R0 - lobyte
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; Rn = Rn+1
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; R14H = 0 - carry cleared
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;
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SW16LDat LDA (Reg0,X)
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STA Reg0
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LDY #0 ;Zero the ACC's hi-byte
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STY Reg0+1
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STY Reg14+1 ;Indicate R0 is +ve
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INC Reg0,X
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BNE LD0D6
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INC Reg0+1,X
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LD0D6 JMP LD011
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;
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; Rn is decremented by 1 and the hibyte of ACC is loaded
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; from the memory location whose address now resides in Rn.
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; Rn is again decremented by 1 and the lobyte of ACC is
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; loaded from the corresponding memory location. Branch
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; conditions reflect the final ACC contents. The carry
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; is cleared. Because Rn is decremented prior to loading
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; each of the ACC halves, double-byte stacks may be
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; implemented with the STD Rn and POPD Rn ops where Rn
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; is the stack pointer.
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;
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; Input
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; Rn - ptr to mem location
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; Output
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; R0 - both bytes
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; Rn = Rn+2
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; R14H = 0 - carry cleared
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;
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SW16POPD LDA Reg0,X
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BNE LD0DF
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DEC Reg0+1,X
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LD0DF DEC Reg0,X
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LDA (Reg0,X)
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TAY
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LDA Reg0,X
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BNE LD0EA
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DEC Reg0+1,X
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LD0EA DEC Reg0,X
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LDA (Reg0,X)
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STA Reg0
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STY Reg0+1
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LDY #0
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STY Reg14+1
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JMP LD011
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;
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; The lobyte of the ACC is loaded from the memory location
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; whose address resides in Rn AFTER Rn is decremented by 1,
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; and the hibyte is cleared. Branch conditions reflect
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; the final 2-byte ACC contents which will always be
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; positive and never minus one. The carry is cleared.
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; Because Rn is decremented prior to loading the ACC,
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; single byte stacks may be implemented with the
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; STI Rn and POP Rn ops where Rn is the stack pointer.
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; Input
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; Rn - ptr to mem location
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; Output
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; R0L - changed
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; R0H = 0
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; Rn = Rn+1
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; R14H = 0 - carry cleared
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;
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SW16POP LDY #0
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LDA Reg0,X
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JMP LD106
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;=================================================
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LD100 EQU * ;ENTRY?
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LDA ROMIN2
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JMP $E000 ;AppleSoft
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;=================================================
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LD106 BNE LD10A
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DEC Reg0+1,X
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LD10A DEC Reg0,X
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LDA (Reg0,X)
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STA Reg0
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STY Reg0+1 ;zero hi-byte
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LDY #0
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STY Reg14+1
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JMP LD011
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;
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; The lobyte of the ACC is loaded from memory location
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; whose address resides in Rn, and Rn is then incremented
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; by 1. Its hibyte is loaded from the memory location whose
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; address resides in the incremented Rn, and Rn is again
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; incremented by 1. Branch conditions reflect the contents
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; of final ACC. The carry is cleared.
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; Input
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; Rn - ptr to mem location
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; Output
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; R0 - both bytes changed
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; Rn = Rn+2
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; R14H = 0 - carry cleared
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;
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SW16LDDat LDA (Reg0,X)
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STA Reg0
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INC Reg0,X
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BNE LD123
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INC Reg0+1,X
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LD123 LDA (Reg0,X)
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STA Reg0+1
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LDY #0
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STY Reg14+1
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INC Reg0,X
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BNE LD131
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INC Reg0+1,X
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LD131 JMP LD011
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;
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; The lobyte of ACC is stored into memory location
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; whose address resides in Rn, and Rn is the incremented
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; by 1. The hibyte of ACC is stored into the memory
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; location whose address resides in the incremented
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; Rn, and Rn is again incremented by 1. Branch conditions
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; reflect the contents of ACC which are unchanged.
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; The carry is cleared.
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; Input
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; Rn - ptr to mem location
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; R0 - both bytes used
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; Output
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; Rn = Rn+2
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; R14H = 0 - carry cleared
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;
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SW16STDat LDA Reg0
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STA (Reg0,X)
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LDY #0
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STY Reg14+1
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INC Reg0,X
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BNE LD142
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INC Reg0+1,X
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LD142 LDA Reg0+1
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STA (Reg0,X)
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INC Reg0,X
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BNE LD14C
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INC Reg0+1,X
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LD14C JMP LD011
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;
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; The lobyte of ACC is stored into the memory location
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; whose address resides in Rn after Rn is decremented by 1.
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; Branch conditions will reflect the 2-byte ACC contents
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; which are not modified. STP Rn and POP Rn are used
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; together to move data blocks beginning at the greatest
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; address and working down. Additionally, single-byte
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; stacks may be implemented with the STP Rn ops.
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; Input
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; R0 - lobyte used
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; Rn - ptr to mem location
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; Output
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; Rn = Rn+1
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; R14H = 0 - carry cleared
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;
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SW16STPat LDA Reg0,X
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BNE LD155
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DEC Reg0+1,X
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LD155 DEC Reg0,X
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LDA Reg0
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STA (Reg0,X)
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LDY #0
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STY Reg14+1
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JMP LD011
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;
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; The contents of Rn are decremented by 1. The carry is
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; cleared and other branch conditions reflect the
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; decremented value.
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; Input
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; Rn
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; Output
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; Rn = Rn-1
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; R14H = set on entry into SW16
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;
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SW16DCR LDA Reg0,X
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BNE LD168
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DEC Reg0+1,X
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LD168 DEC Reg0,X
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JMP LD011
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;
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; The low order 16 bits of the subtraction are restored in
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; the ACC, the 17-th bit becomes the carry and other branch
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; conditions reflect the final ACC contents. If the 16-bit
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; unsigned ACC contents are greater than or equal to the
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; 16-bit unsigned Rn contents, then the carry is set,
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; otherwise it is cleared. Rn is not disturbed.
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; For SUB instruction, register specification would be
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; changed to indicate R0 (the SW16 ACC)
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;
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; Output
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; R0
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; R14H = lsb indicate carry condition (0/1)
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;
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SW16SUB LDY #0
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;
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; The ACC (R0) contents are compared to Rn by performing
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; the 16 bit binary subtraction ACC-Rn and storing the low
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; order 16 difference bits in R13 for subsequent branch
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; tests. If the 16 bit unsigned ACC contents are greater
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; than or equal to the 16 bit unsigned Rn contents, then
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; the carry is set, otherwise it is cleared. No other
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; registers, including ACC and Rn, are disturbed.
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; Input
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; Rn - both bytes used; unchanged
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; R0 - both bytes used; unchanged
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; Output
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; R13 = 0 if ACC == Rn
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; R14H = lsb indicate carry condition (26/27)
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;
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SW16CPR SEC ;(Y)=13;2 for CPR instr
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LDA Reg0
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SBC Reg0,X
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; STA |Reg0,Y
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DB $99,$00,$00
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LDA Reg0+1
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SBC Reg0+1,X
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; STA |Reg0+1,Y
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DB $99,$01,$00
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TYA
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ADC #0 ;Propagate the carry as well as indicate
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STA Reg14+1 ; the "prior" result reg is R0/R13
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JMP LD011
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;
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; The contents of Rn are added to the contents of ACC,
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; and the low-order 16 bits of the sum restored in ACC.
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; The 17-th bit becomes the carry and the other branch
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; conditions reflect the final ACC contents.
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; For ADD instruction, register specification would be
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; changed to indicate R0 (the SW16 ACC)
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; Input
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;
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; Rn - both bytes used
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; R0 - both bytes used
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; Output
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; R0 - changed
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; R14H = lsb indicate carry condition (0/1)
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;
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SW16ADD LDA Reg0
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ADC Reg0,X
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STA Reg0
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LDA Reg0+1
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ADC Reg0+1,X
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LDY #0
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; STA |Reg0+1,Y
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DB $99,$01,$00
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TYA ;(A)=0
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ADC #0 ;Propagate the C-bit as well as
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STA Reg14+1 ; indicate the "prior" result reg is ACC
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JMP LD011
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;
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; A branch to the effective address (PC + 2 + d) is taken
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; and execution is resumed in SWEET 16 mode. The current
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; PC is pushed onto a SWEET 16 subroutine return address
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; stack whose pointer is R12, and R12 is incremented by 2.
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; The carry is cleared and branch conditions set to
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; indicate the current ACC contents.
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; Input
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; R15
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; Output
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; R12 = R12+2
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; (R12) = Mem location pointed to
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;
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SW16BS LDX #Reg12 ;12;2 (SW16 stack register)
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LDA Reg15 ;PC
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STA (Reg0,X)
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INC Reg12
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BNE LD1A9
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INC Reg12+1
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LD1A9 LDA Reg15+1
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STA (Reg0,X)
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INC Reg12
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BNE SW16BR
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INC Reg12
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;
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; An effective address (ea) is calculated by adding the
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; signed displacement byte (d) to the PC. The PC contains
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; the address of the instruction immediately following the
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; BR, or the address of the BR op plus 2. The displacement
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; is a signed two's complement value from -128 to +127.
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; Branch conditions are not changed.
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;
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; NOTE: The effective address calculation is identical to
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; that for 6502 relative branches. The Hex add & Subtract
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; features of the APPLE ][ monitor may be used to
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; calculate displacements.
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;
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SW16BR CLC
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LDA (Reg15),Y ;Get displacement byte
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BPL LD1B9
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DEY ;=$FF (-1)
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LD1B9 ADC Reg15 ;Add to SW16 PC
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|
STA Reg15
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|
TYA
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|
ADC Reg15+1
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|
STA Reg15+1
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JMP LD011
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;
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|
; A branch is effected only if the carry is set. Branch
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|
; conditions are not changed.
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|
;
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|
SW16BC BCS SW16BR
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JMP LD011
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|
;
|
|
; A branch to the effective address is taken only is the
|
|
; carry is clear, otherwise execution resumes as normal
|
|
; with the next instruction. Branch conditions are
|
|
; not changed.
|
|
;
|
|
SW16BNC BCC SW16BR
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|
JMP LD011
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|
;
|
|
; A branch is effected only if the prior 'result' (or most
|
|
; recently transferred data) was positive. Branch
|
|
; conditions are not changed
|
|
;
|
|
SW16BP LDA Reg0+1,X ;Need to chk hi-byte only
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|
BPL SW16BR
|
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JMP LD011
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|
;
|
|
; A branch is effected only if prior 'result' was minus.
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|
; Branch conditions are not changed.
|
|
;
|
|
SW16BM LDA Reg0+1,X ;Need to chk hi-byte only
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|
BMI SW16BR
|
|
JMP LD011
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|
;
|
|
; A Branch is effected only if the prior 'result' was zero.
|
|
; Branch conditions are not changed.
|
|
;
|
|
SW16BZ LDA Reg0,X
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|
ORA Reg0+1,X
|
|
BEQ SW16BR
|
|
JMP LD011
|
|
;
|
|
; A branch is effected only if the prior 'result' was
|
|
; non-zero. Branch conditions are not changed.
|
|
;
|
|
SW16BNZ LDA Reg0,X
|
|
ORA Reg0+1,X
|
|
BNE SW16BR
|
|
JMP LD011
|
|
;
|
|
; A branch is effected only if the prior 'result' was -1
|
|
; ($FFFF Hex). Branch conditions are not changed.
|
|
;
|
|
SW16BM1 LDA Reg0,X ;Get 'prior result' register
|
|
AND Reg0+1,X
|
|
EOR #-1
|
|
BEQ SW16BR
|
|
JMP LD011
|
|
;
|
|
; A branch effected only if the prior 'result' was NOT
|
|
; -1 ($FFFF). Branch conditions are not changed.
|
|
;
|
|
SW16BNM1 LDA Reg0,X
|
|
AND Reg0+1,X
|
|
EOR #-1
|
|
BNE SW16BR
|
|
JMP LD011
|
|
;
|
|
; RS terminates execution of a SWEET16 subroutine and
|
|
; returns to the SWEET 16 calling program which resumes
|
|
; execution (in SWEET 16 mode). R12, which is the SWEET16
|
|
; subroutine return stack pointer, is decremented twice.
|
|
; Branch conditions are not changed.
|
|
;
|
|
SW16RS LDX #Reg12 ;12;2 for R12 as stack pointer
|
|
LDA Reg12
|
|
BNE LD20D
|
|
DEC Reg12+1
|
|
LD20D DEC Reg12
|
|
LDA (Reg0,X) ;Get byte from SW16 stack
|
|
STA Reg15+1 ;Modify the PC
|
|
LDA Reg12
|
|
BNE LD219
|
|
DEC Reg12+1
|
|
LD219 DEC Reg12
|
|
LDA (Reg0,X)
|
|
STA Reg15
|
|
JMP LD011
|
|
;
|
|
; $D222 The 2-byte constant is loaded into Rn (n=0-F) and
|
|
; branch conditions set accordingly. Carry is cleared.
|
|
; Output
|
|
; Rn
|
|
;
|
|
SW16SET LDA (Reg15),Y ;Get hi-byte of constant
|
|
STA Reg0+1,X
|
|
DEY
|
|
LDA (Reg15),Y ;Lo-byte of constant
|
|
STA Reg0,X
|
|
TYA ;Y=1
|
|
SEC ;Add 2 to SW16 PC
|
|
ADC Reg15
|
|
STA Reg15
|
|
BCC LD235
|
|
INC Reg15+1
|
|
LD235 JMP LD011
|
|
;
|
|
; Usage: CPIM constant
|
|
; The contents of the ACC is compared against the
|
|
; 2-byte constant by performing the 16-bit binary
|
|
; subtraction ACC-CONSTANT and storing the low order 16
|
|
; difference bits in R13 for subsequent branch tests.
|
|
; If the 16-bit unsigned ACC contents are greater
|
|
; than or equal to the 16-bit unsigned CONSTANT,
|
|
; then the carry is set, otherwise it is cleared.
|
|
; No other registers, are disturbed.
|
|
;
|
|
SW16CPIM SEC ;(Y)=0
|
|
LDX #Reg13 ;13;2
|
|
LDA Reg0
|
|
SBC (Reg15),Y
|
|
STA Reg0,X
|
|
INC Reg15
|
|
BNE LD247
|
|
INC Reg15+1
|
|
LD247 LDA Reg0+1
|
|
SBC (Reg15),Y
|
|
STA Reg0+1,X
|
|
TXA ;=26
|
|
ADC #0
|
|
STA Reg14+1 ;=27 if there's a C
|
|
JMP LD011
|
|
;
|
|
; A branch to the effective address (PC + 3 + d) is taken
|
|
; and execution is resumed in SWEET 16 mode. The current PC
|
|
; is pushed onto a SWEET 16 subroutine return address
|
|
; stack whose pointer is R12, and R12 is incremented by 2.
|
|
; The carry is cleared and branch conditions set to
|
|
; indicate the current ACC contents.
|
|
;
|
|
SW16BSL LDX #Reg12 ;12;2 (SW16 stack register)
|
|
LDA Reg15 ;PC
|
|
STA (Reg0,X)
|
|
INC Reg12
|
|
BNE LD261
|
|
INC Reg12+1
|
|
LD261 LDA Reg15+1
|
|
STA (Reg0,X)
|
|
INC Reg12
|
|
BNE SW16BRL
|
|
INC Reg12+1
|
|
;
|
|
; An effective address (ea) is calculated by adding the
|
|
; signed displacement word (d) to the PC. The PC contains
|
|
; the address of the instruction immediately following the
|
|
; BRL, or the address of the BRL op plus 3. The
|
|
; displacement is a signed two's complement value from
|
|
; -32768 ($8000) to +32767 ($7FFF).
|
|
; Branch conditions are not changed.
|
|
;
|
|
SW16BRL CLC
|
|
LDA (Reg15),Y
|
|
INC Reg15
|
|
BNE LD274
|
|
INC Reg15+1
|
|
LD274 ADC Reg15
|
|
TAX
|
|
LDA (Reg15),Y
|
|
ADC Reg15+1
|
|
STA Reg15+1
|
|
STX Reg15
|
|
JMP LD011
|
|
;=================================================
|