2013-01-12 22:44:42 +00:00
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/*
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* Copyright (c) 2013, Texas Instruments Incorporated - http://www.ti.com/
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* 3. Neither the name of the copyright holder nor the names of its
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* contributors may be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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* COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
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* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
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* OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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/*
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* cc2538 linker configuration file. This is not the actual file used at link
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* stage. Rather, it is used as input for the auto-generation of the actual
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* ld script, which is called cc2538.ld and will be in the project directory
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*/
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#if (LPM_CONF_MAX_PM==2) && (LPM_CONF_ENABLE != 0)
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2013-11-25 14:43:37 +00:00
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#define NRSRAM_START 0x20000000
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#define NRSRAM_LEN 0x00004000
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#define SRAM_START 0x20004000
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#define SRAM_LEN 0x00004000
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2013-01-12 22:44:42 +00:00
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#else
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2013-11-25 14:43:37 +00:00
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#define SRAM_START 0x20000000
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#define SRAM_LEN 0x00008000
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2013-01-12 22:44:42 +00:00
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#endif
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2014-05-02 15:35:58 +00:00
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#ifdef FLASH_CONF_ORIGIN
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#define FLASH_ORIGIN FLASH_CONF_ORIGIN
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#else
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#error FLASH_CONF_ORIGIN is not specified. Please define FLASH_CONF_ORIGIN in contiki-conf.h.
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#endif
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#ifdef FLASH_CONF_SIZE
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#define FLASH_SIZE FLASH_CONF_SIZE
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#else
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#error FLASH_CONF_SIZE is not specified. Please define FLASH_CONF_SIZE in contiki-conf.h.
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#endif
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#define FLASH_CCA_LENGTH 44
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#define FLASH_LENGTH (FLASH_SIZE - FLASH_CCA_LENGTH)
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#define FLASH_CCA_ORIGIN (FLASH_ORIGIN + FLASH_LENGTH)
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2013-01-12 22:44:42 +00:00
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MEMORY
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{
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2014-05-02 15:35:58 +00:00
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FLASH (rx) : ORIGIN = FLASH_ORIGIN, LENGTH = FLASH_LENGTH
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FLASH_CCA (RX) : ORIGIN = FLASH_CCA_ORIGIN, LENGTH = FLASH_CCA_LENGTH
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2013-11-25 14:43:37 +00:00
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#if (LPM_CONF_MAX_PM==2) && (LPM_CONF_ENABLE != 0)
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NRSRAM (RWX) : ORIGIN = NRSRAM_START, LENGTH = NRSRAM_LEN
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#endif
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2013-01-12 22:44:42 +00:00
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SRAM (RWX) : ORIGIN = SRAM_START, LENGTH = SRAM_LEN
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}
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SECTIONS
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{
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.text :
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{
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_text = .;
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KEEP(*(.vectors))
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*(.text*)
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*(.rodata*)
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_etext = .;
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} > FLASH= 0
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cc2538: Move SoC data to a dedicated section to save space
Some SoC data requires huge alignments. E.g., the µDMA channel control table has
to be 1024-byte aligned. This table was simply aligned to 1024 bytes in the C
code, which had the following consequences, wasting a lot of RAM:
- As this table could be placed anywhere in .bss, there could be an alignment
gap of up to 1023 bytes between the preceding data and this table.
- The size of this table was also aligned to 1024 bytes, regardless of
UDMA_CONF_MAX_CHANNEL, making this configuration option supposed to save RAM
just useless.
- .bss was also aligned to at least 1024 bytes, creating a huge alignment gap
between .data and .bss.
Instead of relying on the compiler to force this alignment, and on the linker to
automatically place data, this change places carefully such SoC data in RAM
using the linker script. A dedicated section is created to place such SoC data
requiring huge alignments, and it is put at the beginning of the SRAM in order
to ensure a maximal alignment without any gap. In this way, the alignment of
.bss also remains normal, and the size of this table is not constrained by its
alignment, but only by its contents (i.e. by UDMA_CONF_MAX_CHANNEL).
In the case of the µDMA channel control table, the data is still zeroed by
udma_init() (instead of also being zeroed as part of .bss).
Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
2013-12-19 20:30:35 +00:00
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.socdata (NOLOAD) :
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{
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*(.udma_channel_control_table)
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} > SRAM
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2013-01-12 22:44:42 +00:00
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.data :
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{
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_data = .;
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*(.data*)
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_edata = .;
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} > SRAM AT > FLASH
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.ARM.exidx :
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{
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*(.ARM.exidx*)
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} > FLASH
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.bss :
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{
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_bss = .;
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*(.bss*)
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*(COMMON)
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_ebss = .;
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} > SRAM
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2013-11-25 14:43:37 +00:00
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#if (LPM_CONF_MAX_PM==2) && (LPM_CONF_ENABLE != 0)
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2013-12-13 16:06:48 +00:00
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.nrdata (NOLOAD) :
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2013-11-25 14:43:37 +00:00
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{
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_nrdata = .;
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*(.nrdata*)
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_enrdata = .;
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} > NRSRAM
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#endif
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2013-01-12 22:44:42 +00:00
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.flashcca :
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{
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KEEP(*(.flashcca))
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} > FLASH_CCA
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}
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