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69 lines
3.1 KiB
C
69 lines
3.1 KiB
C
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/*
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* Copyright (c) 2012, Texas Instruments Incorporated - http://www.ti.com/
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* 3. Neither the name of the copyright holder nor the names of its
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* contributors may be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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* COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
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* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
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* OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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/**
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* \addtogroup cc2538
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* @{
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*
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* \defgroup cc2538-mpu cc2538 Memory Protection Unit
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*
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* Driver for the cc2538 Memory Protection Unit
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* @{
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*
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* \file
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* Header file for the ARM Memory Protection Unit
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*/
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#ifndef MPU_H_
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#define MPU_H_
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#define MPU_MPU_TYPE 0xE000ED90 /**< MPU Type */
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#define MPU_MPU_CTRL 0xE000ED94 /**< MPU Control */
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#define MPU_MPU_NUMBER 0xE000ED98 /**< MPU Region Number */
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#define MPU_MPU_BASE 0xE000ED9C /**< MPU Region Base Address */
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#define MPU_MPU_ATTR 0xE000EDA0 /**< MPU Region Attribute and Size */
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#define MPU_MPU_BASE1 0xE000EDA4 /**< MPU Region Base Address Alias 1 */
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#define MPU_MPU_ATTR1 0xE000EDA8 /**< MPU Region Attribute and Size Alias 1 */
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#define MPU_MPU_BASE2 0xE000EDAC /**< MPU Region Base Address Alias 2 */
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#define MPU_MPU_ATTR2 0xE000EDB0 /**< MPU Region Attribute and Size Alias 2*/
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#define MPU_MPU_BASE3 0xE000EDB4 /**< MPU Region Base Address Alias 3 */
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#define MPU_MPU_ATTR3 0xE000EDB8 /**< MPU Region Attribute and Size Alias 3*/
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#define MPU_DBG_CTRL 0xE000EDF0 /**< Debug Control and Status Reg */
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#define MPU_DBG_XFER 0xE000EDF4 /**< Debug Core Reg. Transfer Select */
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#define MPU_DBG_DATA 0xE000EDF8 /**< Debug Core Register Data */
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#define MPU_DBG_INT 0xE000EDFC /**< Debug Reset Interrupt Control */
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#define MPU_SW_TRIG 0xE000EF00 /**< Software Trigger Interrupt */
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#endif /* MPU_H_ */
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/**
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* @}
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* @}
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*/
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