2007-08-20 11:01:13 +00:00
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#include <signal.h>
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#define CC1020_MAIN 0x00
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#define CC1020_INTERFACE 0x01
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#define CC1020_RESET 0x02
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#define CC1020_SEQUENCING 0x03
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#define CC1020_FREQ_2A 0x04
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#define CC1020_FREQ_1A 0x05
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#define CC1020_FREQ_0A 0x06
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#define CC1020_CLOCK_A 0x07
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#define CC1020_FREQ_2B 0x08
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#define CC1020_FREQ_1B 0x09
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#define CC1020_FREQ_0B 0x0A
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#define CC1020_CLOCK_B 0x0B
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#define CC1020_VCO 0x0C
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#define CC1020_MODEM 0x0D
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#define CC1020_DEVIATION 0x0E
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#define CC1020_AFC_CONTROL 0x0F
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#define CC1020_FILTER 0x10
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#define CC1020_VGA1 0x11
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#define CC1020_VGA2 0x12
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#define CC1020_VGA3 0x13
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#define CC1020_VGA4 0x14
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#define CC1020_LOCK 0x15
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#define CC1020_FRONTEND 0x16
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#define CC1020_ANALOG 0x17
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#define CC1020_BUFF_SWING 0x18
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#define CC1020_BUFF_CURRENT 0x19
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#define CC1020_PLL_BW 0x1A
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#define CC1020_CALIBRATE 0x1B
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#define CC1020_PA_POWER 0x1C
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#define CC1020_MATCH 0x1D
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#define CC1020_PHASE_COMP 0x1E
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#define CC1020_GAIN_COMP 0x1F
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#define CC1020_POWERDOWN 0x20
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#define CC1020_TEST1 0x21
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#define CC1020_TEST2 0x22
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#define CC1020_TEST3 0x23
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#define CC1020_TEST4 0x24
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#define CC1020_TEST5 0x25
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#define CC1020_TEST6 0x26
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#define CC1020_TEST7 0x27
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#define CC1020_STATUS 0x40
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#define CC1020_RESET_DONE 0x41
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#define CC1020_RSS 0x42
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#define CC1020_AFC 0x43
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#define CC1020_GAUSS_FILTER 0x44
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#define CC1020_STATUS1 0x45
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#define CC1020_STATUS2 0x46
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#define CC1020_STATUS3 0x47
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#define CC1020_STATUS4 0x48
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#define CC1020_STATUS5 0x49
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#define CC1020_STATUS6 0x4A
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#define CC1020_STATUS7 0x4B
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// For CC1020_STATUS
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#define LOCK_CONTINUOUS 0x10
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#define CAL_COMPLETE 0x80
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#define PA_POWER 0x0F // initial default for output power
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#define LOCK_NOK 0x00
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#define LOCK_OK 0x01
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#define LOCK_RECAL_OK 0x02
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#define CAL_TIMEOUT 0x7FFE
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#define LOCK_TIMEOUT 0x7FFE
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#define RESET_TIMEOUT 0x7FFE
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#define TX_CURRENT 0x87
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#define RX_CURRENT 0x86
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// CC1020 driver configuration
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#define CC1020_BUFFERSIZE 250
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// PDI (Data in) is on P21
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#define PDO (P2IN & 0x01)
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// PSEL is on P30 and low active
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#define PSEL_ON do { P3OUT &= ~0x01; } while(0)
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#define PSEL_OFF do { P3OUT |= 0x01; } while(0)
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#define PCLK_HIGH do { P2OUT |= 0x08; } while(0)
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#define PCLK_LOW do { P2OUT &= ~0x08; } while(0)
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// PDO (Data out) is on P22
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#define PDI_HIGH do { P2OUT |= 0x02; } while(0)
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#define PDI_LOW do { P2OUT &= ~0x02; } while(0)
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// Enable power for LNA (P24, low-active)
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#define LNA_POWER_ON() do { P2OUT &= ~0x10; } while(0)
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#define LNA_POWER_OFF() do { P2OUT |= 0x10; } while(0)
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#define CC_LOCK (P2IN & 0x04)
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#define DISABLE_RX_IRQ() \
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do { IE1 &= ~(URXIE0); } while(0)
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#define ENABLE_RX_IRQ() \
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do { IFG1 &= ~URXIFG0; IE1 |= URXIE0; } while(0)
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#define ACK_TIMEOUT_115 4 // In RADIO_STROKE ticks
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#define ACK_TIMEOUT_19 16
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#define MHZ_869525 1
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const u8_t cc1020_config_19200[41] = {
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0x01, // 0x00, MAIN
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0x0F, // 0x01, INTERFACE
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0xFF, // 0x02, RESET
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0x8F, // 0x03, SEQUENCING
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// 869.525 at 50kHz
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0x3A, // 0x04, FREQ_2A
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0x32, // 0x05, FREQ_1A
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0x97, // 0x06, FREQ_0A // 19200
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0x38, // 0x07, CLOCK_A // 19200
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0x3A, // 0x08, FREQ_2B
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0x37, // 0x09, FREQ_1B
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0xEB, // 0x0A, FREQ_0B // 19200
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0x38, // 0x0B, CLOCK_B // 19200
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0x44, // 0x0C, VCO 44
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0x51, // 0x0D, MODEM Manchester
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0x2B, // 0x0E, DEVIATION // FSK
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0x4C, // 0x0F, AFC_CONTROL Ruetten 0xCC
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0x25, // 0x10, FILTER Bandwith 100 kHz
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0x61, // 0x11, VGA1
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0x55, // 0x12, VGA2
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0x2D, // 0x13, VGA3
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0x37, // 0x14, VGA4 // 0x29, VGA4 ADJUSTED CS to 23!
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0x40, // 0x15, LOCK is Carrier SENSE
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0x76, // 0x16, FRONTEND
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0x87, // 0x17, ANALOG, RX=86/TX=87
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0x10, // 0x18, BUFF_SWING
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0x25, // 0x19, BUFF_CURRENT
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0xAE, // 0x1A, PLL_BW
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0x34, // 0x1B, CALIBRATE
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PA_POWER, // 0x1C, PA_POWER AN025 = 0xA0
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0xF0, // 0x1D, MATCH
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0x00, // 0x1E, PHASE_COMP
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0x00, // 0x1F, GAIN_COMP
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0x00, // 0x20, POWERDOWN
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0x4d, // 0x4d, // 0x21,
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0x10, // 0x10, // 0x22,
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0x06, // 0x06, // 0x23,
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0x00, // 0x00, // 0x24,
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0x40, // 0x40, // 0x25,
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0x00, // 0x00, // 0x26,
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0x00, // 0x00, // 0x27,
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// Not in real config of chipCon from here!!!
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ACK_TIMEOUT_19
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};
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const u8_t cc1020_config_115200[41] = {
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0x01, // 0x00, MAIN
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0x0F, // 0x01, INTERFACE
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0xFF, // 0x02, RESET
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0x8F, // 0x03, SEQUENCING
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// 869.525 at 200kHz
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0x3A, // 0x04, FREQ_2A
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0x32, // 0x05, FREQ_1A
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0x97, // 0x06, FREQ_0A // 19200
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0x29, // 0x07, CLOCK_A // 19200
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0x3A, // 0x08, FREQ_2B
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0x37, // 0x09, FREQ_1B
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0xEB, // 0x0A, FREQ_0B // 19200
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0x29, // 0x0B, CLOCK_B // 19200
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0x44, // 0x0C, VCO 44
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0x51, // 0x0D, MODEM Manchester
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0x58, // 0x0E, DEVIATION // FSK
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0x4C, // 0x0F, AFC_CONTROL Ruetten 0xCC
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0x80, // 0x10, FILTER Bandwith 500 kHz
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0x61, // 0x11, VGA1
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0x55, // 0x12, VGA2
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0x30, // 0x13, VGA3
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0x35, // 0x14, VGA4
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0x20, // 0x15, LOCK is Carrier SENSE
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0x76, // 0x16, FRONTEND
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0x87, // 0x17, ANALOG, RX=86/TX=87
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0x10, // 0x18, BUFF_SWING
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0x25, // 0x19, BUFF_CURRENT
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0xAE, // 0x1A, PLL_BW
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0x34, // 0x1B, CALIBRATE
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PA_POWER, // 0x1C, PA_POWER AN025 = 0xA0
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0xF0, // 0x1D, MATCH
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0x00, // 0x1E, PHASE_COMP
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0x00, // 0x1F, GAIN_COMP
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0x00, // 0x20, POWERDOWN
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0x4d, // 0x21,
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0x10, // 0x22,
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0x06, // 0x23,
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0x00, // 0x24,
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0x40, // 0x25,
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0x00, // 0x26,
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0x00, // 0x27,
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// Not in real config of chipCon from here!!!
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ACK_TIMEOUT_115
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};
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/// cc1020 state
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enum cc1020_state {
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CC1020_OFF,
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CC1020_RX,
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CC1020_TX
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};
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/******************************************************************************
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* @name Packet specification
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* @{
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*/
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const u8_t syncword[2] = {0xD3,0x91};
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__attribute__((packed))
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struct cc1020_header {
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u8_t length; // header: number of bytes in packet including header
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};
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#define PREAMBLESIZE 6
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#define PREAMBLE 0xAA
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#define TAILSIZE 2
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#define TAIL 0xFA
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#define SYNCWDSIZE (sizeof (syncword))
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#define HDRSIZE (sizeof (struct cc1020_header))
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///@}
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/// cc1020 receiver state
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enum cc1020_rxstate {
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CC1020_RX_SEARCHING, // searching for preamble + sync word
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CC1020_RX_RECEIVE, // receiving bytes
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CC1020_RX_PROCESSING // processing data in buffer
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};
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