contiki/cpu/x86/drivers/quarkX1000/i2c-registers.h

/*
 * Copyright (C) 2015, Intel Corporation. All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 * 1. Redistributions of source code must retain the above copyright
 *    notice, this list of conditions and the following disclaimer.
 * 2. Redistributions in binary form must reproduce the above copyright
 *    notice, this list of conditions and the following disclaimer in the
 *    documentation and/or other materials provided with the distribution.
 *
 * 3. Neither the name of the copyright holder nor the names of its
 *    contributors may be used to endorse or promote products derived
 *    from this software without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE
 * COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
 * OF THE POSSIBILITY OF SUCH DAMAGE.
 */

#ifndef CPU_X86_DRIVERS_QUARKX1000_I2C_REGISTERS_H_
#define CPU_X86_DRIVERS_QUARKX1000_I2C_REGISTERS_H_

#define QUARKX1000_IC_CON            0x00
#define QUARKX1000_IC_TAR            0x04
#define QUARKX1000_IC_DATA_CMD       0x10
#define QUARKX1000_IC_SS_SCL_HCNT    0x14
#define QUARKX1000_IC_SS_SCL_LCNT    0x18
#define QUARKX1000_IC_FS_SCL_HCNT    0x1C
#define QUARKX1000_IC_FS_SCL_LCNT    0x20
#define QUARKX1000_IC_INTR_STAT      0x2C
#define QUARKX1000_IC_INTR_MASK      0x30
#define QUARKX1000_IC_RAW_INTR_STAT  0x34
#define QUARKX1000_IC_RX_TL          0x38
#define QUARKX1000_IC_TX_TL          0x3C
#define QUARKX1000_IC_CLR_INTR       0x40
#define QUARKX1000_IC_CLR_RX_UNDER   0x44
#define QUARKX1000_IC_CLR_RX_OVER    0x48
#define QUARKX1000_IC_CLR_TX_OVER    0x4C
#define QUARKX1000_IC_CLR_RD_REQ     0x50
#define QUARKX1000_IC_CLR_TX_ABRT    0x54
#define QUARKX1000_IC_CLR_ACTIVITY   0x5C
#define QUARKX1000_IC_CLR_STOP_DET   0x60
#define QUARKX1000_IC_CLR_START_DET  0x64
#define QUARKX1000_IC_ENABLE         0x6C
#define QUARKX1000_IC_STATUS         0x70
#define QUARKX1000_IC_TXFLR          0x74
#define QUARKX1000_IC_RXFLR          0x78
#define QUARKX1000_IC_SDA_HOLD       0x7C
#define QUARKX1000_IC_TX_ABRT_SOURCE 0x80
#define QUARKX1000_IC_ENABLE_STATUS  0x9C
#define QUARKX1000_IC_FS_SPKLEN      0xA0

#define QUARKX1000_IC_HIGHEST        QUARKX1000_IC_FS_SPKLEN

/* IC_CON */
#define QUARKX1000_IC_CON_MASTER_MODE_SHIFT         0
#define QUARKX1000_IC_CON_MASTER_MODE_MASK       0x01
#define QUARKX1000_IC_CON_SPEED_SHIFT               1
#define QUARKX1000_IC_CON_SPEED_MASK             0x06
#define QUARKX1000_IC_CON_10BITADDR_MASTER_SHIFT    4
#define QUARKX1000_IC_CON_10BITADDR_MASTER_MASK  0x10
#define QUARKX1000_IC_CON_RESTART_EN_SHIFT          5
#define QUARKX1000_IC_CON_RESTART_EN_MASK        0x20

/* IC_TAR */
#define QUARKX1000_IC_TAR_SHIFT     0
#define QUARKX1000_IC_TAR_MASK  0x3FF

/* IC_DATA_CMD */
#define QUARKX1000_IC_DATA_CMD_DAT_SHIFT         0
#define QUARKX1000_IC_DATA_CMD_DAT_MASK      0x0FF
#define QUARKX1000_IC_DATA_CMD_CMD_SHIFT         8
#define QUARKX1000_IC_DATA_CMD_CMD_MASK      0x100
#define QUARKX1000_IC_DATA_CMD_STOP_SHIFT        9
#define QUARKX1000_IC_DATA_CMD_STOP_MASK     0x200
#define QUARKX1000_IC_DATA_CMD_RESTART_SHIFT    10
#define QUARKX1000_IC_DATA_CMD_RESTART_MASK  0x400

/* IC_SS_SCL_HCNT */
#define QUARKX1000_IC_SS_SCL_HCNT_SHIFT      0
#define QUARKX1000_IC_SS_SCL_HCNT_MASK  0xFFFF

/* IC_SS_SCL_LCNT */
#define QUARKX1000_IC_SS_SCL_LCNT_SHIFT      0
#define QUARKX1000_IC_SS_SCL_LCNT_MASK  0xFFFF

/* IC_FS_SCL_HCNT */
#define QUARKX1000_IC_FS_SCL_HCNT_SHIFT      0
#define QUARKX1000_IC_FS_SCL_HCNT_MASK  0xFFFF

/* IC_FS_SCL_LCNT */
#define QUARKX1000_IC_FS_SCL_LCNT_SHIFT      0
#define QUARKX1000_IC_FS_SCL_LCNT_MASK  0xFFFF

/* IC_INTR_STAT */
#define QUARKX1000_IC_INTR_STAT_RX_UNDER_SHIFT      0
#define QUARKX1000_IC_INTR_STAT_RX_UNDER_MASK   0x001
#define QUARKX1000_IC_INTR_STAT_RX_OVER_SHIFT       1
#define QUARKX1000_IC_INTR_STAT_RX_OVER_MASK    0x002
#define QUARKX1000_IC_INTR_STAT_RX_FULL_SHIFT       2
#define QUARKX1000_IC_INTR_STAT_RX_FULL_MASK    0x004
#define QUARKX1000_IC_INTR_STAT_TX_OVER_SHIFT       3
#define QUARKX1000_IC_INTR_STAT_TX_OVER_MASK    0x008
#define QUARKX1000_IC_INTR_STAT_TX_EMPTY_SHIFT      4
#define QUARKX1000_IC_INTR_STAT_TX_EMPTY_MASK   0x010
#define QUARKX1000_IC_INTR_STAT_RD_REQ_SHIFT        5
#define QUARKX1000_IC_INTR_STAT_RD_REQ_MASK     0x020
#define QUARKX1000_IC_INTR_STAT_TX_ABRT_SHIFT       6
#define QUARKX1000_IC_INTR_STAT_TX_ABRT_MASK    0x040
#define QUARKX1000_IC_INTR_STAT_ACTIVITY_SHIFT      8
#define QUARKX1000_IC_INTR_STAT_ACTIVITY_MASK   0x100
#define QUARKX1000_IC_INTR_STAT_STOP_DET_SHIFT      9
#define QUARKX1000_IC_INTR_STAT_STOP_DET_MASK   0x200
#define QUARKX1000_IC_INTR_STAT_START_DET_SHIFT    10
#define QUARKX1000_IC_INTR_STAT_START_DET_MASK  0x400

/* IC_ENABLE */
#define QUARKX1000_IC_ENABLE_SHIFT    0
#define QUARKX1000_IC_ENABLE_MASK  0x01

/* IC_STATUS */
#define QUARKX1000_IC_STATUS_ACTIVITY_SHIFT        0
#define QUARKX1000_IC_STATUS_ACTIVITY_MASK      0x01
#define QUARKX1000_IC_STATUS_TFNF_SHIFT            1
#define QUARKX1000_IC_STATUS_TFNF_MASK          0x02
#define QUARKX1000_IC_STATUS_TFE_SHIFT             2
#define QUARKX1000_IC_STATUS_TFE_MASK           0x04
#define QUARKX1000_IC_STATUS_RFNE_SHIFT            3
#define QUARKX1000_IC_STATUS_RFNE_MASK          0x08
#define QUARKX1000_IC_STATUS_RFF_SHIFT             4
#define QUARKX1000_IC_STATUS_RFF_MASK           0x10
#define QUARKX1000_IC_STATUS_MST_ACTIVITY_SHIFT    5
#define QUARKX1000_IC_STATUS_MST_ACTIVITY_MASK  0x20

/* IC_TXFLR */
#define QUARKX1000_IC_TXFLR_SHIFT    0
#define QUARKX1000_IC_TXFLR_MASK  0x1F

/* IC_RXFLR */
#define QUARKX1000_IC_RXFLR_SHIFT    0
#define QUARKX1000_IC_RXFLR_MASK  0x1F

/* IC_FS_SPKLEN */
#define QUARKX1000_IC_FS_SPKLEN_SHIFT    0
#define QUARKX1000_IC_FS_SPKLEN_MASK  0xFF

#endif /* CPU_X86_DRIVERS_QUARKX1000_I2C_REGISTERS_H_ */