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66 lines
2.5 KiB
C
66 lines
2.5 KiB
C
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/*
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* Copyright (C) 2015, Intel Corporation. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* 3. Neither the name of the copyright holder nor the names of its
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* contributors may be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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* COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
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* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
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* OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef CPU_X86_MM_PAGING_H_
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#define CPU_X86_MM_PAGING_H_
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#include <stdint.h>
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/**
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* Page table entry format for PAE mode page table. See Intel Combined Manual,
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* Vol. 3, Section 4.4 for more details.
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*/
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typedef union pte {
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struct {
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uint64_t present : 1;
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uint64_t writable : 1;
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uint64_t user_accessible : 1;
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uint64_t pwt : 1; /**< Specify write-through cache policy */
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uint64_t pcd : 1; /**< Disable caching */
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uint64_t accessed : 1;
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uint64_t dirty : 1;
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uint64_t : 5;
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uint64_t addr : 51;
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uint64_t exec_disable : 1;
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};
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uint64_t raw;
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} pte_t;
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#define ENTRIES_PER_PDPT 4
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#define ENTRIES_PER_PAGE_TABLE 512
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typedef pte_t pdpt_t[ENTRIES_PER_PDPT];
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typedef pte_t page_table_t[ENTRIES_PER_PAGE_TABLE];
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#define MIN_PAGE_SIZE_SHAMT 12
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#define MIN_PAGE_SIZE (1 << MIN_PAGE_SIZE_SHAMT)
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#endif /* CPU_X86_MM_PAGING_H_ */
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