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Add support for the CC13xx CPU

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This commit:

* Moves all cpu files from cpu/cc26xx to cpu/cc26xx-cc13xx
* Bumps the CC26xxware submodule to the latest TI release
* Adds CC13xxware as a submodule
* Adds support for sub-ghz mode / IEEE 802.15.4g
* Splits the driver into multiple files for clarity. We now have the following structure:
  * A common module that handles access to the RF core, interrupts etc
  * A module that takes care of BLE functionality
  * A netstack radio driver for IEEE mode (2.4GHz)
  * A netstack radio driver for PROP mode (sub-ghz - multiple bands)

This commit also adds tick suppression functionality, applicable to all chips of the CC26xx and CC13xx families. Instead waking up on every clock tick simply to increment our software counter, we now only wake up just in time to service the next scheduled etimer. ContikiMAC-triggered wakeups are unaffected.

Laslty, this commit also applies a number of minor changes:
* Addition of missing includes
* Removal of stub functions
* Removal of a woraround for a CC26xxware bug that has now been fixed
This commit is contained in:
Jonas Olsson 2015-08-16 16:30:04 +01:00
parent 6c6a1af70d
commit 01e36532c2
58 changed files with 8595 additions and 7565 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

7
.gitmodules vendored
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@ -4,6 +4,9 @@
[submodule "tools/cc2538-bsl"]
path = tools/cc2538-bsl
url = https://github.com/JelmerT/cc2538-bsl.git
[submodule "cpu/cc26xx/lib/cc26xxware"]
path = cpu/cc26xx/lib/cc26xxware
[submodule "cpu/cc26xx-cc13xx/lib/cc26xxware"]
path = cpu/cc26xx-cc13xx/lib/cc26xxware
url = https://github.com/g-oikonomou/cc26xxware.git
[submodule "cpu/cc26xx-cc13xx/lib/cc13xxware"]
path = cpu/cc26xx-cc13xx/lib/cc13xxware
url = https://github.com/g-oikonomou/cc13xxware.git

7
cpu/cc26xx-cc13xx/Makefile.cc13xx Normal file
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@ -0,0 +1,7 @@
TI_XXWARE_PATH = lib/cc13xxware
CONTIKI_CPU_SOURCEFILES += smartrf-settings.c prop-mode.c
CFLAGS += -DCPU_FAMILY_CC13XX=1
include $(CONTIKI_CPU)/Makefile.cc26xx-cc13xx

3
cpu/cc26xx-cc13xx/Makefile.cc26xx Normal file
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@ -0,0 +1,3 @@
TI_XXWARE_PATH = lib/cc26xxware
include $(CONTIKI_CPU)/Makefile.cc26xx-cc13xx

30
cpu/cc26xx/Makefile.cc26xx → cpu/cc26xx-cc13xx/Makefile.cc26xx-cc13xx
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@ -8,25 +8,24 @@ NM = arm-none-eabi-nm
SIZE = arm-none-eabi-size
SREC_CAT = srec_cat
CPU_ABS_PATH = cpu/cc26xx
TI_CC26XXWARE_PATH = lib/cc26xxware
TI_CC26XXWARE = $(CONTIKI_CPU)/$(TI_CC26XXWARE_PATH)
CPU_ABS_PATH = cpu/cc26xx-cc13xx
TI_XXWARE = $(CONTIKI_CPU)/$(TI_XXWARE_PATH)
### cc26xxware sources under driverlib will be added to the MODULES list
TI_CC26XXWARE_SRC = $(CPU_ABS_PATH)/$(TI_CC26XXWARE_PATH)/driverlib
TI_XXWARE_SRC = $(CPU_ABS_PATH)/$(TI_XXWARE_PATH)/driverlib
### The directory with startup sources will be added to the CONTIKI_CPU_DIRS
### and the sources therein are added to the sources list explicitly. They are
### also listed explicitly in the linker command (through TARGET_STARTFILES),
### to make sure they always get linked in the image
TI_CC26XXWARE_STARTUP_DIR = $(TI_CC26XXWARE_PATH)/startup_files
TI_CC26XXWARE_STARTUP_SRCS = ccfg.c startup_gcc.c
TI_XXWARE_STARTUP_DIR = $(TI_XXWARE_PATH)/startup_files
TI_XXWARE_STARTUP_SRCS = ccfg.c startup_gcc.c
### MODULES will add some of these to the include path, but we need to add
### them earlier to prevent filename clashes with Contiki core files
CFLAGS += -I$(TI_CC26XXWARE) -I$(CONTIKI)/$(TI_CC26XXWARE_SRC)
CFLAGS += -I$(TI_CC26XXWARE)/inc
MODULES += $(TI_CC26XXWARE_SRC)
CFLAGS += -I$(TI_XXWARE) -I$(CONTIKI)/$(TI_XXWARE_SRC)
CFLAGS += -I$(TI_XXWARE)/inc
MODULES += $(TI_XXWARE_SRC)
LDSCRIPT = $(CONTIKI_CPU)/cc26xx.ld
@ -35,10 +34,6 @@ CFLAGS += -ffunction-sections -fdata-sections
CFLAGS += -fshort-enums -fomit-frame-pointer -fno-strict-aliasing
CFLAGS += -Wall -std=c99
### Workaround for driverlib's cpu.h which tests if defined(gcc)
### Delete if it gets fixed or if we stop using the driverlib
CFLAGS += -Dgcc=__GNUC__
LDFLAGS += -mcpu=cortex-m3 -mthumb -mlittle-endian -nostartfiles
LDFLAGS += -T $(LDSCRIPT)
LDFLAGS += -Wl,--gc-sections,--sort-section=alignment
@ -62,23 +57,24 @@ endif
CLEAN += symbols.c symbols.h *.d *.elf *.hex
### CPU-dependent directories
CONTIKI_CPU_DIRS = . dev dev/rfc-api $(TI_CC26XXWARE_STARTUP_DIR)
CONTIKI_CPU_DIRS = . dev rf-core rf-core/api $(TI_XXWARE_STARTUP_DIR)
### Use the existing debug I/O in cpu/arm/common
CONTIKI_CPU_DIRS += ../arm/common/dbg-io
### CPU-dependent source files
CONTIKI_CPU_SOURCEFILES += clock.c rtimer-arch.c cc26xx-rtc.c uart.c
CONTIKI_CPU_SOURCEFILES += cc26xx-rf.c contiki-watchdog.c
CONTIKI_CPU_SOURCEFILES += clock.c rtimer-arch.c soc-rtc.c uart.c
CONTIKI_CPU_SOURCEFILES += contiki-watchdog.c
CONTIKI_CPU_SOURCEFILES += putchar.c ieee-addr.c batmon-sensor.c
CONTIKI_CPU_SOURCEFILES += slip-arch.c slip.c cc26xx-uart.c lpm.c
CONTIKI_CPU_SOURCEFILES += gpio-interrupt.c oscillators.c
CONTIKI_CPU_SOURCEFILES += rf-core.c rf-ble.c ieee-mode.c
DEBUG_IO_SOURCEFILES += dbg-printf.c dbg-snprintf.c dbg-sprintf.c strformat.c
CONTIKI_SOURCEFILES += $(CONTIKI_CPU_SOURCEFILES) $(DEBUG_IO_SOURCEFILES)
TARGET_START_SOURCEFILES += fault-handlers.c $(TI_CC26XXWARE_STARTUP_SRCS)
TARGET_START_SOURCEFILES += fault-handlers.c $(TI_XXWARE_STARTUP_SRCS)
TARGET_STARTFILES = $(addprefix $(OBJECTDIR)/,$(call oname, $(TARGET_START_SOURCEFILES)))
### Don't treat the .elf as intermediate

12
cpu/cc26xx/cc26xx.ld → cpu/cc26xx-cc13xx/cc26xx.ld
View File

@ -44,8 +44,11 @@ MEMORY
*/
FLASH_CCFG (RX) : ORIGIN = 0x0001FFA8, LENGTH = 88
/* RAM Size 20KB (PG2.1) */
/* RAM Size 20KB */
SRAM (RWX) : ORIGIN = 0x20000000, LENGTH = 0x00005000
/* Application can use GPRAM region as RAM if cache is disabled in CCFG */
GPRAM (RWX) : ORIGIN = 0x11000000, LENGTH = 0x00002000
}
/*. Highest address of the stack. Used in startup file .*/
@ -99,5 +102,10 @@ SECTIONS
. = . + _Min_Heap_Size;
. = . + _Min_Stack_Size;
. = ALIGN(4);
} >SRAM
} > SRAM
.gpram :
{
} > GPRAM
}

66
cpu/cc26xx/clock.c → cpu/cc26xx-cc13xx/clock.c
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@ -35,30 +35,35 @@
* \defgroup cc26xx-platforms TI CC26xx-powered Platforms
* @{
*
* \defgroup cc26xx The TI CC26xx CPU
* \defgroup cc26xx The TI CC26xx and CC13xx CPUs
*
* This group documents the TI CC26xx and CC13xx CPUs. The two CPU families are
* very similar, with the main difference being related to radio capability.
*
* Documentation in this group should be considered to be applicable to both
* families, unless explicitly stated otherwise.
*
* @{
*
* \addtogroup cc26xx-clocks
* @{
*
* \defgroup cc26xx-software-clock CC26xx Software Clock
* \defgroup cc26xx-software-clock Software Clock
*
* Implementation of the clock module for the cc26xx.
* Implementation of the clock module for the CC26xx and CC13xx.
*
* The software clock uses the facilities provided by the AON RTC driver
* @{
*
* \file
* Software clock implementation for the TI CC26xx
* Software clock implementation for the TI CC13xx/CC26xx
*/
/*---------------------------------------------------------------------------*/
#include "contiki.h"
#include "ti-lib.h"
/*---------------------------------------------------------------------------*/
static volatile clock_time_t count;
static volatile clock_time_t second_countdown;
static volatile unsigned long secs;
static volatile uint64_t count;
/*---------------------------------------------------------------------------*/
static void
power_domain_on(void)
@ -72,8 +77,6 @@ void
clock_init(void)
{
count = 0;
secs = 0;
second_countdown = CLOCK_SECOND;
/*
* Here, we configure GPT0 Timer A, which we subsequently use in
@ -120,33 +123,50 @@ clock_init(void)
CCIF clock_time_t
clock_time(void)
{
return count;
return (clock_time_t)(count & 0xFFFFFFFF);
}
/*---------------------------------------------------------------------------*/
void
clock_update(void)
{
count++;
bool interrupts_disabled;
uint32_t aon_rtc_secs_now;
uint16_t aon_rtc_ticks_now;
interrupts_disabled = ti_lib_int_master_disable();
aon_rtc_secs_now = HWREG(AON_RTC_BASE + AON_RTC_O_SEC);
aon_rtc_ticks_now = HWREG(AON_RTC_BASE + AON_RTC_O_SUBSEC) >> 16;
/* Convert AON RTC ticks to clock tick counter */
count = (aon_rtc_secs_now * CLOCK_SECOND) + (aon_rtc_ticks_now >> 9);
/* Re-enable interrupts */
if(!interrupts_disabled) {
ti_lib_int_master_enable();
}
if(etimer_pending()) {
etimer_request_poll();
}
if(--second_countdown == 0) {
secs++;
second_countdown = CLOCK_SECOND;
}
}
/*---------------------------------------------------------------------------*/
void
clock_set_seconds(unsigned long sec)
{
secs = sec;
}
/*---------------------------------------------------------------------------*/
CCIF unsigned long
clock_seconds(void)
{
return secs;
bool interrupts_disabled;
uint32_t secs_now;
interrupts_disabled = ti_lib_int_master_disable();
secs_now = ti_lib_aon_rtc_sec_get();
/* Re-enable interrupts */
if(!interrupts_disabled) {
ti_lib_int_master_enable();
}
return (unsigned long)secs_now;
}
/*---------------------------------------------------------------------------*/
void

6
cpu/cc26xx/dbg.h → cpu/cc26xx-cc13xx/dbg.h
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@ -32,13 +32,13 @@
* \addtogroup cc26xx
* @{
*
* \defgroup cc26xx-char-io CC26xx Character I/O
* \defgroup cc26xx-char-io CC13xx/CC26xx Character I/O
*
* CC26xx CPU-specific functions for debugging and SLIP I/O
* CC13xx/CC26xx CPU-specific functions for debugging and SLIP I/O
* @{
*
* \file
* Header file for the CC26xx Debug I/O module
* Header file for the CC13xx/CC26xx Debug I/O module
*/
#ifndef DBG_H_
#define DBG_H_

0
cpu/cc26xx/debug-uart.h → cpu/cc26xx-cc13xx/debug-uart.h
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2
cpu/cc26xx/dev/batmon-sensor.c → cpu/cc26xx-cc13xx/dev/batmon-sensor.c
View File

@ -33,7 +33,7 @@
* @{
*
* \file
* Driver for the CC26xx AON battery monitor
* Driver for the CC13xx/CC26xx AON battery monitor
*/
/*---------------------------------------------------------------------------*/
#include "contiki-conf.h"

4
cpu/cc26xx/dev/batmon-sensor.h → cpu/cc26xx-cc13xx/dev/batmon-sensor.h
View File

@ -32,13 +32,13 @@
* \addtogroup cc26xx
* @{
*
* \defgroup cc26xx-batmon CC26xx BatMon sensor driver
* \defgroup cc26xx-batmon CC13xx/CC26xx BatMon sensor driver
*
* Driver for the on-chip battery voltage and chip temperature sensor.
* @{
*
* \file
* Header file for the CC26xx battery monitor
* Header file for the CC13xx/CC26xx battery monitor
*/
/*---------------------------------------------------------------------------*/
#ifndef BATMON_SENSOR_H_

12
cpu/cc26xx/dev/cc26xx-uart.c → cpu/cc26xx-cc13xx/dev/cc26xx-uart.c
View File

@ -27,6 +27,15 @@
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
* OF THE POSSIBILITY OF SUCH DAMAGE.
*/
/*---------------------------------------------------------------------------*/
/**
* \addtogroup cc26xx-uart
* @{
*
* \file
* Implementation of the CC13xx/CC26xx UART driver.
*/
/*---------------------------------------------------------------------------*/
#include "contiki-conf.h"
#include "cc26xx-uart.h"
#include "hw_types.h"
@ -41,6 +50,7 @@
#include <stdint.h>
#include <stdbool.h>
#include <string.h>
/*---------------------------------------------------------------------------*/
/* Which events to trigger a UART interrupt */
#define CC26XX_UART_RX_INTERRUPT_TRIGGERS (UART_INT_RX | UART_INT_RT)
@ -382,3 +392,5 @@ cc26xx_uart_isr(void)
ENERGEST_OFF(ENERGEST_TYPE_IRQ);
}
/*---------------------------------------------------------------------------*/
/** @} */

6
cpu/cc26xx/dev/cc26xx-uart.h → cpu/cc26xx-cc13xx/dev/cc26xx-uart.h
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@ -31,13 +31,13 @@
* \addtogroup cc26xx
* @{
*
* \defgroup cc26xx-uart CC26xx UARTs
* \defgroup cc26xx-uart CC13xx/CC26xx UARTs
*
* Driver for the CC26xx UART controller
* Driver for the CC13xx/CC26xx UART controller
* @{
*
* \file
* Header file for the CC26xx UART driver
* Header file for the CC13xx/CC26xx UART driver
*/
#ifndef CC26XX_UART_H_
#define CC26XX_UART_H_

16
cpu/cc26xx/dev/contiki-watchdog.c → cpu/cc26xx-cc13xx/dev/contiki-watchdog.c
View File

@ -31,16 +31,16 @@
* \addtogroup cc26xx-clocks
* @{
*
* \defgroup cc26xx-wdt CC26xx watchdog timer driver
* \defgroup cc26xx-wdt CC13xx/CC26xx watchdog timer driver
*
* Driver for the CC26xx Watchdog Timer
* Driver for the CC13xx/CC26xx Watchdog Timer
*
* This file is not called watchdog.c because the filename is in use by
* TI CC26xxware
* TI CC26xxware/CC13xxware
* @{
*
* \file
* Implementation of the cc26xx watchdog driver.
* Implementation of the CC13xx/CC26xx watchdog driver.
*/
#include "watchdog.h"
#include "ti-lib.h"
@ -75,14 +75,6 @@ watchdog_periodic(void)
ti_lib_watchdog_int_clear();
}
/*---------------------------------------------------------------------------*/
/**
* \brief Stub function to satisfy API requirements
*/
void
watchdog_stop(void)
{
}
/*---------------------------------------------------------------------------*/
/**
* \brief Manually trigger a WDT reboot
*/

10
cpu/cc26xx/dev/gpio-interrupt.c → cpu/cc26xx-cc13xx/dev/gpio-interrupt.c
View File

@ -28,6 +28,14 @@
* OF THE POSSIBILITY OF SUCH DAMAGE.
*/
/*---------------------------------------------------------------------------*/
/**
* \addtogroup cc26xx-gpio-interrupts
* @{
*
* \file
* Implementation of CC13xx/CC26xx GPIO interrupt handling.
*/
/*---------------------------------------------------------------------------*/
#include "ioc.h"
#include "gpio-interrupt.h"
#include "sys/energest.h"
@ -94,4 +102,4 @@ gpio_interrupt_isr(void)
ENERGEST_OFF(ENERGEST_TYPE_IRQ);
}
/*---------------------------------------------------------------------------*/
/** @} */

8
cpu/cc26xx/dev/gpio-interrupt.h → cpu/cc26xx-cc13xx/dev/gpio-interrupt.h
View File

@ -32,15 +32,15 @@
* \addtogroup cc26xx
* @{
*
* \defgroup cc26xx-gpio-interrupts CC26xx GPIO interrupt handling
* \defgroup cc26xx-gpio-interrupts CC13xx/CC26xx GPIO interrupt handling
*
* The CC26xx GPIO interrupt handler and an API which can be used by other
* parts of the code when they wish to be notified of a GPIO interrupt
* The CC13xx/CC26xx GPIO interrupt handler and an API which can be used by
* other parts of the code when they wish to be notified of a GPIO interrupt
*
* @{
*
* \file
* Header file for the CC26xx GPIO interrupt management
* Header file for the CC13xx/CC26xx GPIO interrupt management
*/
/*---------------------------------------------------------------------------*/
#ifndef GPIO_INTERRUPT_H_

5
cpu/cc26xx/dev/oscillators.c → cpu/cc26xx-cc13xx/dev/oscillators.c
View File

@ -166,7 +166,4 @@ oscillators_switch_to_hf_rc(void)
osc_interface_dis(smph_clk_state);
}
/*---------------------------------------------------------------------------*/
/**
* @}
* @}
*/
/** @} */

6
cpu/cc26xx/dev/oscillators.h → cpu/cc26xx-cc13xx/dev/oscillators.h
View File

@ -32,9 +32,9 @@
* \addtogroup cc26xx
* @{
*
* \defgroup cc26xx-oscillators CC26XX oscillator control
* \defgroup cc26xx-oscillators CC13xx/CC26xx oscillator control
*
* Wrapper around those CC26xxware OSC functions that we need in Contiki.
* Wrapper around CC26xxware/CC13xxware OSC functions that we need in Contiki.
*
* All CC26xxware OSC control requires access to the semaphore module within
* AUX. Thus, in addition to enabling the oscillator interface, we need to
@ -43,7 +43,7 @@
* @{
*
* \file
* Header file for the CC26XX oscillator control
* Header file for the CC13xx/CC26xx oscillator control
*/
/*---------------------------------------------------------------------------*/
#ifndef OSCILLATORS_H_

102
cpu/cc26xx/dev/cc26xx-rtc.c → cpu/cc26xx-cc13xx/dev/soc-rtc.c
View File

@ -27,15 +27,15 @@
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
* OF THE POSSIBILITY OF SUCH DAMAGE.
*/
/*---------------------------------------------------------------------------*/
/**
* \addtogroup cc26xx-rtc
* \addtogroup cc13xx-cc26xx-rtc
* @{
*
*/
/**
* \file
* Implementation of the CC26xx AON RTC driver
* Implementation of the CC13xx/CC26xx AON RTC driver
*/
/*---------------------------------------------------------------------------*/
#include "contiki.h"
#include "sys/energest.h"
#include "rtimer.h"
@ -46,16 +46,31 @@
#include <stdint.h>
#include <stdbool.h>
/*---------------------------------------------------------------------------*/
#define cc26xx_rtc_isr(...) AONRTCIntHandler(__VA_ARGS__)
#define soc_rtc_isr(...) AONRTCIntHandler(__VA_ARGS__)
/*---------------------------------------------------------------------------*/
/* Prototype of a function in clock.c. Called every time the handler fires */
void clock_update(void);
/*---------------------------------------------------------------------------*/
#define COMPARE_INCREMENT (RTIMER_SECOND / CLOCK_SECOND)
#define MULTIPLE_512_MASK 0xFFFFFE00
/*---------------------------------------------------------------------------*/
/*
* Used to test timer wraparounds.
*
* Set to 0xFFFFFFFA to test AON RTC second counter wraparound
* Set to 0xFFFA to test AON RTC 16.16 format wraparound
*/
#ifdef SOC_RTC_CONF_START_TICK_COUNT
#define SOC_RTC_START_TICK_COUNT SOC_RTC_CONF_START_TICK_COUNT
#else
#define SOC_RTC_START_TICK_COUNT 0
#endif
/*---------------------------------------------------------------------------*/
void
cc26xx_rtc_init(void)
soc_rtc_init(void)
{
uint32_t compare_value;
bool interrupts_disabled;
uint32_t next;
/* Disable and clear interrupts */
interrupts_disabled = ti_lib_int_master_disable();
@ -63,22 +78,22 @@ cc26xx_rtc_init(void)
ti_lib_aon_rtc_disable();
ti_lib_aon_rtc_event_clear(AON_RTC_CH0);
ti_lib_aon_rtc_event_clear(AON_RTC_CH2);
ti_lib_aon_rtc_event_clear(AON_RTC_CH1);
/* Setup the wakeup event */
ti_lib_aon_event_mcu_wake_up_set(AON_EVENT_MCU_WU0, AON_EVENT_RTC0);
ti_lib_aon_event_mcu_wake_up_set(AON_EVENT_MCU_WU1, AON_EVENT_RTC2);
ti_lib_aon_rtc_combined_event_config(AON_RTC_CH0 | AON_RTC_CH2);
ti_lib_aon_event_mcu_wake_up_set(AON_EVENT_MCU_WU0, AON_EVENT_RTC_CH0);
ti_lib_aon_event_mcu_wake_up_set(AON_EVENT_MCU_WU1, AON_EVENT_RTC_CH1);
ti_lib_aon_rtc_combined_event_config(AON_RTC_CH0 | AON_RTC_CH1);
/* Configure channel 2 in continuous compare, 128 ticks / sec */
ti_lib_aon_rtc_inc_value_ch2_set(RTIMER_SECOND / CLOCK_SECOND);
ti_lib_aon_rtc_mode_ch2_set(AON_RTC_MODE_CH2_CONTINUOUS);
compare_value = (RTIMER_SECOND / CLOCK_SECOND) +
ti_lib_aon_rtc_current_compare_value_get();
ti_lib_aon_rtc_compare_value_set(AON_RTC_CH2, compare_value);
HWREG(AON_RTC_BASE + AON_RTC_O_SEC) = SOC_RTC_START_TICK_COUNT;
/* Enable channel 2 and the RTC */
ti_lib_aon_rtc_channel_enable(AON_RTC_CH2);
next = ti_lib_aon_rtc_current_compare_value_get() + COMPARE_INCREMENT;
/* Configure channel 1 to start generating clock ticks. First tick at 512 */
ti_lib_aon_rtc_compare_value_set(AON_RTC_CH1, next);
/* Enable channel 1 and the RTC */
ti_lib_aon_rtc_channel_enable(AON_RTC_CH1);
ti_lib_aon_rtc_enable();
ti_lib_int_enable(INT_AON_RTC);
@ -90,41 +105,60 @@ cc26xx_rtc_init(void)
}
/*---------------------------------------------------------------------------*/
rtimer_clock_t
cc26xx_rtc_get_next_trigger()
soc_rtc_get_next_trigger()
{
rtimer_clock_t ch2 = ti_lib_aon_rtc_compare_value_get(AON_RTC_CH2);
rtimer_clock_t ch1 = ti_lib_aon_rtc_compare_value_get(AON_RTC_CH1);
if(HWREG(AON_RTC_BASE + AON_RTC_O_CHCTL) & AON_RTC_CHCTL_CH0_EN) {
rtimer_clock_t ch0 = ti_lib_aon_rtc_compare_value_get(AON_RTC_CH2);
rtimer_clock_t ch0 = ti_lib_aon_rtc_compare_value_get(AON_RTC_CH0);
return RTIMER_CLOCK_LT(ch0, ch2) ? ch0 : ch2;
return RTIMER_CLOCK_LT(ch0, ch1) ? ch0 : ch1;
}
return ch2;
return ch1;
}
/*---------------------------------------------------------------------------*/
void
cc26xx_rtc_schedule_one_shot(uint32_t ticks)
soc_rtc_schedule_one_shot(uint32_t channel, uint32_t ticks)
{
if((channel != AON_RTC_CH0) && (channel != AON_RTC_CH1)) {
return;
}
/* Set the channel to fire a one-shot compare event at time==ticks */
ti_lib_aon_rtc_compare_value_set(AON_RTC_CH0, ticks);
ti_lib_aon_rtc_channel_enable(AON_RTC_CH0);
ti_lib_aon_rtc_compare_value_set(channel, ticks);
ti_lib_aon_rtc_channel_enable(channel);
}
/*---------------------------------------------------------------------------*/
/* The AON RTC interrupt handler */
void
cc26xx_rtc_isr(void)
soc_rtc_isr(void)
{
uint32_t now, next;
ENERGEST_ON(ENERGEST_TYPE_IRQ);
if(ti_lib_aon_rtc_event_get(AON_RTC_CH0)) {
ti_lib_aon_rtc_event_clear(AON_RTC_CH0);
rtimer_run_next();
now = ti_lib_aon_rtc_current_compare_value_get();
/* Adjust the s/w tick counter irrespective of which event trigger this */
clock_update();
if(ti_lib_aon_rtc_event_get(AON_RTC_CH1)) {
HWREG(AON_RTC_BASE + AON_RTC_O_EVFLAGS) = AON_RTC_EVFLAGS_CH1;
/*
* We need to keep ticking while we are awake, so we schedule the next
* event on the next 512 tick boundary. If we drop to deep sleep before it
* happens, lpm_drop() will reschedule us in the 'distant' future
*/
next = (now + COMPARE_INCREMENT) & MULTIPLE_512_MASK;
ti_lib_aon_rtc_compare_value_set(AON_RTC_CH1, next);
}
if(ti_lib_aon_rtc_event_get(AON_RTC_CH2)) {
ti_lib_aon_rtc_event_clear(AON_RTC_CH2);
clock_update();
if(ti_lib_aon_rtc_event_get(AON_RTC_CH0)) {
ti_lib_aon_rtc_channel_disable(AON_RTC_CH0);
HWREG(AON_RTC_BASE + AON_RTC_O_EVFLAGS) = AON_RTC_EVFLAGS_CH0;
rtimer_run_next();
}
ENERGEST_OFF(ENERGEST_TYPE_IRQ);

44
cpu/cc26xx/dev/cc26xx-rtc.h → cpu/cc26xx-cc13xx/dev/soc-rtc.h
View File

@ -31,34 +31,28 @@
* \addtogroup cc26xx
* @{
*
* \defgroup cc26xx-clocks CC26xx clock and timer subsystem
* \defgroup cc26xx-clocks CC13xx/CC26xx clock and timer subsystem
*
* For the CC26xx cpu we use the AON RTC as the basis for all clocks and timers
* For the CC13xx/CC26xx cpu we use the AON RTC as the basis for all clocks and
* timers
*
* We configure the AON RTC's channel 2 to run in continuous mode, generating
* 128 interrupts / second. In continuous mode, the next compare event is
* scheduled by the hardware automatically; the events are equidistant and
* this also means we don't need the overhead of re-scheduling within the
* interrupt handler
*
* For rtimers, we use the RTC's channel 0 in one-shot compare mode. When the
* compare event fires, we call rtimer_run_next
* We use two of the aviable AON RTC channels. Channel 0 is used by the rtimer
* sub-system. Channel 1 is used by the system clock and the LPM module.
*
* The RTC runs in all power modes except 'shutdown'
*
* \sa cpu/cc26xx/clock.c cpu/cc26xx/rtimer-arch.c
* @{
*
* \defgroup cc26xx-rtc CC26xx AON RTC driver
* \defgroup cc13xx-cc26xx-rtc CC13xx/CC26xx AON RTC driver
*
* Underpins the platform's software clocks and timers
*
* @{
* \file
* Header file for the CC26XX AON RTC driver
* Header file for the CC13xx/CC26xx AON RTC driver
*/
#ifndef CC26XX_RTC_H_
#define CC26XX_RTC_H_
#ifndef SOC_RTC_H_
#define SOC_RTC_H_
/*---------------------------------------------------------------------------*/
#include "contiki.h"
@ -67,12 +61,13 @@
#include <stdint.h>
/*---------------------------------------------------------------------------*/
/**
* \brief Initialise the CC26XX AON RTC module
* \brief Initialise the CC13XX/CC26XX AON RTC module
*
* This timer configures AON RTC channels.
*
* This timer configures the AON RTC's channel 2 to run in continuous mode
* This function must be called before clock_init() and rtimer_init()
*/
void cc26xx_rtc_init(void);
void soc_rtc_init(void);
/**
* \brief Return the time of the next scheduled rtimer event
@ -81,17 +76,24 @@ void cc26xx_rtc_init(void);
* This function will check both AON RTC channels and will only take CH0's
* compare into account if the channel is actually enabled
*/
rtimer_clock_t cc26xx_rtc_get_next_trigger(void);
rtimer_clock_t soc_rtc_get_next_trigger(void);
/**
* \brief Schedule an AON RTC channel 0 one-shot compare event
* \param channel AON_RTC_CH0 or AON_RTC_CH1
* \param t The time when the event will be fired. This is an absolute
* time, in other words the event will fire AT time \e t,
* not IN \e t ticks
*
* Channel AON_RTC_CH0 is reserved for the rtimer. AON_RTC_CH1 is reserved
* for the system clock.
*
* User applications should not use this function. User applications should
* instead use Contiki's timer-related libraries
*/
void cc26xx_rtc_schedule_one_shot(uint32_t t);
void soc_rtc_schedule_one_shot(uint32_t channel, uint32_t t);
/*---------------------------------------------------------------------------*/
#endif /* CC26XX_RTC_H_ */
#endif /* SOC_RTC_H_ */
/*---------------------------------------------------------------------------*/
/**
* @}

0
cpu/cc26xx/dev/uart1.h → cpu/cc26xx-cc13xx/dev/uart1.h
View File

0
cpu/cc26xx/fault-handlers.c → cpu/cc26xx-cc13xx/fault-handlers.c
View File

2
cpu/cc26xx/ieee-addr.c → cpu/cc26xx-cc13xx/ieee-addr.c
View File

@ -34,7 +34,7 @@
* @{
*
* \file
* Driver for the CC26xx IEEE addresses
* Driver for the CC13xx/CC26xx IEEE addresses
*/
/*---------------------------------------------------------------------------*/
#include "contiki-conf.h"

2
cpu/cc26xx/ieee-addr.h → cpu/cc26xx-cc13xx/ieee-addr.h
View File

@ -33,7 +33,7 @@
* \addtogroup cc26xx
* @{
*
* \defgroup cc26xx-ieee-addr CC26xx IEEE Address Control
* \defgroup cc26xx-ieee-addr CC13xx/CC26xx IEEE Address Control
*
* Driver for the retrieval of an IEEE address from flash
*

1
cpu/cc26xx-cc13xx/lib/cc13xxware Submodule

@ -0,0 +1 @@
Subproject commit 63ed52888467ea7d403b0c743852162395232c9e

1
cpu/cc26xx-cc13xx/lib/cc26xxware Submodule

@ -0,0 +1 @@
Subproject commit 0e82b18bf2c69fb0a40af4d2496db2a3dc721cec

46
cpu/cc26xx/lpm.c → cpu/cc26xx-cc13xx/lpm.c
View File

@ -32,12 +32,12 @@
* \addtogroup cc26xx-lpm
* @{
*
* Implementation of CC26xx low-power operation functionality
* Implementation of CC13xx/CC26xx low-power operation functionality
*
* @{
*
* \file
* Driver for CC26xx's low-power operation
* Driver for CC13xx/CC26xx low-power operation
*/
/*---------------------------------------------------------------------------*/
#include "prcm.h"
@ -48,8 +48,11 @@
#include "lib/list.h"
#include "dev/leds.h"
#include "dev/watchdog.h"
#include "dev/cc26xx-rtc.h"
#include "dev/soc-rtc.h"
#include "dev/oscillators.h"
#include <stdint.h>
#include <string.h>
/*---------------------------------------------------------------------------*/
#if ENERGEST_CONF_ON
static unsigned long irq_energest = 0;
@ -72,7 +75,10 @@ LIST(modules_list);
* Don't consider standby mode if the next AON RTC event is scheduled to fire
* in less than STANDBY_MIN_DURATION rtimer ticks
*/
#define STANDBY_MIN_DURATION (RTIMER_SECOND >> 8)
#define STANDBY_MIN_DURATION (RTIMER_SECOND >> 11)
/*---------------------------------------------------------------------------*/
/* Prototype of a function in clock.c. Called every time we come out of DS */
void clock_update(void);
/*---------------------------------------------------------------------------*/
void
lpm_shutdown(uint32_t wakeup_pin, uint32_t io_pull, uint32_t wake_on)
@ -93,10 +99,10 @@ lpm_shutdown(uint32_t wakeup_pin, uint32_t io_pull, uint32_t wake_on)
/* Reset AON even fabric to default wakeup sources */
for(i = AON_EVENT_MCU_WU0; i <= AON_EVENT_MCU_WU3; i++) {
ti_lib_aon_event_mcu_wake_up_set(i, AON_EVENT_NULL);
ti_lib_aon_event_mcu_wake_up_set(i, AON_EVENT_NONE);
}
for(i = AON_EVENT_AUX_WU0; i <= AON_EVENT_AUX_WU2; i++) {
ti_lib_aon_event_aux_wake_up_set(i, AON_EVENT_NULL);
ti_lib_aon_event_aux_wake_up_set(i, AON_EVENT_NONE);
}
ti_lib_sys_ctrl_aon_sync();
@ -222,6 +228,14 @@ wake_up(void)
/* Check operating conditions, optimally choose DCDC versus GLDO */
ti_lib_sys_ctrl_dcdc_voltage_conditional_control();
/*
* We may or may not have been woken up by an AON RTC tick. If not, we need
* to adjust our software tick counter
*/
clock_update();
watchdog_periodic();
/* Notify all registered modules that we've just woken up */
for(module = list_head(modules_list); module != NULL;
module = module->next) {
@ -237,10 +251,11 @@ lpm_drop()
lpm_registered_module_t *module;
uint8_t max_pm = LPM_MODE_MAX_SUPPORTED;
uint8_t module_pm;
clock_time_t next_event;
uint32_t domains = LOCKABLE_DOMAINS;
if(RTIMER_CLOCK_LT(cc26xx_rtc_get_next_trigger(),
if(RTIMER_CLOCK_LT(soc_rtc_get_next_trigger(),
RTIMER_NOW() + STANDBY_MIN_DURATION)) {
lpm_sleep();
return;
@ -269,6 +284,18 @@ lpm_drop()
/* Critical. Don't get interrupted! */
ti_lib_int_master_disable();
/*
* Reschedule AON RTC CH1 to fire an event N ticks before the next etimer
* event
*/
next_event = etimer_next_expiration_time();
if(next_event) {
next_event = next_event - clock_time();
soc_rtc_schedule_one_shot(AON_RTC_CH1, RTIMER_NOW() +
(next_event * (RTIMER_SECOND / CLOCK_SECOND)));
}
/*
* Notify all registered modules that we are dropping to mode X. We do not
* need to do this for simple sleep.
@ -357,7 +384,7 @@ lpm_drop()
while(ti_lib_aon_wuc_power_status_get() & AONWUC_AUX_POWER_ON);
/* Configure the recharge controller */
ti_lib_sys_ctrl_set_recharge_before_power_down(false);
ti_lib_sys_ctrl_set_recharge_before_power_down(XOSC_IN_HIGH_POWER_MODE);
/*
* If both PERIPH and SERIAL PDs are off, request the uLDO as the power
@ -436,6 +463,9 @@ void
lpm_init()
{
list_init(modules_list);
/* Always wake up on any DIO edge detection */
ti_lib_aon_event_mcu_wake_up_set(AON_EVENT_MCU_WU2, AON_EVENT_IO);
}
/*---------------------------------------------------------------------------*/
void

6
cpu/cc26xx/lpm.h → cpu/cc26xx-cc13xx/lpm.h
View File

@ -32,14 +32,14 @@
* \addtogroup cc26xx
* @{
*
* \defgroup cc26xx-lpm CC26xx Low-Power management
* \defgroup cc26xx-lpm CC13xx/CC26xx Low-Power management
*
* CC26xx low-power operation
* CC13xx/CC26xx low-power operation
*
* @{
*
* \file
* Header file for the management of CC26xx low-power operation
* Header file for the management of CC13xx/CC26xx low-power operation
*/
/*---------------------------------------------------------------------------*/
#ifndef LPM_H_

0
cpu/cc26xx/mtarch.h → cpu/cc26xx-cc13xx/mtarch.h
View File

0
cpu/cc26xx/putchar.c → cpu/cc26xx-cc13xx/putchar.c
View File

2163
cpu/cc26xx/dev/rfc-api/ble_cmd.h → cpu/cc26xx-cc13xx/rf-core/api/ble_cmd.h
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File diff suppressed because it is too large Load Diff

188
cpu/cc26xx/dev/rfc-api/ble_mailbox.h → cpu/cc26xx-cc13xx/rf-core/api/ble_mailbox.h
View File

@ -1,119 +1,69 @@
/******************************************************************************
* Filename: ble_mailbox.h
* Revised: $ $
* Revision: $ $
*
* Description: Definitions for BLE interface
*
* Copyright (C) 2015 Texas Instruments Incorporated - http://www.ti.com/
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* Neither the name of Texas Instruments Incorporated nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************/
#ifndef _BLE_MAILBOX_H
#define _BLE_MAILBOX_H
#include "mailbox.h"
/// \name CPE interrupt definitions for BLE
/// Interrupt masks for the CPE interrupt in RDBELL. These are new names for interrupts in mailbox.h,
/// used for compartibility with previous versions with separate interrupt numbers.
///@{
#define IRQN_BLE_TX_DONE IRQN_TX_DONE
#define IRQN_BLE_TX_ACK IRQN_TX_ACK
#define IRQN_BLE_TX_CTRL IRQN_TX_CTRL
#define IRQN_BLE_TX_CTRL_ACK IRQN_TX_CTRL_ACK
#define IRQN_BLE_TX_CTRL_ACK_ACK IRQN_TX_CTRL_ACK_ACK
#define IRQN_BLE_TX_RETRANS IRQN_TX_RETRANS
#define IRQN_BLE_TX_ENTRY_DONE IRQN_TX_ENTRY_DONE
#define IRQN_BLE_TX_BUFFER_CHANGED IRQN_TX_BUFFER_CHANGED
#define IRQN_BLE_RX_OK IRQN_RX_OK
#define IRQN_BLE_RX_NOK IRQN_RX_NOK
#define IRQN_BLE_RX_IGNORED IRQN_RX_IGNORED
#define IRQN_BLE_RX_EMPTY IRQN_RX_EMPTY
#define IRQN_BLE_RX_CTRL IRQN_RX_CTRL
#define IRQN_BLE_RX_CTRL_ACK IRQN_RX_CTRL_ACK
#define IRQN_BLE_RX_BUF_FULL IRQN_RX_BUF_FULL
#define IRQN_BLE_RX_ENTRY_DONE IRQN_RX_ENTRY_DONE
#define IRQ_BLE_TX_DONE (1U << IRQN_BLE_TX_DONE)
#define IRQ_BLE_TX_ACK (1U << IRQN_BLE_TX_ACK)
#define IRQ_BLE_TX_CTRL (1U << IRQN_BLE_TX_CTRL)
#define IRQ_BLE_TX_CTRL_ACK (1U << IRQN_BLE_TX_CTRL_ACK)
#define IRQ_BLE_TX_CTRL_ACK_ACK (1U << IRQN_BLE_TX_CTRL_ACK_ACK)
#define IRQ_BLE_TX_RETRANS (1U << IRQN_BLE_TX_RETRANS)
#define IRQ_BLE_TX_ENTRY_DONE (1U << IRQN_BLE_TX_ENTRY_DONE)
#define IRQ_BLE_TX_BUFFER_CHANGED (1U << IRQN_BLE_TX_BUFFER_CHANGED)
#define IRQ_BLE_RX_OK (1U << IRQN_BLE_RX_OK)
#define IRQ_BLE_RX_NOK (1U << IRQN_BLE_RX_NOK)
#define IRQ_BLE_RX_IGNORED (1U << IRQN_BLE_RX_IGNORED)
#define IRQ_BLE_RX_EMPTY (1U << IRQN_BLE_RX_EMPTY)
#define IRQ_BLE_RX_CTRL (1U << IRQN_BLE_RX_CTRL)
#define IRQ_BLE_RX_CTRL_ACK (1U << IRQN_BLE_RX_CTRL_ACK)
#define IRQ_BLE_RX_BUF_FULL (1U << IRQN_BLE_RX_BUF_FULL)
#define IRQ_BLE_RX_ENTRY_DONE (1U << IRQN_BLE_RX_ENTRY_DONE)
///@}
/// \name Radio operation status
/// Radio operation status format:
/// Bits 15:12: Protocol
/// 0001: BLE
/// Bits 11:10: Type
/// 00: Not finished
/// 01: Done successfully
/// 10: Done with error
/// Bits 9:0: Identifier
/// \name Operation finished normally
///@{
#define BLE_DONE_OK 0x1400 ///< Operation ended normally
#define BLE_DONE_RXTIMEOUT 0x1401 ///< Timeout of first Rx of slave operation or end of scan window
#define BLE_DONE_NOSYNC 0x1402 ///< Timeout of subsequent Rx
#define BLE_DONE_RXERR 0x1403 ///< Operation ended because of receive error (CRC or other)
#define BLE_DONE_CONNECT 0x1404 ///< CONNECT_REQ received or transmitted
#define BLE_DONE_MAXNACK 0x1405 ///< Maximum number of retransmissions exceeded
#define BLE_DONE_ENDED 0x1406 ///< Operation stopped after end trigger
#define BLE_DONE_ABORT 0x1407 ///< Operation aborted by command
#define BLE_DONE_STOPPED 0x1408 ///< Operation stopped after stop command
///@}
/// \name Operation finished with error
///@{
#define BLE_ERROR_PAR 0x1800 ///< Illegal parameter
#define BLE_ERROR_RXBUF 0x1801 ///< No available Rx buffer (Advertiser, Scanner, Initiator)
#define BLE_ERROR_NO_SETUP 0x1802 ///< Operation using Rx or Tx attemted when not in BLE mode
#define BLE_ERROR_NO_FS 0x1803 ///< Operation using Rx or Tx attemted without frequency synth configured
#define BLE_ERROR_SYNTH_PROG 0x1804 ///< Synthesizer programming failed to complete on time
#define BLE_ERROR_RXOVF 0x1805 ///< Receiver overflowed during operation
#define BLE_ERROR_TXUNF 0x1806 ///< Transmitter underflowed during operation
///@}
///@}
#endif
/******************************************************************************
* Filename: ble_mailbox.h
* Revised: $ $
* Revision: $ $
*
* Description: Definitions for BLE interface
*
* Copyright (C) 2015 Texas Instruments Incorporated - http://www.ti.com/
*
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* Neither the name of Texas Instruments Incorporated nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************/
#ifndef BLE_MAILBOX_H_
#define BLE_MAILBOX_H_
/// \name Radio operation status
///@{
/// \name Operation finished normally
///@{
#define BLE_DONE_OK 0x1400 ///< Operation ended normally
#define BLE_DONE_RXTIMEOUT 0x1401 ///< Timeout of first Rx of slave operation or end of scan window
#define BLE_DONE_NOSYNC 0x1402 ///< Timeout of subsequent Rx
#define BLE_DONE_RXERR 0x1403 ///< Operation ended because of receive error (CRC or other)
#define BLE_DONE_CONNECT 0x1404 ///< CONNECT_REQ received or transmitted
#define BLE_DONE_MAXNACK 0x1405 ///< Maximum number of retransmissions exceeded
#define BLE_DONE_ENDED 0x1406 ///< Operation stopped after end trigger
#define BLE_DONE_ABORT 0x1407 ///< Operation aborted by command
#define BLE_DONE_STOPPED 0x1408 ///< Operation stopped after stop command
///@}
/// \name Operation finished with error
///@{
#define BLE_ERROR_PAR 0x1800 ///< Illegal parameter
#define BLE_ERROR_RXBUF 0x1801 ///< No available Rx buffer (Advertiser, Scanner, Initiator)
#define BLE_ERROR_NO_SETUP 0x1802 ///< Operation using Rx or Tx attemted when not in BLE mode
#define BLE_ERROR_NO_FS 0x1803 ///< Operation using Rx or Tx attemted without frequency synth configured
#define BLE_ERROR_SYNTH_PROG 0x1804 ///< Synthesizer programming failed to complete on time
#define BLE_ERROR_RXOVF 0x1805 ///< Receiver overflowed during operation
#define BLE_ERROR_TXUNF 0x1806 ///< Transmitter underflowed during operation
///@}
///@}
#endif /* BLE_MAILBOX_H_ */

2074
cpu/cc26xx/dev/rfc-api/common_cmd.h → cpu/cc26xx-cc13xx/rf-core/api/common_cmd.h
View File

File diff suppressed because it is too large Load Diff

213
cpu/cc26xx-cc13xx/rf-core/api/data_entry.h Normal file
View File

@ -0,0 +1,213 @@
/******************************************************************************
* Filename: data_entry.h
* Revised: 2015-08-04 11:44:20 +0200 (Tue, 04 Aug 2015)
* Revision: 44329
*
* Description: Definition of API for data exchange
*
* Copyright (c) 2015, Texas Instruments Incorporated
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1) Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2) Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3) Neither the name of the ORGANIZATION nor the names of its contributors may
* be used to endorse or promote products derived from this software without
* specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************/
#ifndef DATA_ENTRY_H_
#define DATA_ENTRY_H_
#ifndef __RFC_STRUCT
#ifdef __GNUC__
#define __RFC_STRUCT __attribute__ ((aligned (4)))
#else
#define __RFC_STRUCT
#endif
#endif
//! \addtogroup rfc
//! @{
//! \addtogroup data_entry
//! @{
#include <stdint.h>
#include "mailbox.h"
typedef struct __RFC_STRUCT rfc_dataEntry_s rfc_dataEntry_t;
typedef struct __RFC_STRUCT rfc_dataEntryGeneral_s rfc_dataEntryGeneral_t;
typedef struct __RFC_STRUCT rfc_dataEntryMulti_s rfc_dataEntryMulti_t;
typedef struct __RFC_STRUCT rfc_dataEntryPointer_s rfc_dataEntryPointer_t;
typedef struct __RFC_STRUCT rfc_dataEntryPartial_s rfc_dataEntryPartial_t;
//! \addtogroup dataEntry
//! @{
struct __RFC_STRUCT rfc_dataEntry_s {
uint8_t* pNextEntry; //!< Pointer to next entry in the queue, NULL if this is the last entry
uint8_t status; //!< Indicates status of entry, including whether it is free for the system CPU to write to
struct {
uint8_t type:2; //!< \brief Type of data entry structure<br>
//!< 0: General data entry <br>
//!< 1: Multi-element Rx entry<br>
//!< 2: Pointer entry<br>
//!< 3: Partial read Rx entry
uint8_t lenSz:2; //!< \brief Size of length word in start of each Rx entry element<br>
//!< 0: No length indicator<br>
//!< 1: One byte length indicator<br>
//!< 2: Two bytes length indicator<br>
//!< 3: <i>Reserved</i>
uint8_t irqIntv:4; //!< \brief For partial read Rx entry only: The number of bytes between interrupt generated
//!< by the radio CPU (0: 16 bytes)
} config;
uint16_t length; //!< \brief For pointer entries: Number of bytes in the data buffer pointed to<br>
//!< For other entries: Number of bytes following this length field
};
//! @}
//! \addtogroup dataEntryGeneral
//! @{
//! General data entry structure (type = 0)
struct __RFC_STRUCT rfc_dataEntryGeneral_s {
uint8_t* pNextEntry; //!< Pointer to next entry in the queue, NULL if this is the last entry
uint8_t status; //!< Indicates status of entry, including whether it is free for the system CPU to write to
struct {
uint8_t type:2; //!< \brief Type of data entry structure<br>
//!< 0: General data entry <br>
//!< 1: Multi-element Rx entry<br>
//!< 2: Pointer entry<br>
//!< 3: Partial read Rx entry
uint8_t lenSz:2; //!< \brief Size of length word in start of each Rx entry element<br>
//!< 0: No length indicator<br>
//!< 1: One byte length indicator<br>
//!< 2: Two bytes length indicator<br>
//!< 3: <i>Reserved</i>
uint8_t irqIntv:4; //!< \brief For partial read Rx entry only: The number of bytes between interrupt generated
//!< by the radio CPU (0: 16 bytes)
} config;
uint16_t length; //!< \brief For pointer entries: Number of bytes in the data buffer pointed to<br>
//!< For other entries: Number of bytes following this length field
uint8_t data; //!< First byte of the data array to be received or transmitted
};
//! @}
//! \addtogroup dataEntryMulti
//! @{
//! Multi-element data entry structure (type = 1)
struct __RFC_STRUCT rfc_dataEntryMulti_s {
uint8_t* pNextEntry; //!< Pointer to next entry in the queue, NULL if this is the last entry
uint8_t status; //!< Indicates status of entry, including whether it is free for the system CPU to write to
struct {
uint8_t type:2; //!< \brief Type of data entry structure<br>
//!< 0: General data entry <br>
//!< 1: Multi-element Rx entry<br>
//!< 2: Pointer entry<br>
//!< 3: Partial read Rx entry
uint8_t lenSz:2; //!< \brief Size of length word in start of each Rx entry element<br>
//!< 0: No length indicator<br>
//!< 1: One byte length indicator<br>
//!< 2: Two bytes length indicator<br>
//!< 3: <i>Reserved</i>
uint8_t irqIntv:4; //!< \brief For partial read Rx entry only: The number of bytes between interrupt generated
//!< by the radio CPU (0: 16 bytes)
} config;
uint16_t length; //!< \brief For pointer entries: Number of bytes in the data buffer pointed to<br>
//!< For other entries: Number of bytes following this length field
uint16_t numElements; //!< Number of entry elements committed in the entry
uint16_t nextIndex; //!< Index to the byte after the last byte of the last entry element committed by the radio CPU
uint8_t rxData; //!< First byte of the data array of received data entry elements
};
//! @}
//! \addtogroup dataEntryPointer
//! @{
//! Pointer data entry structure (type = 2)
struct __RFC_STRUCT rfc_dataEntryPointer_s {
uint8_t* pNextEntry; //!< Pointer to next entry in the queue, NULL if this is the last entry
uint8_t status; //!< Indicates status of entry, including whether it is free for the system CPU to write to
struct {
uint8_t type:2; //!< \brief Type of data entry structure<br>
//!< 0: General data entry <br>
//!< 1: Multi-element Rx entry<br>
//!< 2: Pointer entry<br>
//!< 3: Partial read Rx entry
uint8_t lenSz:2; //!< \brief Size of length word in start of each Rx entry element<br>
//!< 0: No length indicator<br>
//!< 1: One byte length indicator<br>
//!< 2: Two bytes length indicator<br>
//!< 3: <i>Reserved</i>
uint8_t irqIntv:4; //!< \brief For partial read Rx entry only: The number of bytes between interrupt generated
//!< by the radio CPU (0: 16 bytes)
} config;
uint16_t length; //!< \brief For pointer entries: Number of bytes in the data buffer pointed to<br>
//!< For other entries: Number of bytes following this length field
uint8_t* pData; //!< Pointer to data buffer of data to be received ro transmitted
};
//! @}
//! \addtogroup dataEntryPartial
//! @{
//! Partial read data entry structure (type = 3)
struct __RFC_STRUCT rfc_dataEntryPartial_s {
uint8_t* pNextEntry; //!< Pointer to next entry in the queue, NULL if this is the last entry
uint8_t status; //!< Indicates status of entry, including whether it is free for the system CPU to write to
struct {
uint8_t type:2; //!< \brief Type of data entry structure<br>
//!< 0: General data entry <br>
//!< 1: Multi-element Rx entry<br>
//!< 2: Pointer entry<br>
//!< 3: Partial read Rx entry
uint8_t lenSz:2; //!< \brief Size of length word in start of each Rx entry element<br>
//!< 0: No length indicator<br>
//!< 1: One byte length indicator<br>
//!< 2: Two bytes length indicator<br>
//!< 3: <i>Reserved</i>
uint8_t irqIntv:4; //!< \brief For partial read Rx entry only: The number of bytes between interrupt generated
//!< by the radio CPU (0: 16 bytes)
} config;
uint16_t length; //!< \brief For pointer entries: Number of bytes in the data buffer pointed to<br>
//!< For other entries: Number of bytes following this length field
struct {
uint16_t numElements:13; //!< Number of entry elements committed in the entry
uint16_t bEntryOpen:1; //!< 1 if the entry contains an element that is still open for appending data
uint16_t bFirstCont:1; //!< 1 if the first element is a continuation of the last packet from the previous entry
uint16_t bLastCont:1; //!< 1 if the packet in the last element continues in the next entry
} pktStatus;
uint16_t nextIndex; //!< Index to the byte after the last byte of the last entry element committed by the radio CPU
uint8_t rxData; //!< First byte of the data array of received data entry elements
};
//! @}
//! @}
//! @}
#endif /* DATA_ENTRY_H_ */

1225
cpu/cc26xx/dev/rfc-api/ieee_cmd.h → cpu/cc26xx-cc13xx/rf-core/api/ieee_cmd.h
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File diff suppressed because it is too large Load Diff

182
cpu/cc26xx/dev/rfc-api/ieee_mailbox.h → cpu/cc26xx-cc13xx/rf-core/api/ieee_mailbox.h
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@ -1,107 +1,75 @@
/******************************************************************************
* Filename: ieee_mailbox.h
* Revised: $ $
* Revision: $ $
*
* Description: Definitions for IEEE 802.15.4 interface
*
* Copyright (C) 2015 Texas Instruments Incorporated - http://www.ti.com/
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* Neither the name of Texas Instruments Incorporated nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************/
#ifndef _IEEE_MAILBOX_H
#define _IEEE_MAILBOX_H
#include "mailbox.h"
/// \name CPE interrupt definitions for IEEE 802.15.4
/// Interrupt masks for the CPE interrupt in RDBELL. These are new names for interrupts in mailbox.h,
/// used for compartibility with previous versions with separate interrupt numbers.
///@{
#define IRQN_IEEE_BG_COMMAND_SUSPENDED IRQN_BG_COMMAND_SUSPENDED
#define IRQN_IEEE_TX_FRAME IRQN_TX_DONE
#define IRQN_IEEE_TX_ACK IRQN_TX_ACK
#define IRQN_IEEE_RX_FRAME IRQN_RX_OK
#define IRQN_IEEE_RX_NOK IRQN_RX_NOK
#define IRQN_IEEE_RX_IGNORED IRQN_RX_IGNORED
#define IRQN_IEEE_RX_BUF_FULL IRQN_RX_BUF_FULL
#define IRQN_IEEE_RX_ENTRY_DONE IRQN_RX_ENTRY_DONE
#define IRQ_IEEE_BG_COMMAND_SUSPENDED (1U << IRQN_IEEE_BG_COMMAND_SUSPENDED)
#define IRQ_IEEE_TX_FRAME (1U << IRQN_IEEE_TX_FRAME)
#define IRQ_IEEE_TX_ACK (1U << IRQN_IEEE_TX_ACK)
#define IRQ_IEEE_RX_FRAME (1U << IRQN_IEEE_RX_FRAME)
#define IRQ_IEEE_RX_NOK (1U << IRQN_IEEE_RX_NOK)
#define IRQ_IEEE_RX_IGNORED (1U << IRQN_IEEE_RX_IGNORED)
#define IRQ_IEEE_RX_BUF_FULL (1U << IRQN_IEEE_RX_BUF_FULL)
#define IRQ_IEEE_RX_ENTRY_DONE (1U << IRQN_IEEE_RX_ENTRY_DONE)
///@}
/// \name Radio operation status
/// Radio operation status format:
/// Bits 15:12: Protocol
/// 0010: IEEE 802.15.4
/// Bits 11:10: Type
/// 00: Not finished
/// 01: Done successfully
/// 10: Done with error
/// Bits 9:0: Identifier
/// \name Operation not finished
///@{
#define IEEE_SUSPENDED 0x2001 ///< Operation suspended
///@}
/// \name Operation finished normally
///@{
#define IEEE_DONE_OK 0x2400 ///< Operation ended normally
#define IEEE_DONE_BUSY 0x2401 ///< CSMA-CA operation ended with failure
#define IEEE_DONE_STOPPED 0x2402 ///< Operation stopped after stop command
#define IEEE_DONE_ACK 0x2403 ///< ACK packet received with pending data bit cleared
#define IEEE_DONE_ACKPEND 0x2404 ///< ACK packet received with pending data bit set
#define IEEE_DONE_TIMEOUT 0x2405 ///< Operation ended due to timeout
#define IEEE_DONE_BGEND 0x2406 ///< FG operation ended because necessary background level
///< operation ended
#define IEEE_DONE_ABORT 0x2407 ///< Operation aborted by command
///@}
/// \name Operation finished with error
///@{
#define IEEE_ERROR_PAR 0x2800 ///< Illegal parameter
#define IEEE_ERROR_NO_SETUP 0x2801 ///< Operation using Rx or Tx attemted when not in 15.4 mode
#define IEEE_ERROR_NO_FS 0x2802 ///< Operation using Rx or Tx attemted without frequency synth configured
#define IEEE_ERROR_SYNTH_PROG 0x2803 ///< Synthesizer programming failed to complete on time
#define IEEE_ERROR_RXOVF 0x2804 ///< Receiver overflowed during operation
#define IEEE_ERROR_TXUNF 0x2805 ///< Transmitter underflowed during operation
///@}
///@}
#endif
/******************************************************************************
* Filename: ieee_mailbox.h
* Revised: $ $
* Revision: $ $
*
* Description: Definitions for IEEE 802.15.4 interface
*
* Copyright (C) 2015 Texas Instruments Incorporated - http://www.ti.com/
*
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* Neither the name of Texas Instruments Incorporated nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************/
#ifndef IEEE_MAILBOX_H_
#define IEEE_MAILBOX_H_
#include "mailbox.h"
/// \name Radio operation status
///@{
/// \name Operation not finished
///@{
#define IEEE_SUSPENDED 0x2001 ///< Operation suspended
///@}
/// \name Operation finished normally
///@{
#define IEEE_DONE_OK 0x2400 ///< Operation ended normally
#define IEEE_DONE_BUSY 0x2401 ///< CSMA-CA operation ended with failure
#define IEEE_DONE_STOPPED 0x2402 ///< Operation stopped after stop command
#define IEEE_DONE_ACK 0x2403 ///< ACK packet received with pending data bit cleared
#define IEEE_DONE_ACKPEND 0x2404 ///< ACK packet received with pending data bit set
#define IEEE_DONE_TIMEOUT 0x2405 ///< Operation ended due to timeout
#define IEEE_DONE_BGEND 0x2406 ///< FG operation ended because necessary background level
///< operation ended
#define IEEE_DONE_ABORT 0x2407 ///< Operation aborted by command
///@}
/// \name Operation finished with error
///@{
#define IEEE_ERROR_PAR 0x2800 ///< Illegal parameter
#define IEEE_ERROR_NO_SETUP 0x2801 ///< Operation using Rx or Tx attemted when not in 15.4 mode
#define IEEE_ERROR_NO_FS 0x2802 ///< Operation using Rx or Tx attemted without frequency synth configured
#define IEEE_ERROR_SYNTH_PROG 0x2803 ///< Synthesizer programming failed to complete on time
#define IEEE_ERROR_RXOVF 0x2804 ///< Receiver overflowed during operation
#define IEEE_ERROR_TXUNF 0x2805 ///< Transmitter underflowed during operation
///@}
///@}
#endif /* IEEE_MAILBOX_H_ */

908
cpu/cc26xx/dev/rfc-api/mailbox.h → cpu/cc26xx-cc13xx/rf-core/api/mailbox.h
View File

@ -1,580 +1,328 @@
/******************************************************************************
* Filename: mailbox.h
* Revised: $ $
* Revision: $ $
*
* Description: Definitions for interface between system and radio CPU
*
* Copyright (C) 2015 Texas Instruments Incorporated - http://www.ti.com/
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* Neither the name of Texas Instruments Incorporated nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************/
#ifndef _MAILBOX_H
#define _MAILBOX_H
#include <stdint.h>
#include <string.h>
/// Type definition for RAT
typedef uint32_t ratmr_t;
/// Type definition for a data queue
typedef struct {
uint8_t *pCurrEntry; ///< Pointer to the data queue entry to be used, NULL for an empty queue
uint8_t *pLastEntry; ///< Pointer to the last entry in the queue, NULL for a circular queue
} dataQueue_t;
/// \name CPE interrupt definitions
/// Interrupt masks for the CPE interrupt in RDBELL.
///@{
#define IRQN_COMMAND_DONE 0 ///< Radio operation command finished
#define IRQN_LAST_COMMAND_DONE 1 ///< Last radio operation command in a chain finished
#define IRQN_FG_COMMAND_DONE 2 ///< FG level Radio operation command finished
#define IRQN_LAST_FG_COMMAND_DONE 3 ///< Last FG level radio operation command in a chain finished
#define IRQN_TX_DONE 4 ///< Packet transmitted
#define IRQN_TX_ACK 5 ///< ACK packet transmitted
#define IRQN_TX_CTRL 6 ///< Control packet transmitted
#define IRQN_TX_CTRL_ACK 7 ///< Acknowledgement received on a transmitted control packet
#define IRQN_TX_CTRL_ACK_ACK 8 ///< Acknowledgement received on a transmitted control packet, and acknowledgement transmitted for that packet
#define IRQN_TX_RETRANS 9 ///< Packet retransmitted
#define IRQN_TX_ENTRY_DONE 10 ///< Tx queue data entry state changed to Finished
#define IRQN_TX_BUFFER_CHANGED 11 ///< A buffer change is complete
#define IRQN_BG_COMMAND_SUSPENDED 12 ///< A background level radio operation command has been suspended
#define IRQN_RX_OK 16 ///< Packet received with CRC OK, payload, and not to be ignored
#define IRQN_RX_NOK 17 ///< Packet received with CRC error
#define IRQN_RX_IGNORED 18 ///< Packet received with CRC OK, but to be ignored
#define IRQN_RX_EMPTY 19 ///< Packet received with CRC OK, not to be ignored, no payload
#define IRQN_RX_CTRL 20 ///< Control packet received with CRC OK, not to be ignored
#define IRQN_RX_CTRL_ACK 21 ///< Control packet received with CRC OK, not to be ignored, then ACK sent
#define IRQN_RX_BUF_FULL 22 ///< Packet received that did not fit in the Rx queue
#define IRQN_RX_ENTRY_DONE 23 ///< Rx queue data entry changing state to Finished
#define IRQN_RX_DATA_WRITTEN 24 ///< Data written to partial read Rx buffer
#define IRQN_RX_N_DATA_WRITTEN 25 ///< Specified number of bytes written to partial read Rx buffer
#define IRQN_RX_ABORTED 26 ///< Packet reception stopped before packet was done
#define IRQN_SYNTH_NO_LOCK 28 ///< The synth has gone out of lock after calibration
#define IRQN_MODULES_UNLOCKED 29 ///< As part of the boot process, the CM0 has opened access to RF core modules and memories
#define IRQN_BOOT_DONE 30 ///< The RF core CPU boot is finished
#define IRQN_INTERNAL_ERROR 31 ///< Internal error observed
#define IRQ_COMMAND_DONE (1U << IRQN_COMMAND_DONE)
#define IRQ_LAST_COMMAND_DONE (1U << IRQN_LAST_COMMAND_DONE)
#define IRQ_FG_COMMAND_DONE (1U << IRQN_FG_COMMAND_DONE)
#define IRQ_LAST_FG_COMMAND_DONE (1U << IRQN_LAST_FG_COMMAND_DONE)
#define IRQ_TX_DONE (1U << IRQN_TX_DONE)
#define IRQ_TX_ACK (1U << IRQN_TX_ACK)
#define IRQ_TX_CTRL (1U << IRQN_TX_CTRL)
#define IRQ_TX_CTRL_ACK (1U << IRQN_TX_CTRL_ACK)
#define IRQ_TX_CTRL_ACK_ACK (1U << IRQN_TX_CTRL_ACK_ACK)
#define IRQ_TX_RETRANS (1U << IRQN_TX_RETRANS)
#define IRQ_TX_ENTRY_DONE (1U << IRQN_TX_ENTRY_DONE)
#define IRQ_TX_BUFFER_CHANGED (1U << IRQN_TX_BUFFER_CHANGED)
#define IRQ_BG_COMMAND_SUSPENDED (1U << IRQN_BG_COMMAND_SUSPENDED)
#define IRQ_RX_OK (1U << IRQN_RX_OK)
#define IRQ_RX_NOK (1U << IRQN_RX_NOK)
#define IRQ_RX_IGNORED (1U << IRQN_RX_IGNORED)
#define IRQ_RX_EMPTY (1U << IRQN_RX_EMPTY)
#define IRQ_RX_CTRL (1U << IRQN_RX_CTRL)
#define IRQ_RX_CTRL_ACK (1U << IRQN_RX_CTRL_ACK)
#define IRQ_RX_BUF_FULL (1U << IRQN_RX_BUF_FULL)
#define IRQ_RX_ENTRY_DONE (1U << IRQN_RX_ENTRY_DONE)
#define IRQ_RX_DATA_WRITTEN (1U << IRQN_RX_DATA_WRITTEN)
#define IRQ_RX_N_DATA_WRITTEN (1U << IRQN_RX_N_DATA_WRITTEN)
#define IRQ_RX_ABORTED (1U << IRQN_RX_ABORTED)
#define IRQ_SYNTH_NO_LOCK (1U << IRQN_SYNTH_NO_LOCK)
#define IRQ_MODULES_UNLOCKED (1U << IRQN_MODULES_UNLOCKED)
#define IRQ_BOOT_DONE (1U << IRQN_BOOT_DONE)
#define IRQ_INTERNAL_ERROR (1U << IRQN_INTERNAL_ERROR)
///@}
/// \name CMDSTA values
/// Values returned in result byte of CMDSTA
///@{
#define CMDSTA_Pending 0x00 ///< The command has not yet been parsed
#define CMDSTA_Done 0x01 ///< Command successfully parsed
#define CMDSTA_IllegalPointer 0x81 ///< The pointer signaled in CMDR is not valid
#define CMDSTA_UnknownCommand 0x82 ///< The command number in the command structure is unknown
#define CMDSTA_UnknownDirCommand 0x83 ///< The command number for a direct command is unknown, or the
///< command is not a direct command
#define CMDSTA_ContextError 0x85 ///< An immediate or direct command was issued in a context
///< where it is not supported
#define CMDSTA_SchedulingError 0x86 ///< A radio operation command was attempted to be scheduled
///< while another operation was already running in the RF core
#define CMDSTA_ParError 0x87 ///< There were errors in the command parameters that are parsed
///< on submission.
#define CMDSTA_QueueError 0x88 ///< An operation on a data entry queue was attempted that was
///< not supported by the queue in its current state
#define CMDSTA_QueueBusy 0x89 ///< An operation on a data entry was attempted while that entry
///< was busy
///@}
/// \name Macros for use with command definition files
/// The script create_command.pl generates header files from command and structure definitions in the
/// *_def.txt files. These are the macros to access the definitions
///@{
/// Get a field from a structure
//
/// Gets a field from a structure defined in a _def.txt file. This may be used both in assignments and
/// references (e.g. GET_FIELD(pCmd1, CMD_TEST, testParam) = GET_FIELD(pCmd2, CMD_DUMMY, dummyParam);)
/// \param[in] ptr
/// Pointer to the structure
/// \param[in] cmd
/// Name of the command or structure as defined in the _def.txt file
/// \param[in] field
/// Name of the accessed field as defined in the _def.txt file
///
#define GET_FIELD(ptr, cmd, field) \
(*((_TYPE_##cmd##_##field *) (((uint8_t *)(ptr)) + (_POSITION_##cmd##_##field))))
/// Get a field from a structure, reading as volatile
//
/// Gets a field from a structure defined in a _def.txt file, reading it as a volatile parameter, which
/// takes into account that it may be changed by the other side. This may be used both in assignments and
/// references (e.g. GET_FIELD(pCmd1, CMD_TEST, testParam) = GET_FIELD(pCmd2, CMD_DUMMY, dummyParam);)
/// \param[in] ptr
/// Pointer to the structure
/// \param[in] cmd
/// Name of the command or structure as defined in the _def.txt file
/// \param[in] field
/// Name of the accessed field as defined in the _def.txt file
///
#define GET_FIELD_V(ptr, cmd, field) \
(*((volatile _TYPE_##cmd##_##field *) (((uint8_t *)(ptr)) + (_POSITION_##cmd##_##field))))
/// Get the pointer to a field from a structure
//
/// Gets the pointer to a field from a structure defined in a _def.txt file.
/// \param[in] ptr
/// Pointer to the structure
/// \param[in] cmd
/// Name of the command or structure as defined in the _def.txt file
/// \param[in] field
/// Name of the accessed field as defined in the _def.txt file
///
#define GET_FIELD_PTR(ptr, cmd, field) \
((_TYPE_##cmd##_##field *) (((uint8_t *)(ptr)) + (_POSITION_##cmd##_##field)))
/// Get the volatile pointer to a field from a structure
//
/// Gets the volatile pointer to a field from a structure defined in a _def.txt file.
/// \param[in] ptr
/// Pointer to the structure
/// \param[in] cmd
/// Name of the command or structure as defined in the _def.txt file
/// \param[in] field
/// Name of the accessed field as defined in the _def.txt file
///
#define GET_FIELD_VPTR(ptr, cmd, field) \
((volatile _TYPE_##cmd##_##field *) (((uint8_t *)(ptr)) + (_POSITION_##cmd##_##field)))
/// Get bits from a bit field
//
/// Returns bits from a bit field defined in a _def.txt file.
/// \param[in] value
/// The value of the entire field that contains the bit field
/// \param[in] cmd
/// Name of the command or structure as defined in the _def.txt file
/// \param[in] field
/// Name of the field that contains the bit field definition as defined in the _def.txt file
/// \param[in] bitfield
/// Name of the bitfield as defined in the _def.txt file
///
#define GET_BITS(value, cmd, field, bitfield) \
(((value) >> (_BITPOS_##cmd##_##field##_##bitfield)) & \
((1U << (_NBITS_##cmd##_##field##_##bitfield)) - 1))
/// Get bits from a bit field as a signed value
//
/// Returns sign extended bits from a bit field defined in a _def.txt file.
/// \param[in] value
/// The value of the entire field that contains the bit field
/// \param[in] cmd
/// Name of the command or structure as defined in the _def.txt file
/// \param[in] field
/// Name of the field that contains the bit field definition as defined in the _def.txt file
/// \param[in] bitfield
/// Name of the bitfield as defined in the _def.txt file
///
#define GET_BITS_S(value, cmd, field, bitfield) \
(((int)(value) << (32 - ((_BITPOS_##cmd##_##field##_##bitfield) + (_NBITS_##cmd##_##field##_##bitfield)))) >> \
(32 - (_NBITS_##cmd##_##field##_##bitfield)))
/// Set bits in a bit field
//
/// Modifies a bit field defined in a _def.txt file.
/// \param[in,out] value
/// The value of the entire field that contains the bit field
/// \param[in] cmd
/// Name of the command or structure as defined in the _def.txt file
/// \param[in] field
/// Name of the field that contains the bit field definition as defined in the _def.txt file
/// \param[in] bitfield
/// Name of the bitfield as defined in the _def.txt file
/// \param[in] bvalue
/// The value to set in the bitfield
///
#define SET_BITS(value, cmd, field, bitfield, bvalue) \
(((value) = ((value) & \
(~(((1U << (_NBITS_##cmd##_##field##_##bitfield)) - 1) << (_BITPOS_##cmd##_##field##_##bitfield))) | \
((bvalue) << (_BITPOS_##cmd##_##field##_##bitfield)))))
/// Get bits from a bit field in a structure
//
/// Returns bits from a bit field in a structure defined in a _def.txt file.
/// \param[in] ptr
/// Pointer to the structure
/// \param[in] cmd
/// Name of the command or structure as defined in the _def.txt file
/// \param[in] field
/// Name of the field that contains the bit field definition as defined in the _def.txt file
/// \param[in] bitfield
/// Name of the bitfield as defined in the _def.txt file
///
#define GET_BITFIELD(ptr, cmd, field, bitfield) \
((*((_TYPE_##cmd##_##field *) ((((uint8_t *)(ptr)) + (_POSITION_##cmd##_##field)))) >> \
((_BITPOS_##cmd##_##field##_##bitfield))) & \
((1U << (_NBITS_##cmd##_##field##_##bitfield)) - 1))
/// Get bits from a bit field in a structure, reading as volatile
//
/// Returns bits from a bit field in a structure defined in a _def.txt file, reading it as a
/// volatile parameter.
/// \param[in] ptr
/// Pointer to the structure
/// \param[in] cmd
/// Name of the command or structure as defined in the _def.txt file
/// \param[in] field
/// Name of the field that contains the bit field definition as defined in the _def.txt file
/// \param[in] bitfield
/// Name of the bitfield as defined in the _def.txt file
///
#define GET_BITFIELD_V(ptr, cmd, field, bitfield) \
((*((volatile _TYPE_##cmd##_##field *) ((((uint8_t *)(ptr)) + (_POSITION_##cmd##_##field)))) >> \
((_BITPOS_##cmd##_##field##_##bitfield))) & \
((1U << (_NBITS_##cmd##_##field##_##bitfield)) - 1))
/// Set bits in a bit field in a structure
//
/// Modifies a bit field in a field in a structure defined in a _def.txt file.
/// \param[in] ptr
/// Pointer to the structure
/// \param[in] cmd
/// Name of the command or structure as defined in the _def.txt file
/// \param[in] field
/// Name of the field that contains the bit field definition as defined in the _def.txt file
/// \param[in] bitfield
/// Name of the bitfield as defined in the _def.txt file
/// \param[in] value
/// The value to set in the bitfield
///
#define SET_BITFIELD(ptr, cmd, field, bitfield, value) \
((*((_TYPE_##cmd##_##field *) (((uint8_t *)(ptr)) + (_POSITION_##cmd##_##field)))) = \
((*((_TYPE_##cmd##_##field *) (((uint8_t *)(ptr)) + (_POSITION_##cmd##_##field)))) & \
(~(((1U << (_NBITS_##cmd##_##field##_##bitfield)) - 1) << (_BITPOS_##cmd##_##field##_##bitfield))) | \
(((uint32_t)(value)) << (_BITPOS_##cmd##_##field##_##bitfield))))
/// Set bits in a bit field in a structure, reading and writing as volatile
//
/// Modifies a bit field in a field in a structure defined in a _def.txt file, accessing it as a volatile
/// parameter.
/// \param[in] ptr
/// Pointer to the structure
/// \param[in] cmd
/// Name of the command or structure as defined in the _def.txt file
/// \param[in] field
/// Name of the field that contains the bit field definition as defined in the _def.txt file
/// \param[in] bitfield
/// Name of the bitfield as defined in the _def.txt file
/// \param[in] value
/// The value to set in the bitfield
///
#define SET_BITFIELD_V(ptr, cmd, field, bitfield, value) \
((*((volatile _TYPE_##cmd##_##field *) (((uint8_t *)(ptr)) + (_POSITION_##cmd##_##field)))) = \
((*((volatile _TYPE_##cmd##_##field *) (((uint8_t *)(ptr)) + (_POSITION_##cmd##_##field)))) & \
(~(((1U << (_NBITS_##cmd##_##field##_##bitfield)) - 1) << (_BITPOS_##cmd##_##field##_##bitfield))) | \
(((uint32_t)(value)) << (_BITPOS_##cmd##_##field##_##bitfield))))
/// Get the value of specific bifield in a field with the remaining bits set to 0
//
/// Returns a bitfield so that the value of the full field can be obtained by bitwise
/// OR between these
/// \param[in] cmd
/// Name of the command or structure as defined in the _def.txt file
/// \param[in] field
/// Name of the field that contains the bit field definition as defined in the _def.txt file
/// \param[in] bitfield
/// Name of the bitfield as defined in the _def.txt file
/// \param[in] value
/// The value to use in the bitfield
///
#define BITVALUE(cmd, field, bitfield, value) \
((((uint32_t)(value)) & ((1U << (_NBITS_##cmd##_##field##_##bitfield)) - 1)) << \
(_BITPOS_##cmd##_##field##_##bitfield))
/// Get the size of a structure
//
/// Gets the size of a structure defined in a _def.txt file.
///
/// \param[in] cmd
/// Name of the command or structure as defined in the _def.txt file
///
#define SIZEOF_STRUCT(cmd) \
(_SIZEOF_##cmd)
/// Get the size of a radio operation command structure
//
/// Gets the size of a radio operation command structure defined in a _def.txt file. The difference from
/// SIZEOF_STRUCT is for legacy reasons only.
///
/// \param[in] cmd
/// Name of the command or structure as defined in the _def.txt file
///
#define SIZEOF_RADIO_OP(cmd) \
(_SIZEOF_##cmd)
/// Initializes a structure to an initialization set
//
/// Sets the value of a structure to its given initialization values
/// \param[in] ptr
/// Pointer to the structure, must be word aligned
/// \param[in] cmd
/// Name of the command or structure as defined in the _def.txt file
/// \param[in] set
/// Index of the set of initializations to use
///
#define INIT_STRUCT(ptr, cmd, set) \
(memcpy(((uint32_t *)(ptr)) + (_START_INIT_WIDX_##cmd), (__init_##cmd[(set)]), \
(_N_INIT_WORDS_##cmd) * sizeof(uint32_t)))
///@}
/// \name Macros for sending direct commands
///@{
/// Direct command with no parameter
#define CMDR_DIR_CMD(cmdId) (((cmdId) << 16) | 1)
/// Direct command with 1-byte parameter
#define CMDR_DIR_CMD_1BYTE(cmdId, par) (((cmdId) << 16) | ((par) << 8) | 1)
/// Direct command with 2-byte parameter
#define CMDR_DIR_CMD_2BYTE(cmdId, par) (((cmdId) << 16) | ((par) & 0xFFFC) | 1)
///@}
/// \name Definitions for trigger types
///@{
#define TRIG_NOW 0 ///< Triggers immediately
#define TRIG_NEVER 1 ///< Never trigs
#define TRIG_ABSTIME 2 ///< Trigs at an absolute time
#define TRIG_REL_SUBMIT 3 ///< Trigs at a time relative to the command was submitted
#define TRIG_REL_START 4 ///< Trigs at a time relative to the command started
#define TRIG_REL_PREVSTART 5 ///< Trigs at a time relative to the previous command in the chain started
#define TRIG_REL_FIRSTSTART 6 ///< Trigs at a time relative to the first command in the chain started
#define TRIG_REL_PREVEND 7 ///< Trigs at a time relative to the previous command in the chain ended
#define TRIG_REL_EVT1 8 ///< Trigs at a time relative to the context defined "Event 1"
#define TRIG_REL_EVT2 9 ///< Trigs at a time relative to the context defined "Event 2"
#define TRIG_EXTERNAL 10 ///< Trigs at an external event to the radio timer
#define TRIG_PAST_BM 0x80 ///< Bitmask for setting pastTrig bit in order to trig immediately if
///< trigger happened in the past
///@}
/// \name Definitions for conditional execution
///@{
#define COND_ALWAYS 0 ///< Always run next command (except in case of Abort)
#define COND_NEVER 1 ///< Never run next command
#define COND_STOP_ON_FALSE 2 ///< Run next command if this command returned True, stop if it returned
///< False
#define COND_STOP_ON_TRUE 3 ///< Stop if this command returned True, run next command if it returned
///< False
#define COND_SKIP_ON_FALSE 4 ///< Run next command if this command returned True, skip a number of
///< commands if it returned False
#define COND_SKIP_ON_TRUE 5 ///< Skip a number of commands if this command returned True, run next
///< command if it returned False
///@}
/// \name Radio operation status
/// Radio operation status format:
///@{
/// \name Operation not finished
///@{
#define IDLE 0x0000 ///< Operation not started
#define PENDING 0x0001 ///< Start of command is pending
#define ACTIVE 0x0002 ///< Running
#define SKIPPED 0x0003 ///< Operation skipped due to condition in another command
///@}
/// \name Operation finished normally
///@{
#define DONE_OK 0x0400 ///< Operation ended normally
#define DONE_COUNTDOWN 0x0401 ///< Counter reached zero
#define DONE_RXERR 0x0402 ///< Operation ended with CRC error
#define DONE_TIMEOUT 0x0403 ///< Operation ended with timeout
#define DONE_STOPPED 0x0404 ///< Operation stopped after CMD_STOP command
#define DONE_ABORT 0x0405 ///< Operation aborted by CMD_ABORT command
#define DONE_FAILED 0x0406 ///< Scheduled immediate command failed
///@}
/// \name Operation finished with error
///@{
#define ERROR_PAST_START 0x0800 ///< The start trigger occurred in the past
#define ERROR_START_TRIG 0x0801 ///< Illegal start trigger parameter
#define ERROR_CONDITION 0x0802 ///< Illegal condition for next operation
#define ERROR_PAR 0x0803 ///< Error in a command specific parameter
#define ERROR_POINTER 0x0804 ///< Invalid pointer to next operation
#define ERROR_CMDID 0x0805 ///< Next operation has a command ID that is undefined or not a radio
///< operation command
#define ERROR_WRONG_BG 0x0806 ///< FG level command not compatible with running BG level command
#define ERROR_NO_SETUP 0x0807 ///< Operation using Rx or Tx attemted without CMD_RADIO_SETUP
#define ERROR_NO_FS 0x0808 ///< Operation using Rx or Tx attemted without frequency synth configured
#define ERROR_SYNTH_PROG 0x0809 ///< Synthesizer calibration failed
#define ERROR_TXUNF 0x080A ///< Tx underflow observed
#define ERROR_RXOVF 0x080B ///< Rx overflow observed
#define ERROR_NO_RX 0x080C ///< Attempted to access data from Rx when no such data was yet received
#define ERROR_PENDING 0x080D ///< Command submitted in the future with another command at different level pending
///@}
///@}
/// \name Data entry types
///@{
#define DATA_ENTRY_TYPE_GEN 0 ///< General type: Tx entry or single element Rx entry
#define DATA_ENTRY_TYPE_MULTI 1 ///< Multi-element Rx entry type
#define DATA_ENTRY_TYPE_PTR 2 ///< Pointer entry type
#define DATA_ENTRY_TYPE_PARTIAL 3 ///< Partial read entry type
///@
/// \name Data entry statuses
///@{
#define DATA_ENTRY_PENDING 0 ///< Entry not yet used
#define DATA_ENTRY_ACTIVE 1 ///< Entry in use by radio CPU
#define DATA_ENTRY_BUSY 2 ///< Entry being updated
#define DATA_ENTRY_FINISHED 3 ///< Radio CPU is finished accessing the entry
#define DATA_ENTRY_UNFINISHED 4 ///< Radio CPU is finished accessing the entry, but packet could not be finished
///@}
/// Difference between length and size of rxData field in multi-element Rx entry
#define DATA_ENTRY_MULTI_LEN_OFFSET (_POSITION_dataEntry_rxData - _POSITION_dataEntry_data)
/// \name Macros for RF register override
///@{
/// Macro for ADI half-size value-mask combination
#define ADI_VAL_MASK(addr, mask, value) \
(((addr) & 1) ? (((mask) & 0x0F) | (((value) & 0x0F) << 4)) : \
((((mask) & 0x0F) << 4) | ((value) & 0x0F)))
/// 32-bit write of 16-bit value
#define HW_REG_OVERRIDE(addr, val) ((((uintptr_t) (addr)) & 0xFFFC) | ((uint32_t)(val) << 16))
/// ADI register, full-size write
#define ADI_REG_OVERRIDE(adiNo, addr, val) (2 | ((uint32_t)(val) << 16) | \
(((addr) & 0x3F) << 24) | (((adiNo) ? 1U : 0) << 31))
/// 2 ADI registers, full-size write
#define ADI_2REG_OVERRIDE(adiNo, addr, val, addr2, val2) \
(2 | ((uint32_t)(val2) << 2) | (((addr2) & 0x3F) << 10) | ((uint32_t)(val) << 16) | \
(((addr) & 0x3F) << 24) | (((adiNo) ? 1U : 0) << 31))
/// ADI register, half-size read-modify-write
#define ADI_HALFREG_OVERRIDE(adiNo, addr, mask, val) (2 | (ADI_VAL_MASK(addr, mask, val) << 16) | \
(((addr) & 0x3F) << 24) | (1U << 30) | (((adiNo) ? 1U : 0) << 31))
/// 2 ADI registers, half-size read-modify-write
#define ADI_2HALFREG_OVERRIDE(adiNo, addr, mask, val, addr2, mask2, val2) \
(2 | (ADI_VAL_MASK(addr2, mask2, val2) << 2) | (((addr2) & 0x3F) << 10) | \
(ADI_VAL_MASK(addr, mask, val) << 16) | (((addr) & 0x3F) << 24) | (1U << 30) | (((adiNo) ? 1U : 0) << 31))
/// 16-bit SW register as defined in radio_par_def.txt
#define SW_REG_OVERRIDE(cmd, field, val) (3 | ((_POSITION_##cmd##_##field) << 4) | ((uint32_t)(val) << 16))
/// SW register as defined in radio_par_def.txt with added index (for use with registers > 16 bits).
#define SW_REG_IND_OVERRIDE(cmd, field, offset, val) (3 | \
(((_POSITION_##cmd##_##field) + ((offset) << 1)) << 4) | ((uint32_t)(val) << 16))
/// 8-bit SW register as defined in radio_par_def.txt
#define SW_REG_BYTE_OVERRIDE(cmd, field, val) (0x8003 | ((_POSITION_##cmd##_##field) << 4) | \
((uint32_t)(val) << 16))
/// Two 8-bit SW registers as defined in radio_par_def.txt; the one given by field and the next byte.
#define SW_REG_2BYTE_OVERRIDE(cmd, field, val0, val1) (3 | (((_POSITION_##cmd##_##field) & 0xFFFE) << 4) | \
(((uint32_t)(val0) << 16) & 0x00FF0000) | ((uint32_t)(val1) << 24))
#define HW16_ARRAY_OVERRIDE(addr, length) (1 | (((uintptr_t) (addr)) & 0xFFFC) | ((uint32_t)(length) << 16))
#define HW32_ARRAY_OVERRIDE(addr, length) (1 | (((uintptr_t) (addr)) & 0xFFFC) | \
((uint32_t)(length) << 16) | (1U << 30))
#define ADI_ARRAY_OVERRIDE(adiNo, addr, bHalfSize, length) (1 | ((((addr) & 0x3F) << 2)) | \
((!!(bHalfSize)) << 8) | ((!!(adiNo)) << 9) | ((uint32_t)(length) << 16) | (2U << 30))
#define SW_ARRAY_OVERRIDE(cmd, firstfield, length) (1 | (((_POSITION_##cmd##_##firstfield)) << 2) | \
((uint32_t)(length) << 16) | (3U << 30))
#define MCE_RFE_OVERRIDE(bMceRam, mceRomBank, mceMode, bRfeRam, rfeRomBank, rfeMode) \
(7 | ((!!(bMceRam)) << 8) | (((mceRomBank) & 0x07) << 9) | ((!!(bRfeRam)) << 12) | (((rfeRomBank) & 0x07) << 13) | \
(((mceMode) & 0x00FF) << 16) | (((rfeMode) & 0x00FF) << 24))
#define BAW_OVERRIDE(freqOffset) (0x000B | ((freqOffset) << 16))
#define NEW_OVERRIDE_SEGMENT(address) (((((uintptr_t)(address)) & 0x03FFFFFC) << 6) | 0x000F | \
(((((uintptr_t)(address) >> 24) == 0x20) ? 0x01 : \
(((uintptr_t)(address) >> 24) == 0x21) ? 0x02 : \
(((uintptr_t)(address) >> 24) == 0xA0) ? 0x03 : \
(((uintptr_t)(address) >> 24) == 0x00) ? 0x04 : \
(((uintptr_t)(address) >> 24) == 0x10) ? 0x05 : \
(((uintptr_t)(address) >> 24) == 0x11) ? 0x06 : \
(((uintptr_t)(address) >> 24) == 0x40) ? 0x07 : \
(((uintptr_t)(address) >> 24) == 0x50) ? 0x08 : \
0x09) << 4)) // Use illegal value for illegal address range
/// End of string for override register
#define END_OVERRIDE 0xFFFFFFFF
#define FWPAR_8BIT_ADDR(cmd, field) (0x1800 | (_POSITION_##cmd##_##field))
#define FWPAR_16BIT_ADDR(cmd, field) (0x1000 | (_POSITION_##cmd##_##field))
#define FWPAR_32BIT_ADDR(cmd, field) (0x0000 | (_POSITION_##cmd##_##field))
/// ADI address-value pair
#define ADI_ADDR_VAL(addr, value) ((((addr) & 0x7F) << 8) | ((value) & 0xFF))
#define ADI_ADDR_VAL_MASK(addr, mask, value) ((((addr) & 0x7F) << 8) | ADI_VAL_MASK(addr, mask, value))
/// Low half-word
#define LOWORD(value) ((value) & 0xFFFF)
/// High half-word
#define HIWORD(value) ((value) >> 16)
///@}
#endif
/******************************************************************************
* Filename: mailbox.h
* Revised: 2015-06-29 12:59:58 +0200 (Mon, 29 Jun 2015)
* Revision: 44063
*
* Description: Definitions for interface between system and radio CPU
*
* Copyright (c) 2015, Texas Instruments Incorporated
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1) Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2) Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3) Neither the name of the ORGANIZATION nor the names of its contributors may
* be used to endorse or promote products derived from this software without
* specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************/
#ifndef MAILBOX_H_
#define MAILBOX_H_
#include <stdint.h>
#include <string.h>
/// Type definition for RAT
typedef uint32_t ratmr_t;
/// Type definition for a data queue
typedef struct {
uint8_t *pCurrEntry; ///< Pointer to the data queue entry to be used, NULL for an empty queue
uint8_t *pLastEntry; ///< Pointer to the last entry in the queue, NULL for a circular queue
} dataQueue_t;
/// \name CPE interrupt definitions
/// Interrupt masks for the CPE interrupt in RDBELL.
///@{
#define IRQN_COMMAND_DONE 0 ///< Radio operation command finished
#define IRQN_LAST_COMMAND_DONE 1 ///< Last radio operation command in a chain finished
#define IRQN_FG_COMMAND_DONE 2 ///< FG level Radio operation command finished
#define IRQN_LAST_FG_COMMAND_DONE 3 ///< Last FG level radio operation command in a chain finished
#define IRQN_TX_DONE 4 ///< Packet transmitted
#define IRQN_TX_ACK 5 ///< ACK packet transmitted
#define IRQN_TX_CTRL 6 ///< Control packet transmitted
#define IRQN_TX_CTRL_ACK 7 ///< Acknowledgement received on a transmitted control packet
#define IRQN_TX_CTRL_ACK_ACK 8 ///< Acknowledgement received on a transmitted control packet, and acknowledgement transmitted for that packet
#define IRQN_TX_RETRANS 9 ///< Packet retransmitted
#define IRQN_TX_ENTRY_DONE 10 ///< Tx queue data entry state changed to Finished
#define IRQN_TX_BUFFER_CHANGED 11 ///< A buffer change is complete
#define IRQN_RX_OK 16 ///< Packet received with CRC OK, payload, and not to be ignored
#define IRQN_RX_NOK 17 ///< Packet received with CRC error
#define IRQN_RX_IGNORED 18 ///< Packet received with CRC OK, but to be ignored
#define IRQN_RX_EMPTY 19 ///< Packet received with CRC OK, not to be ignored, no payload
#define IRQN_RX_CTRL 20 ///< Control packet received with CRC OK, not to be ignored
#define IRQN_RX_CTRL_ACK 21 ///< Control packet received with CRC OK, not to be ignored, then ACK sent
#define IRQN_RX_BUF_FULL 22 ///< Packet received that did not fit in the Rx queue
#define IRQN_RX_ENTRY_DONE 23 ///< Rx queue data entry changing state to Finished
#define IRQN_RX_DATA_WRITTEN 24 ///< Data written to partial read Rx buffer
#define IRQN_RX_N_DATA_WRITTEN 25 ///< Specified number of bytes written to partial read Rx buffer
#define IRQN_RX_ABORTED 26 ///< Packet reception stopped before packet was done
#define IRQN_RX_COLLISION_DETECTED 27 ///< A collision was indicated during packet reception
#define IRQN_SYNTH_NO_LOCK 28 ///< The synth has gone out of lock after calibration
#define IRQN_MODULES_UNLOCKED 29 ///< As part of the boot process, the CM0 has opened access to RF core modules and memories
#define IRQN_BOOT_DONE 30 ///< The RF core CPU boot is finished
#define IRQN_INTERNAL_ERROR 31 ///< Internal error observed
#define IRQ_COMMAND_DONE (1U << IRQN_COMMAND_DONE)
#define IRQ_LAST_COMMAND_DONE (1U << IRQN_LAST_COMMAND_DONE)
#define IRQ_FG_COMMAND_DONE (1U << IRQN_FG_COMMAND_DONE)
#define IRQ_LAST_FG_COMMAND_DONE (1U << IRQN_LAST_FG_COMMAND_DONE)
#define IRQ_TX_DONE (1U << IRQN_TX_DONE)
#define IRQ_TX_ACK (1U << IRQN_TX_ACK)
#define IRQ_TX_CTRL (1U << IRQN_TX_CTRL)
#define IRQ_TX_CTRL_ACK (1U << IRQN_TX_CTRL_ACK)
#define IRQ_TX_CTRL_ACK_ACK (1U << IRQN_TX_CTRL_ACK_ACK)
#define IRQ_TX_RETRANS (1U << IRQN_TX_RETRANS)
#define IRQ_TX_ENTRY_DONE (1U << IRQN_TX_ENTRY_DONE)
#define IRQ_TX_BUFFER_CHANGED (1U << IRQN_TX_BUFFER_CHANGED)
#define IRQ_RX_OK (1U << IRQN_RX_OK)
#define IRQ_RX_NOK (1U << IRQN_RX_NOK)
#define IRQ_RX_IGNORED (1U << IRQN_RX_IGNORED)
#define IRQ_RX_EMPTY (1U << IRQN_RX_EMPTY)
#define IRQ_RX_CTRL (1U << IRQN_RX_CTRL)
#define IRQ_RX_CTRL_ACK (1U << IRQN_RX_CTRL_ACK)
#define IRQ_RX_BUF_FULL (1U << IRQN_RX_BUF_FULL)
#define IRQ_RX_ENTRY_DONE (1U << IRQN_RX_ENTRY_DONE)
#define IRQ_RX_DATA_WRITTEN (1U << IRQN_RX_DATA_WRITTEN)
#define IRQ_RX_N_DATA_WRITTEN (1U << IRQN_RX_N_DATA_WRITTEN)
#define IRQ_RX_ABORTED (1U << IRQN_RX_ABORTED)
#define IRQ_RX_COLLISION_DETECTED (1U << IRQN_RX_COLLISION_DETECTED)
#define IRQ_SYNTH_NO_LOCK (1U << IRQN_SYNTH_NO_LOCK)
#define IRQ_MODULES_UNLOCKED (1U << IRQN_MODULES_UNLOCKED)
#define IRQ_BOOT_DONE (1U << IRQN_BOOT_DONE)
#define IRQ_INTERNAL_ERROR (1U << IRQN_INTERNAL_ERROR)
///@}
/// \name CMDSTA values
/// Values returned in result byte of CMDSTA
///@{
#define CMDSTA_Pending 0x00 ///< The command has not yet been parsed
#define CMDSTA_Done 0x01 ///< Command successfully parsed
#define CMDSTA_IllegalPointer 0x81 ///< The pointer signalled in CMDR is not valid
#define CMDSTA_UnknownCommand 0x82 ///< The command number in the command structure is unknown
#define CMDSTA_UnknownDirCommand 0x83 ///< The command number for a direct command is unknown, or the
///< command is not a direct command
#define CMDSTA_ContextError 0x85 ///< An immediate or direct command was issued in a context
///< where it is not supported
#define CMDSTA_SchedulingError 0x86 ///< A radio operation command was attempted to be scheduled
///< while another operation was already running in the RF core
#define CMDSTA_ParError 0x87 ///< There were errors in the command parameters that are parsed
///< on submission.
#define CMDSTA_QueueError 0x88 ///< An operation on a data entry queue was attempted that was
///< not supported by the queue in its current state
#define CMDSTA_QueueBusy 0x89 ///< An operation on a data entry was attempted while that entry
///< was busy
///@}
/// \name Macros for sending direct commands
///@{
/// Direct command with no parameter
#define CMDR_DIR_CMD(cmdId) (((cmdId) << 16) | 1)
/// Direct command with 1-byte parameter
#define CMDR_DIR_CMD_1BYTE(cmdId, par) (((cmdId) << 16) | ((par) << 8) | 1)
/// Direct command with 2-byte parameter
#define CMDR_DIR_CMD_2BYTE(cmdId, par) (((cmdId) << 16) | ((par) & 0xFFFC) | 1)
///@}
/// \name Definitions for trigger types
///@{
#define TRIG_NOW 0 ///< Triggers immediately
#define TRIG_NEVER 1 ///< Never trigs
#define TRIG_ABSTIME 2 ///< Trigs at an absolute time
#define TRIG_REL_SUBMIT 3 ///< Trigs at a time relative to the command was submitted
#define TRIG_REL_START 4 ///< Trigs at a time relative to the command started
#define TRIG_REL_PREVSTART 5 ///< Trigs at a time relative to the previous command in the chain started
#define TRIG_REL_FIRSTSTART 6 ///< Trigs at a time relative to the first command in the chain started
#define TRIG_REL_PREVEND 7 ///< Trigs at a time relative to the previous command in the chain ended
#define TRIG_REL_EVT1 8 ///< Trigs at a time relative to the context defined "Event 1"
#define TRIG_REL_EVT2 9 ///< Trigs at a time relative to the context defined "Event 2"
#define TRIG_EXTERNAL 10 ///< Trigs at an external event to the radio timer
#define TRIG_PAST_BM 0x80 ///< Bitmask for setting pastTrig bit in order to trig immediately if
///< trigger happened in the past
///@}
/// \name Definitions for conditional execution
///@{
#define COND_ALWAYS 0 ///< Always run next command (except in case of Abort)
#define COND_NEVER 1 ///< Never run next command
#define COND_STOP_ON_FALSE 2 ///< Run next command if this command returned True, stop if it returned
///< False
#define COND_STOP_ON_TRUE 3 ///< Stop if this command returned True, run next command if it returned
///< False
#define COND_SKIP_ON_FALSE 4 ///< Run next command if this command returned True, skip a number of
///< commands if it returned False
#define COND_SKIP_ON_TRUE 5 ///< Skip a number of commands if this command returned True, run next
///< command if it returned False
///@}
/// \name Radio operation status
///@{
/// \name Operation not finished
///@{
#define IDLE 0x0000 ///< Operation not started
#define PENDING 0x0001 ///< Start of command is pending
#define ACTIVE 0x0002 ///< Running
#define SKIPPED 0x0003 ///< Operation skipped due to condition in another command
///@}
/// \name Operation finished normally
///@{
#define DONE_OK 0x0400 ///< Operation ended normally
#define DONE_COUNTDOWN 0x0401 ///< Counter reached zero
#define DONE_RXERR 0x0402 ///< Operation ended with CRC error
#define DONE_TIMEOUT 0x0403 ///< Operation ended with timeout
#define DONE_STOPPED 0x0404 ///< Operation stopped after CMD_STOP command
#define DONE_ABORT 0x0405 ///< Operation aborted by CMD_ABORT command
#define DONE_FAILED 0x0406 ///< Scheduled immediate command failed
///@}
/// \name Operation finished with error
///@{
#define ERROR_PAST_START 0x0800 ///< The start trigger occurred in the past
#define ERROR_START_TRIG 0x0801 ///< Illegal start trigger parameter
#define ERROR_CONDITION 0x0802 ///< Illegal condition for next operation
#define ERROR_PAR 0x0803 ///< Error in a command specific parameter
#define ERROR_POINTER 0x0804 ///< Invalid pointer to next operation
#define ERROR_CMDID 0x0805 ///< Next operation has a command ID that is undefined or not a radio
///< operation command
#define ERROR_WRONG_BG 0x0806 ///< FG level command not compatible with running BG level command
#define ERROR_NO_SETUP 0x0807 ///< Operation using Rx or Tx attempted without CMD_RADIO_SETUP
#define ERROR_NO_FS 0x0808 ///< Operation using Rx or Tx attempted without frequency synth configured
#define ERROR_SYNTH_PROG 0x0809 ///< Synthesizer calibration failed
#define ERROR_TXUNF 0x080A ///< Tx underflow observed
#define ERROR_RXOVF 0x080B ///< Rx overflow observed
#define ERROR_NO_RX 0x080C ///< Attempted to access data from Rx when no such data was yet received
#define ERROR_PENDING 0x080D ///< Command submitted in the future with another command at different level pending
///@}
///@}
/// \name Data entry types
///@{
#define DATA_ENTRY_TYPE_GEN 0 ///< General type: Tx entry or single element Rx entry
#define DATA_ENTRY_TYPE_MULTI 1 ///< Multi-element Rx entry type
#define DATA_ENTRY_TYPE_PTR 2 ///< Pointer entry type
#define DATA_ENTRY_TYPE_PARTIAL 3 ///< Partial read entry type
///@
/// \name Data entry statuses
///@{
#define DATA_ENTRY_PENDING 0 ///< Entry not yet used
#define DATA_ENTRY_ACTIVE 1 ///< Entry in use by radio CPU
#define DATA_ENTRY_BUSY 2 ///< Entry being updated
#define DATA_ENTRY_FINISHED 3 ///< Radio CPU is finished accessing the entry
#define DATA_ENTRY_UNFINISHED 4 ///< Radio CPU is finished accessing the entry, but packet could not be finished
///@}
/// \name Macros for RF register override
///@{
/// Macro for ADI half-size value-mask combination
#define ADI_VAL_MASK(addr, mask, value) \
(((addr) & 1) ? (((mask) & 0x0F) | (((value) & 0x0F) << 4)) : \
((((mask) & 0x0F) << 4) | ((value) & 0x0F)))
/// 32-bit write of 16-bit value
#define HW_REG_OVERRIDE(addr, val) ((((uintptr_t) (addr)) & 0xFFFC) | ((uint32_t)(val) << 16))
/// ADI register, full-size write
#define ADI_REG_OVERRIDE(adiNo, addr, val) (2 | ((uint32_t)(val) << 16) | \
(((addr) & 0x3F) << 24) | (((adiNo) ? 1U : 0) << 31))
/// 2 ADI registers, full-size write
#define ADI_2REG_OVERRIDE(adiNo, addr, val, addr2, val2) \
(2 | ((uint32_t)(val2) << 2) | (((addr2) & 0x3F) << 10) | ((uint32_t)(val) << 16) | \
(((addr) & 0x3F) << 24) | (((adiNo) ? 1U : 0) << 31))
/// ADI register, half-size read-modify-write
#define ADI_HALFREG_OVERRIDE(adiNo, addr, mask, val) (2 | (ADI_VAL_MASK(addr, mask, val) << 16) | \
(((addr) & 0x3F) << 24) | (1U << 30) | (((adiNo) ? 1U : 0) << 31))
/// 2 ADI registers, half-size read-modify-write
#define ADI_2HALFREG_OVERRIDE(adiNo, addr, mask, val, addr2, mask2, val2) \
(2 | (ADI_VAL_MASK(addr2, mask2, val2) << 2) | (((addr2) & 0x3F) << 10) | \
(ADI_VAL_MASK(addr, mask, val) << 16) | (((addr) & 0x3F) << 24) | (1U << 30) | (((adiNo) ? 1U : 0) << 31))
/// 16-bit SW register as defined in radio_par_def.txt
#define SW_REG_OVERRIDE(cmd, field, val) (3 | ((_POSITION_##cmd##_##field) << 4) | ((uint32_t)(val) << 16))
/// SW register as defined in radio_par_def.txt with added index (for use with registers > 16 bits).
#define SW_REG_IND_OVERRIDE(cmd, field, offset, val) (3 | \
(((_POSITION_##cmd##_##field) + ((offset) << 1)) << 4) | ((uint32_t)(val) << 16))
/// 8-bit SW register as defined in radio_par_def.txt
#define SW_REG_BYTE_OVERRIDE(cmd, field, val) (0x8003 | ((_POSITION_##cmd##_##field) << 4) | \
((uint32_t)(val) << 16))
/// Two 8-bit SW registers as defined in radio_par_def.txt; the one given by field and the next byte.
#define SW_REG_2BYTE_OVERRIDE(cmd, field, val0, val1) (3 | (((_POSITION_##cmd##_##field) & 0xFFFE) << 4) | \
(((uint32_t)(val0) << 16) & 0x00FF0000) | ((uint32_t)(val1) << 24))
#define HW16_ARRAY_OVERRIDE(addr, length) (1 | (((uintptr_t) (addr)) & 0xFFFC) | ((uint32_t)(length) << 16))
#define HW32_ARRAY_OVERRIDE(addr, length) (1 | (((uintptr_t) (addr)) & 0xFFFC) | \
((uint32_t)(length) << 16) | (1U << 30))
#define ADI_ARRAY_OVERRIDE(adiNo, addr, bHalfSize, length) (1 | ((((addr) & 0x3F) << 2)) | \
((!!(bHalfSize)) << 8) | ((!!(adiNo)) << 9) | ((uint32_t)(length) << 16) | (2U << 30))
#define SW_ARRAY_OVERRIDE(cmd, firstfield, length) (1 | (((_POSITION_##cmd##_##firstfield)) << 2) | \
((uint32_t)(length) << 16) | (3U << 30))
#define MCE_RFE_OVERRIDE(bMceRam, mceRomBank, mceMode, bRfeRam, rfeRomBank, rfeMode) \
(7 | ((!!(bMceRam)) << 8) | (((mceRomBank) & 0x07) << 9) | ((!!(bRfeRam)) << 12) | (((rfeRomBank) & 0x07) << 13) | \
(((mceMode) & 0x00FF) << 16) | (((rfeMode) & 0x00FF) << 24))
#define NEW_OVERRIDE_SEGMENT(address) (((((uintptr_t)(address)) & 0x03FFFFFC) << 6) | 0x000F | \
(((((uintptr_t)(address) >> 24) == 0x20) ? 0x01 : \
(((uintptr_t)(address) >> 24) == 0x21) ? 0x02 : \
(((uintptr_t)(address) >> 24) == 0xA0) ? 0x03 : \
(((uintptr_t)(address) >> 24) == 0x00) ? 0x04 : \
(((uintptr_t)(address) >> 24) == 0x10) ? 0x05 : \
(((uintptr_t)(address) >> 24) == 0x11) ? 0x06 : \
(((uintptr_t)(address) >> 24) == 0x40) ? 0x07 : \
(((uintptr_t)(address) >> 24) == 0x50) ? 0x08 : \
0x09) << 4)) // Use illegal value for illegal address range
/// End of string for override register
#define END_OVERRIDE 0xFFFFFFFF
/// ADI address-value pair
#define ADI_ADDR_VAL(addr, value) ((((addr) & 0x7F) << 8) | ((value) & 0xFF))
#define ADI_ADDR_VAL_MASK(addr, mask, value) ((((addr) & 0x7F) << 8) | ADI_VAL_MASK(addr, mask, value))
/// Low half-word
#define LOWORD(value) ((value) & 0xFFFF)
/// High half-word
#define HIWORD(value) ((value) >> 16)
///@}
#endif /* MAILBOX_H_ */

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cpu/cc26xx-cc13xx/rf-core/api/prop_cmd.h Normal file
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/******************************************************************************
* Filename: prop_cmd.h
* Revised: 2015-08-04 10:40:45 +0200 (Tue, 04 Aug 2015)
* Revision: 44326
*
* Description: CC13xx API for Proprietary mode commands
*
* Copyright (c) 2015, Texas Instruments Incorporated
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1) Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2) Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3) Neither the name of the ORGANIZATION nor the names of its contributors may
* be used to endorse or promote products derived from this software without
* specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************/
#ifndef PROP_CMD_H_
#define PROP_CMD_H_
#ifndef __RFC_STRUCT
#ifdef __GNUC__
#define __RFC_STRUCT __attribute__ ((aligned (4)))
#else
#define __RFC_STRUCT
#endif
#endif
//! \addtogroup rfc
//! @{
//! \addtogroup prop_cmd
//! @{
#include <stdint.h>
#include "mailbox.h"
#include "common_cmd.h"
typedef struct __RFC_STRUCT rfc_carrierSense_s rfc_carrierSense_t;
typedef struct __RFC_STRUCT rfc_CMD_PROP_TX_s rfc_CMD_PROP_TX_t;
typedef struct __RFC_STRUCT rfc_CMD_PROP_RX_s rfc_CMD_PROP_RX_t;
typedef struct __RFC_STRUCT rfc_CMD_PROP_TX_ADV_s rfc_CMD_PROP_TX_ADV_t;
typedef struct __RFC_STRUCT rfc_CMD_PROP_RX_ADV_s rfc_CMD_PROP_RX_ADV_t;
typedef struct __RFC_STRUCT rfc_CMD_PROP_RADIO_SETUP_s rfc_CMD_PROP_RADIO_SETUP_t;
typedef struct __RFC_STRUCT rfc_CMD_PROP_RADIO_DIV_SETUP_s rfc_CMD_PROP_RADIO_DIV_SETUP_t;
typedef struct __RFC_STRUCT rfc_CMD_PROP_SET_LEN_s rfc_CMD_PROP_SET_LEN_t;
typedef struct __RFC_STRUCT rfc_CMD_PROP_RESTART_RX_s rfc_CMD_PROP_RESTART_RX_t;
typedef struct __RFC_STRUCT rfc_propRxOutput_s rfc_propRxOutput_t;
typedef struct __RFC_STRUCT rfc_propRxStatus_s rfc_propRxStatus_t;
//! \addtogroup carrierSense
//! @{
struct __RFC_STRUCT rfc_carrierSense_s {
struct {
uint8_t bEnaRssi:1; //!< If 1, enable RSSI as a criterion
uint8_t bEnaCorr:1; //!< If 1, enable correlation as a criterion
uint8_t operation:1; //!< \brief 0: Busy if either RSSI or correlation indicates Busy<br>
//!< 1: Busy if both RSSI and correlation indicates Busy
uint8_t busyOp:1; //!< \brief 0: Continue carrier sense on channel Busy<br>
//!< 1: End carrier sense on channel Busy<br>
//!< For an Rx command, the receiver will continue when carrier sense ends, but it will then not end if channel goes Idle
uint8_t idleOp:1; //!< \brief 0: Continue on channel Idle<br>
//!< 1: End on channel Idle
uint8_t timeoutRes:1; //!< \brief 0: Timeout with channel state Invalid treated as Busy<br>
//!< 1: Timeout with channel state Invalid treated as Idle
} csConf;
int8_t rssiThr; //!< RSSI threshold
uint8_t numRssiIdle; //!< \brief Number of consecutive RSSI measurements below the threshold needed before the channel is
//!< declared Idle
uint8_t numRssiBusy; //!< \brief Number of consecutive RSSI measurements above the threshold needed before the channel is
//!< declared Busy
uint16_t corrPeriod; //!< Number of RAT ticks for a correlation observation periods
struct {
uint8_t numCorrInv:4; //!< \brief Number of subsequent correlation tops with maximum <code>corrPeriod</code> RAT
//!< ticks between them needed to go from Idle to Invalid
uint8_t numCorrBusy:4; //!< \brief Number of subsequent correlation tops with maximum <code>corrPeriod</code> RAT
//!< ticks between them needed to go from Invalid to Busy
} corrConfig;
struct {
uint8_t triggerType:4; //!< The type of trigger
uint8_t bEnaCmd:1; //!< \brief 0: No alternative trigger command<br>
//!< 1: CMD_TRIGGER can be used as an alternative trigger
uint8_t triggerNo:2; //!< The trigger number of the CMD_TRIGGER command that triggers this action
uint8_t pastTrig:1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error<br>
//!< 1: A trigger in the past is triggered as soon as possible
} csEndTrigger; //!< Trigger classifier for ending the carrier sense
ratmr_t csEndTime; //!< Time used together with <code>csEndTrigger</code> for ending the operation
};
//! @}
//! \addtogroup CMD_PROP_TX
//! @{
#define CMD_PROP_TX 0x3801
struct __RFC_STRUCT rfc_CMD_PROP_TX_s {
uint16_t commandNo; //!< The command ID number 0x3801
uint16_t status; //!< \brief An integer telling the status of the command. This value is
//!< updated by the radio CPU during operation and may be read by the
//!< system CPU at any time.
rfc_radioOp_t *pNextOp; //!< Pointer to the next operation to run after this operation is done
ratmr_t startTime; //!< Absolute or relative start time (depending on the value of <code>startTrigger</code>)
struct {
uint8_t triggerType:4; //!< The type of trigger
uint8_t bEnaCmd:1; //!< \brief 0: No alternative trigger command<br>
//!< 1: CMD_TRIGGER can be used as an alternative trigger
uint8_t triggerNo:2; //!< The trigger number of the CMD_TRIGGER command that triggers this action
uint8_t pastTrig:1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error<br>
//!< 1: A trigger in the past is triggered as soon as possible
} startTrigger; //!< Identification of the trigger that starts the operation
struct {
uint8_t rule:4; //!< Condition for running next command: Rule for how to proceed
uint8_t nSkip:4; //!< Number of skips if the rule involves skipping
} condition;
struct {
uint8_t bFsOff:1; //!< \brief 0: Keep frequency synth on after command<br>
//!< 1: Turn frequency synth off after command
uint8_t :2;
uint8_t bUseCrc:1; //!< \brief 0: Do not append CRC<br>
//!< 1: Append CRC
uint8_t bVarLen:1; //!< \brief 0: Fixed length<br>
//!< 1: Transmit length as first byte
} pktConf;
uint8_t pktLen; //!< Packet length
uint32_t syncWord; //!< Sync word to transmit
uint8_t* pPkt; //!< Pointer to packet
};
//! @}
//! \addtogroup CMD_PROP_RX
//! @{
#define CMD_PROP_RX 0x3802
struct __RFC_STRUCT rfc_CMD_PROP_RX_s {
uint16_t commandNo; //!< The command ID number 0x3802
uint16_t status; //!< \brief An integer telling the status of the command. This value is
//!< updated by the radio CPU during operation and may be read by the
//!< system CPU at any time.
rfc_radioOp_t *pNextOp; //!< Pointer to the next operation to run after this operation is done
ratmr_t startTime; //!< Absolute or relative start time (depending on the value of <code>startTrigger</code>)
struct {
uint8_t triggerType:4; //!< The type of trigger
uint8_t bEnaCmd:1; //!< \brief 0: No alternative trigger command<br>
//!< 1: CMD_TRIGGER can be used as an alternative trigger
uint8_t triggerNo:2; //!< The trigger number of the CMD_TRIGGER command that triggers this action
uint8_t pastTrig:1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error<br>
//!< 1: A trigger in the past is triggered as soon as possible
} startTrigger; //!< Identification of the trigger that starts the operation
struct {
uint8_t rule:4; //!< Condition for running next command: Rule for how to proceed
uint8_t nSkip:4; //!< Number of skips if the rule involves skipping
} condition;
struct {
uint8_t bFsOff:1; //!< \brief 0: Keep frequency synth on after command<br>
//!< 1: Turn frequency synth off after command
uint8_t bRepeatOk:1; //!< \brief 0: End operation after receiving a packet correctly<br>
//!< 1: Go back to sync search after receiving a packet correctly
uint8_t bRepeatNok:1; //!< \brief 0: End operation after receiving a packet with CRC error<br>
//!< 1: Go back to sync search after receiving a packet with CRC error
uint8_t bUseCrc:1; //!< \brief 0: Do not check CRC<br>
//!< 1: Check CRC
uint8_t bVarLen:1; //!< \brief 0: Fixed length<br>
//!< 1: Receive length as first byte
uint8_t bChkAddress:1; //!< \brief 0: No address check<br>
//!< 1: Check address
uint8_t endType:1; //!< \brief 0: Packet is received to the end if end trigger happens after sync is obtained<br>
//!< 1: Packet reception is stopped if end trigger happens
uint8_t filterOp:1; //!< \brief 0: Stop receiver and restart sync search on address mismatch<br>
//!< 1: Receive packet and mark it as ignored on address mismatch
} pktConf;
struct {
uint8_t bAutoFlushIgnored:1; //!< If 1, automatically discard ignored packets from Rx queue
uint8_t bAutoFlushCrcErr:1; //!< If 1, automatically discard packets with CRC error from Rx queue
uint8_t :1;
uint8_t bIncludeHdr:1; //!< If 1, include the received header or length byte in the stored packet; otherwise discard it
uint8_t bIncludeCrc:1; //!< If 1, include the received CRC field in the stored packet; otherwise discard it
uint8_t bAppendRssi:1; //!< If 1, append an RSSI byte to the packet in the Rx queue
uint8_t bAppendTimestamp:1; //!< If 1, append a timestamp to the packet in the Rx queue
uint8_t bAppendStatus:1; //!< If 1, append a status byte to the packet in the Rx queue
} rxConf; //!< Rx configuration
uint32_t syncWord; //!< Sync word to listen for
uint8_t maxPktLen; //!< \brief Packet length for fixed length, maximum packet length for variable length<br>
//!< 0: Unlimited or unknown length
uint8_t address0; //!< Address
uint8_t address1; //!< \brief Address (set equal to <code>address0</code> to accept only one address. If 0xFF, accept
//!< 0x00 as well)
struct {
uint8_t triggerType:4; //!< The type of trigger
uint8_t bEnaCmd:1; //!< \brief 0: No alternative trigger command<br>
//!< 1: CMD_TRIGGER can be used as an alternative trigger
uint8_t triggerNo:2; //!< The trigger number of the CMD_TRIGGER command that triggers this action
uint8_t pastTrig:1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error<br>
//!< 1: A trigger in the past is triggered as soon as possible
} endTrigger; //!< Trigger classifier for ending the operation
ratmr_t endTime; //!< Time used together with <code>endTrigger</code> for ending the operation
dataQueue_t* pQueue; //!< Pointer to receive queue
uint8_t* pOutput; //!< Pointer to output structure
};
//! @}
//! \addtogroup CMD_PROP_TX_ADV
//! @{
#define CMD_PROP_TX_ADV 0x3803
struct __RFC_STRUCT rfc_CMD_PROP_TX_ADV_s {
uint16_t commandNo; //!< The command ID number 0x3803
uint16_t status; //!< \brief An integer telling the status of the command. This value is
//!< updated by the radio CPU during operation and may be read by the
//!< system CPU at any time.
rfc_radioOp_t *pNextOp; //!< Pointer to the next operation to run after this operation is done
ratmr_t startTime; //!< Absolute or relative start time (depending on the value of <code>startTrigger</code>)
struct {
uint8_t triggerType:4; //!< The type of trigger
uint8_t bEnaCmd:1; //!< \brief 0: No alternative trigger command<br>
//!< 1: CMD_TRIGGER can be used as an alternative trigger
uint8_t triggerNo:2; //!< The trigger number of the CMD_TRIGGER command that triggers this action
uint8_t pastTrig:1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error<br>
//!< 1: A trigger in the past is triggered as soon as possible
} startTrigger; //!< Identification of the trigger that starts the operation
struct {
uint8_t rule:4; //!< Condition for running next command: Rule for how to proceed
uint8_t nSkip:4; //!< Number of skips if the rule involves skipping
} condition;
struct {
uint8_t bFsOff:1; //!< \brief 0: Keep frequency synth on after command<br>
//!< 1: Turn frequency synth off after command
uint8_t :2;
uint8_t bUseCrc:1; //!< \brief 0: Do not append CRC<br>
//!< 1: Append CRC
uint8_t bCrcIncSw:1; //!< \brief 0:Do not include sync word in CRC calculation<br>
//!< 1: Include sync word in CRC calculation
uint8_t bCrcIncHdr:1; //!< \brief 0: Do not include header in CRC calculation<br>
//!< 1: Include header in CRC calculation
} pktConf;
uint8_t numHdrBits; //!< Number of bits in header (0&ndash;32)
uint16_t pktLen; //!< Packet length. 0: Unlimited
struct {
uint8_t bExtTxTrig:1; //!< \brief 0: Start packet on a fixed time from the command start trigger<br>
//!< 1: Start packet on an external trigger (input event to RAT)
uint8_t inputMode:2; //!< \brief Input mode if external trigger is used for Tx start<br>
//!< 0: Rising edge<br>
//!< 1: Falling edge<br>
//!< 2: Both edges<br>
//!< 3: <i>Reserved</i>
uint8_t source:5; //!< RAT input event number used for capture if external trigger is used for Tx start
} startConf;
struct {
uint8_t triggerType:4; //!< The type of trigger
uint8_t bEnaCmd:1; //!< \brief 0: No alternative trigger command<br>
//!< 1: CMD_TRIGGER can be used as an alternative trigger
uint8_t triggerNo:2; //!< The trigger number of the CMD_TRIGGER command that triggers this action
uint8_t pastTrig:1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error<br>
//!< 1: A trigger in the past is triggered as soon as possible
} preTrigger; //!< Trigger for transition from preamble to sync word
ratmr_t preTime; //!< \brief Time used together with <code>preTrigger</code> for transition from preamble to sync
//!< word. If <code>preTrigger.triggerType</code> is set to "now", one preamble as
//!< configured in the setup will be sent. Otherwise, the preamble will be repeated until
//!< this trigger is observed.
uint32_t syncWord; //!< Sync word to transmit
uint8_t* pPkt; //!< Pointer to packet, or Tx queue for unlimited length
};
//! @}
//! \addtogroup CMD_PROP_RX_ADV
//! @{
#define CMD_PROP_RX_ADV 0x3804
struct __RFC_STRUCT rfc_CMD_PROP_RX_ADV_s {
uint16_t commandNo; //!< The command ID number 0x3804
uint16_t status; //!< \brief An integer telling the status of the command. This value is
//!< updated by the radio CPU during operation and may be read by the
//!< system CPU at any time.
rfc_radioOp_t *pNextOp; //!< Pointer to the next operation to run after this operation is done
ratmr_t startTime; //!< Absolute or relative start time (depending on the value of <code>startTrigger</code>)
struct {
uint8_t triggerType:4; //!< The type of trigger
uint8_t bEnaCmd:1; //!< \brief 0: No alternative trigger command<br>
//!< 1: CMD_TRIGGER can be used as an alternative trigger
uint8_t triggerNo:2; //!< The trigger number of the CMD_TRIGGER command that triggers this action
uint8_t pastTrig:1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error<br>
//!< 1: A trigger in the past is triggered as soon as possible
} startTrigger; //!< Identification of the trigger that starts the operation
struct {
uint8_t rule:4; //!< Condition for running next command: Rule for how to proceed
uint8_t nSkip:4; //!< Number of skips if the rule involves skipping
} condition;
struct {
uint8_t bFsOff:1; //!< \brief 0: Keep frequency synth on after command<br>
//!< 1: Turn frequency synth off after command
uint8_t bRepeatOk:1; //!< \brief 0: End operation after receiving a packet correctly<br>
//!< 1: Go back to sync search after receiving a packet correctly
uint8_t bRepeatNok:1; //!< \brief 0: End operation after receiving a packet with CRC error<br>
//!< 1: Go back to sync search after receiving a packet with CRC error
uint8_t bUseCrc:1; //!< \brief 0: Do not check CRC<br>
//!< 1: Check CRC
uint8_t bCrcIncSw:1; //!< \brief 0: Do not include sync word in CRC calculation<br>
//!< 1: Include sync word in CRC calculation
uint8_t bCrcIncHdr:1; //!< \brief 0: Do not include header in CRC calculation <br>
//!< 1: Include header in CRC calculation
uint8_t endType:1; //!< \brief 0: Packet is received to the end if end trigger happens after sync is obtained<br>
//!< 1: Packet reception is stopped if end trigger happens
uint8_t filterOp:1; //!< \brief 0: Stop receiver and restart sync search on address mismatch<br>
//!< 1: Receive packet and mark it as ignored on address mismatch
} pktConf;
struct {
uint8_t bAutoFlushIgnored:1; //!< If 1, automatically discard ignored packets from Rx queue
uint8_t bAutoFlushCrcErr:1; //!< If 1, automatically discard packets with CRC error from Rx queue
uint8_t :1;
uint8_t bIncludeHdr:1; //!< If 1, include the received header or length byte in the stored packet; otherwise discard it
uint8_t bIncludeCrc:1; //!< If 1, include the received CRC field in the stored packet; otherwise discard it
uint8_t bAppendRssi:1; //!< If 1, append an RSSI byte to the packet in the Rx queue
uint8_t bAppendTimestamp:1; //!< If 1, append a timestamp to the packet in the Rx queue
uint8_t bAppendStatus:1; //!< If 1, append a status byte to the packet in the Rx queue
} rxConf; //!< Rx configuration
uint32_t syncWord0; //!< Sync word to listen for
uint32_t syncWord1; //!< Alternative sync word if non-zero
uint16_t maxPktLen; //!< \brief Packet length for fixed length, maximum packet length for variable length<br>
//!< 0: Unlimited or unknown length
struct {
uint16_t numHdrBits:6; //!< Number of bits in header (0&ndash;32)
uint16_t lenPos:5; //!< Position of length field in header (0&ndash;31)
uint16_t numLenBits:5; //!< Number of bits in length field (0&ndash;16)
} hdrConf;
struct {
uint16_t addrType:1; //!< \brief 0: Address after header<br>
//!< 1: Address in header
uint16_t addrSize:5; //!< \brief If <code>addrType</code> = 0: Address size in bytes<br>
//!< If <code>addrType</code> = 1: Address size in bits
uint16_t addrPos:5; //!< \brief If <code>addrType</code> = 1: Bit position of address in header<br>
//!< If <code>addrType</code> = 0: Non-zero to extend address with sync word identifier
uint16_t numAddr:5; //!< Number of addresses in address list
} addrConf;
int8_t lenOffset; //!< Signed value to add to length field
struct {
uint8_t triggerType:4; //!< The type of trigger
uint8_t bEnaCmd:1; //!< \brief 0: No alternative trigger command<br>
//!< 1: CMD_TRIGGER can be used as an alternative trigger
uint8_t triggerNo:2; //!< The trigger number of the CMD_TRIGGER command that triggers this action
uint8_t pastTrig:1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error<br>
//!< 1: A trigger in the past is triggered as soon as possible
} endTrigger; //!< Trigger classifier for ending the operation
ratmr_t endTime; //!< Time used together with <code>endTrigger</code> for ending the operation
uint8_t* pAddr; //!< Pointer to address list
dataQueue_t* pQueue; //!< Pointer to receive queue
uint8_t* pOutput; //!< Pointer to output structure
};
//! @}
//! \addtogroup CMD_PROP_RADIO_SETUP
//! @{
#define CMD_PROP_RADIO_SETUP 0x3806
struct __RFC_STRUCT rfc_CMD_PROP_RADIO_SETUP_s {
uint16_t commandNo; //!< The command ID number 0x3806
uint16_t status; //!< \brief An integer telling the status of the command. This value is
//!< updated by the radio CPU during operation and may be read by the
//!< system CPU at any time.
rfc_radioOp_t *pNextOp; //!< Pointer to the next operation to run after this operation is done
ratmr_t startTime; //!< Absolute or relative start time (depending on the value of <code>startTrigger</code>)
struct {
uint8_t triggerType:4; //!< The type of trigger
uint8_t bEnaCmd:1; //!< \brief 0: No alternative trigger command<br>
//!< 1: CMD_TRIGGER can be used as an alternative trigger
uint8_t triggerNo:2; //!< The trigger number of the CMD_TRIGGER command that triggers this action
uint8_t pastTrig:1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error<br>
//!< 1: A trigger in the past is triggered as soon as possible
} startTrigger; //!< Identification of the trigger that starts the operation
struct {
uint8_t rule:4; //!< Condition for running next command: Rule for how to proceed
uint8_t nSkip:4; //!< Number of skips if the rule involves skipping
} condition;
struct {
uint16_t modType:3; //!< \brief 0: FSK<br>
//!< 1: GFSK<br>
//!< Others: <i>Reserved</i>
uint16_t deviation:13; //!< Deviation (250 Hz steps)
} modulation;
struct {
uint32_t preScale:4; //!< Prescaler value
uint32_t :4;
uint32_t rateWord:21; //!< Rate word
} symbolRate;
uint8_t rxBw; //!< Receiver bandwidth
struct {
uint8_t nPreamBytes:6; //!< \brief 0&ndash;30: Number of preamble bytes<br>
//!< 31: 4 preamble bits
uint8_t preamMode:2; //!< \brief 0: Send 0 as the first preamble bit<br>
//!< 1: Send 1 as the first preamble bit<br>
//!< 2: Send same first bit in preamble and sync word<br>
//!< 3: Send different first bit in preamble and sync word
} preamConf;
struct {
uint16_t nSwBits:6; //!< Number of sync word bits (up to 32)
uint16_t bBitReversal:1; //!< \brief 0: Use positive deviation for 1<br>
//!< 1: Use positive deviation for 0
uint16_t bMsbFirst:1; //!< \brief 0: Least significant bit transmitted first<br>
//!< 1: Most significant bit transmitted first
uint16_t fecMode:4; //!< \brief Select coding<br>
//!< 0: Uncoded binary modulation<br>
//!< 10: Manchester coded binary modulation<br>
//!< Others: <i>Reserved</i>
uint16_t :1;
uint16_t whitenMode:3; //!< \brief 0: No whitening<br>
//!< 1: CC1101/CC2500 compatible whitening<br>
//!< 2: PN9 whitening without byte reversal<br>
//!< 3: <i>Reserved</i><br>
//!< 4: No whitener, 32-bit IEEE 802.15.4g compatible CRC<br>
//!< 5: IEEE 802.15.4g compatible whitener and 32-bit CRC<br>
//!< 6: No whitener, dynamically IEEE 802.15.4g compatible 16-bit or 32-bit CRC<br>
//!< 7: Dynamically IEEE 802.15.4g compatible whitener and 16-bit or 32-bit CRC
} formatConf;
struct {
uint16_t frontEndMode:3; //!< \brief 0x00: Differential mode<br>
//!< 0x01: Single-ended mode RFP<br>
//!< 0x02: Single-ended mode RFN<br>
//!< 0x05 Single-ended mode RFP with external frontend control on RF pins (RFN and RXTX)<br>
//!< 0x06 Single-ended mode RFN with external frontend control on RF pins (RFP and RXTX)<br>
//!< Others: <i>Reserved</i>
uint16_t biasMode:1; //!< \brief 0: Internal bias<br>
//!< 1: External bias
uint16_t :6;
uint16_t bNoFsPowerUp:1; //!< \brief 0: Power up frequency synth<br>
//!< 1: Do not power up frequency synth
} config; //!< Configuration options
uint16_t txPower; //!< Transmit power
uint32_t* pRegOverride; //!< \brief Pointer to a list of hardware and configuration registers to override. If NULL, no
//!< override is used.
};
//! @}
//! \addtogroup CMD_PROP_RADIO_DIV_SETUP
//! @{
#define CMD_PROP_RADIO_DIV_SETUP 0x3807
struct __RFC_STRUCT rfc_CMD_PROP_RADIO_DIV_SETUP_s {
uint16_t commandNo; //!< The command ID number 0x3807
uint16_t status; //!< \brief An integer telling the status of the command. This value is
//!< updated by the radio CPU during operation and may be read by the
//!< system CPU at any time.
rfc_radioOp_t *pNextOp; //!< Pointer to the next operation to run after this operation is done
ratmr_t startTime; //!< Absolute or relative start time (depending on the value of <code>startTrigger</code>)
struct {
uint8_t triggerType:4; //!< The type of trigger
uint8_t bEnaCmd:1; //!< \brief 0: No alternative trigger command<br>
//!< 1: CMD_TRIGGER can be used as an alternative trigger
uint8_t triggerNo:2; //!< The trigger number of the CMD_TRIGGER command that triggers this action
uint8_t pastTrig:1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error<br>
//!< 1: A trigger in the past is triggered as soon as possible
} startTrigger; //!< Identification of the trigger that starts the operation
struct {
uint8_t rule:4; //!< Condition for running next command: Rule for how to proceed
uint8_t nSkip:4; //!< Number of skips if the rule involves skipping
} condition;
struct {
uint16_t modType:3; //!< \brief 0: FSK<br>
//!< 1: GFSK<br>
//!< Others: <i>Reserved</i>
uint16_t deviation:13; //!< Deviation (250 Hz steps)
} modulation;
struct {
uint32_t preScale:4; //!< Prescaler value
uint32_t :4;
uint32_t rateWord:21; //!< Rate word
} symbolRate;
uint8_t rxBw; //!< Receiver bandwidth
struct {
uint8_t nPreamBytes:6; //!< \brief 0&ndash;30: Number of preamble bytes<br>
//!< 31: 4 preamble bits
uint8_t preamMode:2; //!< \brief 0: Send 0 as the first preamble bit<br>
//!< 1: Send 1 as the first preamble bit<br>
//!< 2: Send same first bit in preamble and sync word<br>
//!< 3: Send different first bit in preamble and sync word
} preamConf;
struct {
uint16_t nSwBits:6; //!< Number of sync word bits (up to 32)
uint16_t bBitReversal:1; //!< \brief 0: Use positive deviation for 1<br>
//!< 1: Use positive deviation for 0
uint16_t bMsbFirst:1; //!< \brief 0: Least significant bit transmitted first<br>
//!< 1: Most significant bit transmitted first
uint16_t fecMode:4; //!< \brief Select coding<br>
//!< 0: Uncoded binary modulation<br>
//!< 10: Manchester coded binary modulation<br>
//!< Others: <i>Reserved</i>
uint16_t :1;
uint16_t whitenMode:3; //!< \brief 0: No whitening<br>
//!< 1: CC1101/CC2500 compatible whitening<br>
//!< 2: PN9 whitening without byte reversal<br>
//!< 3: <i>Reserved</i><br>
//!< 4: No whitener, 32-bit IEEE 802.15.4g compatible CRC<br>
//!< 5: IEEE 802.15.4g compatible whitener and 32-bit CRC<br>
//!< 6: No whitener, dynamically IEEE 802.15.4g compatible 16-bit or 32-bit CRC<br>
//!< 7: Dynamically IEEE 802.15.4g compatible whitener and 16-bit or 32-bit CRC
} formatConf;
struct {
uint16_t frontEndMode:3; //!< \brief 0x00: Differential mode<br>
//!< 0x01: Single-ended mode RFP<br>
//!< 0x02: Single-ended mode RFN<br>
//!< 0x05 Single-ended mode RFP with external frontend control on RF pins (RFN and RXTX)<br>
//!< 0x06 Single-ended mode RFN with external frontend control on RF pins (RFP and RXTX)<br>
//!< Others: <i>Reserved</i>
uint16_t biasMode:1; //!< \brief 0: Internal bias<br>
//!< 1: External bias
uint16_t :6;
uint16_t bNoFsPowerUp:1; //!< \brief 0: Power up frequency synth<br>
//!< 1: Do not power up frequency synth
} config; //!< Configuration options
uint16_t txPower; //!< Transmit power
uint32_t* pRegOverride; //!< \brief Pointer to a list of hardware and configuration registers to override. If NULL, no
//!< override is used.
uint16_t centerFreq; //!< \brief Center frequency of the frequency band used, in MHz; used for calculating some internal Tx and Rx parameters.
//!< For a single channel RF system, this should be set equal to the RF frequency used.
//!< For a multi channel RF system (e.g. frequency hopping spread spectrum), this should be set equal
//!< to the center frequency of the frequency band used.
int16_t intFreq; //!< \brief Intermediate frequency to use for Rx, in MHz on 4.12 signed format. Tx will use same
//!< intermediate frequency if supported, otherwise 0.<br>
//!< 0x8000: Use default.
uint8_t loDivider; //!< LO frequency divider setting to use. Supported values: 2, 5, 6, 10, 12, 15, and 30
};
//! @}
//! \addtogroup CMD_PROP_SET_LEN
//! @{
#define CMD_PROP_SET_LEN 0x3401
struct __RFC_STRUCT rfc_CMD_PROP_SET_LEN_s {
uint16_t commandNo; //!< The command ID number 0x3401
uint16_t rxLen; //!< Payload length to use
};
//! @}
//! \addtogroup CMD_PROP_RESTART_RX
//! @{
#define CMD_PROP_RESTART_RX 0x3402
struct __RFC_STRUCT rfc_CMD_PROP_RESTART_RX_s {
uint16_t commandNo; //!< The command ID number 0x3402
};
//! @}
//! \addtogroup propRxOutput
//! @{
//! Output structure for Rx operations
struct __RFC_STRUCT rfc_propRxOutput_s {
uint16_t nRxOk; //!< Number of packets that have been received with payload, CRC OK and not ignored
uint16_t nRxNok; //!< Number of packets that have been received with CRC error
uint8_t nRxIgnored; //!< Number of packets that have been received with CRC OK and ignored due to address mismatch
uint8_t nRxStopped; //!< Number of packets not received due to illegal length or address mismatch with pktConf.filterOp = 1
uint8_t nRxBufFull; //!< Number of packets that have been received and discarded due to lack of buffer space
int8_t lastRssi; //!< RSSI of last received packet
ratmr_t timeStamp; //!< Time stamp of last received packet
};
//! @}
//! \addtogroup propRxStatus
//! @{
//! Receive status byte that may be appended to message in receive buffer
struct __RFC_STRUCT rfc_propRxStatus_s {
struct {
uint8_t addressInd:5; //!< Index of address found (0 if not applicable)
uint8_t syncWordId:1; //!< 0 for primary sync word, 1 for alternate sync word
uint8_t result:2; //!< \brief 0: Packet received correctly, not ignored<br>
//!< 1: Packet received with CRC error<br>
//!< 2: Packet received correctly, but can be ignored<br>
//!< 3: Packet reception was aborted
} status;
};
//! @}
//! @}
//! @}
#endif /* PROP_CMD_H_ */

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/******************************************************************************
* Filename: prop_mailbox.h
* Revised: 2015-06-29 12:59:58 +0200 (Mon, 29 Jun 2015)
* Revision: 44063
*
* Description: Definitions for proprietary mode radio interface
*
* Copyright (c) 2015, Texas Instruments Incorporated
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1) Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2) Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3) Neither the name of the ORGANIZATION nor the names of its contributors may
* be used to endorse or promote products derived from this software without
* specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************/
#ifndef PROP_MAILBOX_H_
#define PROP_MAILBOX_H_
/// \name Radio operation status
///@{
/// \name Operation finished normally
///@{
#define PROP_DONE_OK 0x3400 ///< Operation ended normally
#define PROP_DONE_RXTIMEOUT 0x3401 ///< Operation stopped after end trigger while waiting for sync
#define PROP_DONE_BREAK 0x3402 ///< Rx stopped due to time out in the middle of a packet
#define PROP_DONE_ENDED 0x3403 ///< Operation stopped after end trigger during reception
#define PROP_DONE_STOPPED 0x3404 ///< Operation stopped after stop command
#define PROP_DONE_ABORT 0x3405 ///< Operation aborted by abort command
#define PROP_DONE_RXERR 0x3406 ///< Operation ended after receiving packet with CRC error
#define PROP_DONE_IDLE 0x3407 ///< Carrier sense operation ended because of idle channel
#define PROP_DONE_BUSY 0x3408 ///< Carrier sense operation ended because of busy channel
#define PROP_DONE_IDLETIMEOUT 0x3409 ///< Carrier sense operation ended because of time out with csConf.timeoutRes = 1
#define PROP_DONE_BUSYTIMEOUT 0x340A ///< Carrier sense operation ended because of time out with csConf.timeoutRes = 0
///@}
/// \name Operation finished with error
///@{
#define PROP_ERROR_PAR 0x3800 ///< Illegal parameter
#define PROP_ERROR_RXBUF 0x3801 ///< No available Rx buffer at the start of a packet
#define PROP_ERROR_RXFULL 0x3802 ///< Out of Rx buffer during reception in a partial read buffer
#define PROP_ERROR_NO_SETUP 0x3803 ///< Radio was not set up in proprietary mode
#define PROP_ERROR_NO_FS 0x3804 ///< Synth was not programmed when running Rx or Tx
#define PROP_ERROR_RXOVF 0x3805 ///< Rx overflow observed during operation
#define PROP_ERROR_TXUNF 0x3806 ///< Tx underflow observed during operation
///@}
///@}
#endif /* PROP_MAILBOX_H_ */

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/*
* Copyright (c) 2015, Texas Instruments Incorporated - http://www.ti.com/
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. Neither the name of the copyright holder nor the names of its
* contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
* OF THE POSSIBILITY OF SUCH DAMAGE.
*/
/*---------------------------------------------------------------------------*/
/**
* \addtogroup rf-core
* @{
*
* \defgroup rf-core-15-4g-modes IEEE 802.15.4g Frequency Bands and Modes
*
* @{
*
* \file
* Header file with descriptors for the various modes of operation defined in
* IEEE 802.15.4g
*/
/*---------------------------------------------------------------------------*/
#ifndef DOT_15_4G_H_
#define DOT_15_4G_H_
/*---------------------------------------------------------------------------*/
#include "contiki-conf.h"
/*---------------------------------------------------------------------------*/
/* IEEE 802.15.4g frequency band identifiers (Table 68f) */
#define DOT_15_4G_FREQUENCY_BAND_169 0 /* 169.400–169.475 (Europe) - 169 MHz band */
#define DOT_15_4G_FREQUENCY_BAND_450 1 /* 450–470 (US FCC Part 22/90) - 450 MHz band */
#define DOT_15_4G_FREQUENCY_BAND_470 2 /* 470–510 (China) - 470 MHz band */
#define DOT_15_4G_FREQUENCY_BAND_780 3 /* 779–787 (China) - 780 MHz band */
#define DOT_15_4G_FREQUENCY_BAND_863 4 /* 863–870 (Europe) - 863 MHz band */
#define DOT_15_4G_FREQUENCY_BAND_896 5 /* 896–901 (US FCC Part 90) - 896 MHz band */
#define DOT_15_4G_FREQUENCY_BAND_901 6 /* 901–902 (US FCC Part 24) - 901 MHz band */
#define DOT_15_4G_FREQUENCY_BAND_915 7 /* 902–928 (US) - 915 MHz band */
#define DOT_15_4G_FREQUENCY_BAND_917 8 /* 917–923.5 (Korea) - 917 MHz band */
#define DOT_15_4G_FREQUENCY_BAND_920 9 /* 920–928 (Japan) - 920 MHz band */
#define DOT_15_4G_FREQUENCY_BAND_928 10 /* 928–960 (US, non-contiguous) - 928 MHz band */
#define DOT_15_4G_FREQUENCY_BAND_950 11 /* 950–958 (Japan) - 950 MHz band */
#define DOT_15_4G_FREQUENCY_BAND_1427 12 /* 1427–1518 (US and Canada, non-contiguous) - 1427 MHz band */
#define DOT_15_4G_FREQUENCY_BAND_2450 13 /* 2400–2483.5 2450 MHz band */
/*---------------------------------------------------------------------------*/
/* Default band selection to band 4 - 863MHz */
#ifdef DOT_15_4G_CONF_FREQUENCY_BAND_ID
#define DOT_15_4G_FREQUENCY_BAND_ID DOT_15_4G_CONF_FREQUENCY_BAND_ID
#else
#define DOT_15_4G_FREQUENCY_BAND_ID DOT_15_4G_FREQUENCY_BAND_863
#endif
/*---------------------------------------------------------------------------*/
/*
* Channel count, spacing and other params relating to the selected band. We
* currently only support some of the bands defined in .15.4g and for those
* bands we only support operating mode #1 (Table 134).
*
* DOT_15_4G_CHAN0_FREQUENCY is specified here in KHz
*/
#if DOT_15_4G_FREQUENCY_BAND_ID==DOT_15_4G_FREQUENCY_BAND_470
#define DOT_15_4G_CHANNEL_MAX 198
#define DOT_15_4G_CHANNEL_SPACING 200
#define DOT_15_4G_CHAN0_FREQUENCY 470200
#define PROP_MODE_CONF_LO_DIVIDER 0x0A
#elif DOT_15_4G_FREQUENCY_BAND_ID==DOT_15_4G_FREQUENCY_BAND_780
#define DOT_15_4G_CHANNEL_MAX 38
#define DOT_15_4G_CHANNEL_SPACING 200
#define DOT_15_4G_CHAN0_FREQUENCY 779200
#define PROP_MODE_CONF_LO_DIVIDER 0x06
#elif DOT_15_4G_FREQUENCY_BAND_ID==DOT_15_4G_FREQUENCY_BAND_863
#define DOT_15_4G_CHANNEL_MAX 33
#define DOT_15_4G_CHANNEL_SPACING 200
#define DOT_15_4G_CHAN0_FREQUENCY 863125
#define PROP_MODE_CONF_LO_DIVIDER 0x05
#elif DOT_15_4G_FREQUENCY_BAND_ID==DOT_15_4G_FREQUENCY_BAND_915
#define DOT_15_4G_CHANNEL_MAX 128
#define DOT_15_4G_CHANNEL_SPACING 200
#define DOT_15_4G_CHAN0_FREQUENCY 902200
#define PROP_MODE_CONF_LO_DIVIDER 0x05
#elif DOT_15_4G_FREQUENCY_BAND_ID==DOT_15_4G_FREQUENCY_BAND_920
#define DOT_15_4G_CHANNEL_MAX 37
#define DOT_15_4G_CHANNEL_SPACING 200
#define DOT_15_4G_CHAN0_FREQUENCY 920600
#define PROP_MODE_CONF_LO_DIVIDER 0x05
#elif DOT_15_4G_FREQUENCY_BAND_ID==DOT_15_4G_FREQUENCY_BAND_950
#define DOT_15_4G_CHANNEL_MAX 32
#define DOT_15_4G_CHANNEL_SPACING 200
#define DOT_15_4G_CHAN0_FREQUENCY 951000
#define PROP_MODE_CONF_LO_DIVIDER 0x05
#else
#error The selected frequency band is not supported
#endif
/*---------------------------------------------------------------------------*/
#endif /* DOT_15_4G_H_ */
/*---------------------------------------------------------------------------*/
/**
* @}
* @}
*/

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/*
* Copyright (c) 2015, Texas Instruments Incorporated - http://www.ti.com/
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. Neither the name of the copyright holder nor the names of its
* contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
* OF THE POSSIBILITY OF SUCH DAMAGE.
*/
/*---------------------------------------------------------------------------*/
/**
* \addtogroup rf-core-ble
* @{
*
* \file
* Implementation of the CC13xx/CC26xx RF BLE driver
*/
/*---------------------------------------------------------------------------*/
#include "contiki-conf.h"
#include "sys/process.h"
#include "sys/clock.h"
#include "sys/etimer.h"
#include "net/netstack.h"
#include "net/linkaddr.h"
#include "dev/oscillators.h"
#include "rf-core/rf-core.h"
#include "rf-core/rf-ble.h"
#include "rf-core/api/ble_cmd.h"
#include "rf-core/api/common_cmd.h"
#include "ti-lib.h"
/*---------------------------------------------------------------------------*/
#include <stdint.h>
#include <stdbool.h>
#include <stdio.h>
/*---------------------------------------------------------------------------*/
#ifdef __GNUC__
#define CC_ALIGN_ATTR(n) __attribute__ ((aligned(n)))
#else
#define CC_ALIGN_ATTR(n)
#endif
/*---------------------------------------------------------------------------*/
#define DEBUG 0
#if DEBUG
#define PRINTF(...) printf(__VA_ARGS__)
#else
#define PRINTF(...)
#endif
/*---------------------------------------------------------------------------*/
/* BLE Intervals: Send a burst of advertisements every BLE_ADV_INTERVAL secs */
#define BLE_ADV_INTERVAL (CLOCK_SECOND * 5)
#define BLE_ADV_DUTY_CYCLE (CLOCK_SECOND / 10)
#define BLE_ADV_MESSAGES 10
/* BLE Advertisement-related macros */
#define BLE_ADV_TYPE_DEVINFO 0x01
#define BLE_ADV_TYPE_NAME 0x09
#define BLE_ADV_TYPE_MANUFACTURER 0xFF
#define BLE_ADV_NAME_BUF_LEN 32
#define BLE_ADV_PAYLOAD_BUF_LEN 64
#define BLE_UUID_SIZE 16
/*---------------------------------------------------------------------------*/
static unsigned char ble_params_buf[32] CC_ALIGN_ATTR(4);
static uint8_t ble_mode_on = RF_BLE_IDLE;
static struct etimer ble_adv_et;
static uint8_t payload[BLE_ADV_PAYLOAD_BUF_LEN];
static int p = 0;
static int i;
/*---------------------------------------------------------------------------*/
typedef struct default_ble_tx_power_s {
uint16_t ib:6;
uint16_t gc:2;
uint16_t boost:1;
uint16_t temp_coeff:7;
} default_ble_tx_power_t;
static default_ble_tx_power_t tx_power = { 0x29, 0x00, 0x00, 0x00 };
/*---------------------------------------------------------------------------*/
/* BLE beacond config */
static struct ble_beacond_config {
clock_time_t interval;
char adv_name[BLE_ADV_NAME_BUF_LEN];
} beacond_config = { .interval = BLE_ADV_INTERVAL };
/*---------------------------------------------------------------------------*/
/* BLE overrides */
static uint32_t ble_overrides[] = {
0x00364038, /* Synth: Set RTRIM (POTAILRESTRIM) to 6 */
0x000784A3, /* Synth: Set FREF = 3.43 MHz (24 MHz / 7) */
0xA47E0583, /* Synth: Set loop bandwidth after lock to 80 kHz (K2) */
0xEAE00603, /* Synth: Set loop bandwidth after lock to 80 kHz (K3, LSB) */
0x00010623, /* Synth: Set loop bandwidth after lock to 80 kHz (K3, MSB) */
0x00456088, /* Adjust AGC reference level */
0xFFFFFFFF, /* End of override list */
};
/*---------------------------------------------------------------------------*/
PROCESS(rf_ble_beacon_process, "CC13xx / CC26xx RF BLE Beacon Process");
/*---------------------------------------------------------------------------*/
static int
send_ble_adv_nc(int channel, uint8_t *adv_payload, int adv_payload_len)
{
uint32_t cmd_status;
rfc_CMD_BLE_ADV_NC_t cmd;
rfc_bleAdvPar_t *params;
params = (rfc_bleAdvPar_t *)ble_params_buf;
/* Clear both buffers */
memset(&cmd, 0x00, sizeof(cmd));
memset(ble_params_buf, 0x00, sizeof(ble_params_buf));
/* Adv NC */
cmd.commandNo = CMD_BLE_ADV_NC;
cmd.condition.rule = COND_NEVER;
cmd.whitening.bOverride = 0;
cmd.whitening.init = 0;
cmd.pParams = params;
cmd.channel = channel;
/* Set up BLE Advertisement parameters */
params->pDeviceAddress = (uint16_t *)&linkaddr_node_addr.u8[LINKADDR_SIZE - 2];
params->endTrigger.triggerType = TRIG_NEVER;
params->endTime = TRIG_NEVER;
/* Set up BLE Advertisement parameters */
params = (rfc_bleAdvPar_t *)ble_params_buf;
params->advLen = adv_payload_len;
params->pAdvData = adv_payload;
if(rf_core_send_cmd((uint32_t)&cmd, &cmd_status) == RF_CORE_CMD_ERROR) {
PRINTF("send_ble_adv_nc: Chan=%d CMDSTA=0x%08lx, status=0x%04x\n",
channel, cmd_status, cmd.status);
return RF_CORE_CMD_ERROR;
}
/* Wait until the command is done */
if(rf_core_wait_cmd_done(&cmd) != RF_CORE_CMD_OK) {
PRINTF("send_ble_adv_nc: Chan=%d CMDSTA=0x%08lx, status=0x%04x\n",
channel, cmd_status, cmd.status);
return RF_CORE_CMD_ERROR;
}
return RF_CORE_CMD_OK;
}
/*---------------------------------------------------------------------------*/
void
rf_ble_beacond_config(clock_time_t interval, const char *name)
{
if(RF_BLE_ENABLED == 0) {
return;
}
if(name != NULL) {
if(strlen(name) == 0 || strlen(name) >= BLE_ADV_NAME_BUF_LEN) {
return;
}
memset(beacond_config.adv_name, 0, BLE_ADV_NAME_BUF_LEN);
memcpy(beacond_config.adv_name, name, strlen(name));
}
if(interval != 0) {
beacond_config.interval = interval;
}
}
/*---------------------------------------------------------------------------*/
uint8_t
rf_ble_beacond_start()
{
if(RF_BLE_ENABLED == 0) {
return RF_CORE_CMD_ERROR;
}
if(ti_lib_chipinfo_supports_ble() == false) {
return RF_CORE_CMD_ERROR;
}
if(beacond_config.adv_name[0] == 0) {
return RF_CORE_CMD_ERROR;
}
ble_mode_on = RF_BLE_IDLE;
process_start(&rf_ble_beacon_process, NULL);
return RF_CORE_CMD_OK;
}
/*---------------------------------------------------------------------------*/
uint8_t
rf_ble_is_active()
{
return ble_mode_on;
}
/*---------------------------------------------------------------------------*/
void
rf_ble_beacond_stop()
{
process_exit(&rf_ble_beacon_process);
}
/*---------------------------------------------------------------------------*/
static uint8_t
rf_radio_setup()
{
uint32_t cmd_status;
rfc_CMD_RADIO_SETUP_t cmd;
/* Create radio setup command */
rf_core_init_radio_op((rfc_radioOp_t *)&cmd, sizeof(cmd), CMD_RADIO_SETUP);
cmd.txPower.IB = tx_power.ib;
cmd.txPower.GC = tx_power.gc;
cmd.txPower.tempCoeff = tx_power.temp_coeff;
cmd.txPower.boost = tx_power.boost;
cmd.pRegOverride = ble_overrides;
cmd.mode = 0;
/* Send Radio setup to RF Core */
if(rf_core_send_cmd((uint32_t)&cmd, &cmd_status) != RF_CORE_CMD_OK) {
PRINTF("rf_radio_setup: CMDSTA=0x%08lx, status=0x%04x\n",
cmd_status, cmd.status);
return RF_CORE_CMD_ERROR;
}
/* Wait until radio setup is done */
if(rf_core_wait_cmd_done(&cmd) != RF_CORE_CMD_OK) {
PRINTF("rf_radio_setup: wait, CMDSTA=0x%08lx, status=0x%04x\n",
cmd_status, cmd.status);
return RF_CORE_CMD_ERROR;
}
return RF_CORE_CMD_OK;
}
/*---------------------------------------------------------------------------*/
PROCESS_THREAD(rf_ble_beacon_process, ev, data)
{
uint8_t was_on;
int j;
uint32_t cmd_status;
bool interrupts_disabled;
PROCESS_BEGIN();
while(1) {
etimer_set(&ble_adv_et, beacond_config.interval);
PROCESS_WAIT_EVENT();
if(ev == PROCESS_EVENT_EXIT) {
PROCESS_EXIT();
}
/* Set the adv payload each pass: The device name may have changed */
p = 0;
/* device info */
memset(payload, 0, BLE_ADV_PAYLOAD_BUF_LEN);
payload[p++] = 0x02; /* 2 bytes */
payload[p++] = BLE_ADV_TYPE_DEVINFO;
payload[p++] = 0x1a; /* LE general discoverable + BR/EDR */
payload[p++] = 1 + strlen(beacond_config.adv_name);
payload[p++] = BLE_ADV_TYPE_NAME;
memcpy(&payload[p], beacond_config.adv_name,
strlen(beacond_config.adv_name));
p += strlen(beacond_config.adv_name);
for(i = 0; i < BLE_ADV_MESSAGES; i++) {
/*
* Under ContikiMAC, some IEEE-related operations will be called from an
* interrupt context. We need those to see that we are in BLE mode.
*/
interrupts_disabled = ti_lib_int_master_disable();
ble_mode_on = RF_BLE_ACTIVE;
if(!interrupts_disabled) {
ti_lib_int_master_enable();
}
/*
* Send BLE_ADV_MESSAGES beacon bursts. Each burst on all three
* channels, with a BLE_ADV_DUTY_CYCLE interval between bursts
*
* First, determine our state:
*
* If we are running NullRDC, we are likely in IEEE RX mode. We need to
* abort the IEEE BG Op before entering BLE mode.
* If we are ContikiMAC, we are likely off, in which case we need to
* boot the CPE before entering BLE mode
*/
was_on = rf_core_is_accessible();
if(was_on) {
/*
* We were on: If we are in the process of receiving a frame, abort the
* BLE beacon burst. Otherwise, terminate the primary radio Op so we
* can switch to BLE mode
*/
if(NETSTACK_RADIO.receiving_packet()) {
PRINTF("rf_ble_beacon_process: We were receiving\n");
/* Abort this pass */
break;
}
rf_core_primary_mode_abort();
} else {
/* Request the HF XOSC to source the HF clock. */
oscillators_request_hf_xosc();
/* We were off: Boot the CPE */
if(rf_core_boot() != RF_CORE_CMD_OK) {
PRINTF("rf_ble_beacon_process: rf_core_boot() failed\n");
/* Abort this pass */
break;
}
/* Trigger a switch to the XOSC, so that we can use the FS */
oscillators_switch_to_hf_xosc();
}
/* Enter BLE mode */
if(rf_radio_setup() != RF_CORE_CMD_OK) {
PRINTF("cc26xx_rf_ble_beacon_process: Error entering BLE mode\n");
/* Continue so we can at least try to restore our previous state */
} else {
/* Send advertising packets on all 3 advertising channels */
for(j = 37; j <= 39; j++) {
if(send_ble_adv_nc(j, payload, p) != RF_CORE_CMD_OK) {
PRINTF("cc26xx_rf_ble_beacon_process: Channel=%d, "
"Error advertising\n", j);
/* Break the loop, but don't return just yet */
break;
}
}
}
/* Send a CMD_STOP command to RF Core */
if(rf_core_send_cmd(CMDR_DIR_CMD(CMD_STOP), &cmd_status) != RF_CORE_CMD_OK) {
PRINTF("cc26xx_rf_ble_beacon_process: status=0x%08lx\n", cmd_status);
/* Continue... */
}
if(was_on) {
/* We were on, go back to previous primary mode */
rf_core_primary_mode_restore();
} else {
/* We were off. Shut back off */
rf_core_power_down();
/* Switch HF clock source to the RCOSC to preserve power */
oscillators_switch_to_hf_rc();
}
etimer_set(&ble_adv_et, BLE_ADV_DUTY_CYCLE);
interrupts_disabled = ti_lib_int_master_disable();
ble_mode_on = RF_BLE_IDLE;
if(!interrupts_disabled) {
ti_lib_int_master_enable();
}
/* Wait unless this is the last burst */
if(i < BLE_ADV_MESSAGES - 1) {
PROCESS_WAIT_EVENT();
}
}
interrupts_disabled = ti_lib_int_master_disable();
ble_mode_on = RF_BLE_IDLE;
if(!interrupts_disabled) {
ti_lib_int_master_enable();
}
}
PROCESS_END();
}
/*---------------------------------------------------------------------------*/
/**
* @}
* @}
*/

80
cpu/cc26xx/dev/cc26xx-rf.h → cpu/cc26xx-cc13xx/rf-core/rf-ble.h
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 2014, Texas Instruments Incorporated - http://www.ti.com/
* Copyright (c) 2015, Texas Instruments Incorporated - http://www.ti.com/
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@ -10,7 +10,6 @@
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* 3. Neither the name of the copyright holder nor the names of its
* contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
@ -28,59 +27,35 @@
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
* OF THE POSSIBILITY OF SUCH DAMAGE.
*/
/*---------------------------------------------------------------------------*/
/**
* \addtogroup cc26xx
* \addtogroup rf-core
* @{
*
* \defgroup cc26xx-rf CC26xx RF driver
*
* The CC26xx RF has dual capability: It can operate in IEEE 802.15.4 mode at
* 2.4GHz, but it can also operate in BLE mode. This driver provides a fully
* contiki-compliant .15.4 functionality, but it also provides some very basic
* BLE capability.
* \defgroup rf-core-ble CC13xx/CC26xx BLE driver
*
* @{
*/
/**
*
* \file
* Header file for the CC26xx RF driver
* Header file for the CC13xx/CC26xx BLE driver
*/
#ifndef CC26XX_RF_H_
#define CC26XX_RF_H_
/*---------------------------------------------------------------------------*/
#include "contiki.h"
#include "cc26xx-model.h"
#include "dev/radio.h"
#ifndef RF_BLE_H_
#define RF_BLE_H_
/*---------------------------------------------------------------------------*/
#include "contiki-conf.h"
#include "rf-core/rf-core.h"
#include <stdint.h>
/*---------------------------------------------------------------------------*/
#ifdef CC26XX_RF_CONF_CHANNEL
#define CC26XX_RF_CHANNEL CC26XX_RF_CONF_CHANNEL
#ifdef RF_BLE_CONF_ENABLED
#define RF_BLE_ENABLED RF_BLE_CONF_ENABLED
#else
#define CC26XX_RF_CHANNEL 18
#endif /* CC26XX_RF_CONF_CHANNEL */
#ifdef CC26XX_RF_CONF_AUTOACK
#define CC26XX_RF_AUTOACK CC26XX_RF_CONF_AUTOACK
#else
#define CC26XX_RF_AUTOACK 1
#endif /* CC26XX_RF_CONF_AUTOACK */
#if (CC26XX_RF_CONF_BLE_SUPPORT) && (CC26XX_MODEL_CPU_VARIANT == 2650)
#define CC26XX_RF_BLE_SUPPORT CC26XX_RF_CONF_BLE_SUPPORT
#else
#define CC26XX_RF_BLE_SUPPORT 0
#define RF_BLE_ENABLED 1
#endif
/*---------------------------------------------------------------------------
* RF Config
*---------------------------------------------------------------------------*/
/* Constants */
#define CC26XX_RF_CHANNEL_MIN 11
#define CC26XX_RF_CHANNEL_MAX 26
#define CC26XX_RF_CHANNEL_SPACING 5
#define CC26XX_RF_CHANNEL_SET_ERROR -1
#define CC26XX_RF_MAX_PACKET_LEN 127
#define CC26XX_RF_MIN_PACKET_LEN 4
/*---------------------------------------------------------------------------*/
#define RF_BLE_IDLE 0
#define RF_BLE_ACTIVE 1
/*---------------------------------------------------------------------------*/
/**
* \brief Set the device name to use with the BLE advertisement/beacon daemon
@ -91,24 +66,31 @@
* this function can be used to configure a single parameter at a time if so
* desired.
*/
void cc26xx_rf_ble_beacond_config(clock_time_t interval, const char *name);
void rf_ble_beacond_config(clock_time_t interval, const char *name);
/**
* \brief Start the BLE advertisement/beacon daemon
* \return 1: Success, 0: Failure
* \return RF_CORE_CMD_OK: Success, RF_CORE_CMD_ERROR: Failure
*
* Before calling this function, the name to advertise must first be set by
* calling cc26xx_rf_ble_beacond_set_adv_name(). Otherwise, this function will
* return an error.
* calling rf_ble_beacond_config(). Otherwise, this function will return an
* error.
*/
uint8_t cc26xx_rf_ble_beacond_start(void);
uint8_t rf_ble_beacond_start(void);
/**
* \brief Stop the BLE advertisement/beacon daemon
*/
void cc26xx_rf_ble_beacond_stop(void);
void rf_ble_beacond_stop(void);
/**
* \brief Check whether the BLE beacond is currently active
* \retval 1 The radio is in BLE mode
* \retval 0 The BLE daemon is not active, or disabled
*/
uint8_t rf_ble_is_active(void);
/*---------------------------------------------------------------------------*/
#endif /* CC26XX_RF_H_ */
#endif /* RF_BLE_H_ */
/*---------------------------------------------------------------------------*/
/**
* @}

518
cpu/cc26xx-cc13xx/rf-core/rf-core.c Normal file
View File

@ -0,0 +1,518 @@
/*
* Copyright (c) 2015, Texas Instruments Incorporated - http://www.ti.com/
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. Neither the name of the copyright holder nor the names of its
* contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
* OF THE POSSIBILITY OF SUCH DAMAGE.
*/
/*---------------------------------------------------------------------------*/
/**
* \addtogroup rf-core
* @{
*
* \file
* Implementation of the CC13xx/CC26xx RF core driver
*/
/*---------------------------------------------------------------------------*/
#include "contiki-conf.h"
#include "dev/watchdog.h"
#include "sys/process.h"
#include "sys/energest.h"
#include "net/netstack.h"
#include "net/packetbuf.h"
#include "net/rime/rimestats.h"
#include "rf-core/rf-core.h"
#include "ti-lib.h"
/*---------------------------------------------------------------------------*/
/* RF core and RF HAL API */
#include "hw_rfc_dbell.h"
#include "hw_rfc_pwr.h"
/*---------------------------------------------------------------------------*/
/* RF Core Mailbox API */
#include "rf-core/api/mailbox.h"
#include "rf-core/api/common_cmd.h"
#include "rf-core/api/ble_cmd.h"
#include "rf-core/api/ieee_cmd.h"
#include "rf-core/api/data_entry.h"
#include "rf-core/api/ble_mailbox.h"
#include "rf-core/api/ieee_mailbox.h"
#include "rf-core/api/prop_mailbox.h"
#include "rf-core/api/prop_cmd.h"
/*---------------------------------------------------------------------------*/
#include <stdint.h>
#include <stdbool.h>
#include <stdio.h>
#include <string.h>
/*---------------------------------------------------------------------------*/
#define DEBUG 0
#if DEBUG
#define PRINTF(...) printf(__VA_ARGS__)
#else
#define PRINTF(...)
#endif
/*---------------------------------------------------------------------------*/
#ifdef __GNUC__
#define CC_ALIGN_ATTR(n) __attribute__ ((aligned(n)))
#else
#define CC_ALIGN_ATTR(n)
#endif
/*---------------------------------------------------------------------------*/
#ifdef RF_CORE_CONF_DEBUG_CRC
#define RF_CORE_DEBUG_CRC RF_CORE_CONF_DEBUG_CRC
#else
#define RF_CORE_DEBUG_CRC DEBUG
#endif
/*---------------------------------------------------------------------------*/
/* RF interrupts */
#define RX_FRAME_IRQ IRQ_RX_ENTRY_DONE
#define ERROR_IRQ IRQ_INTERNAL_ERROR
#define RX_NOK_IRQ IRQ_RX_NOK
/* Those IRQs are enabled all the time */
#if RF_CORE_DEBUG_CRC
#define ENABLED_IRQS (RX_FRAME_IRQ | ERROR_IRQ | RX_NOK_IRQ)
#else
#define ENABLED_IRQS (RX_FRAME_IRQ | ERROR_IRQ)
#endif
#define cc26xx_rf_cpe0_isr RFCCPE0IntHandler
#define cc26xx_rf_cpe1_isr RFCCPE1IntHandler
/*---------------------------------------------------------------------------*/
/* Remember the last Radio Op issued to the radio */
static rfc_radioOp_t *last_radio_op = NULL;
/*---------------------------------------------------------------------------*/
/* A struct holding pointers to the primary mode's abort() and restore() */
static const rf_core_primary_mode_t *primary_mode = NULL;
/*---------------------------------------------------------------------------*/
PROCESS(rf_core_process, "CC13xx / CC26xx RF driver");
/*---------------------------------------------------------------------------*/
#define RF_CORE_CLOCKS_MASK (RFC_PWR_PWMCLKEN_RFC_M | RFC_PWR_PWMCLKEN_CPE_M \
| RFC_PWR_PWMCLKEN_CPERAM_M)
/*---------------------------------------------------------------------------*/
uint8_t
rf_core_is_accessible()
{
if(ti_lib_prcm_rf_ready() &&
ti_lib_prcm_power_domain_status(PRCM_DOMAIN_RFCORE) ==
PRCM_DOMAIN_POWER_ON) {
return RF_CORE_ACCESSIBLE;
}
return RF_CORE_NOT_ACCESSIBLE;
}
/*---------------------------------------------------------------------------*/
uint_fast8_t
rf_core_send_cmd(uint32_t cmd, uint32_t *status)
{
uint32_t timeout_count = 0;
bool interrupts_disabled;
bool is_radio_op = false;
/* If cmd is 4-byte aligned, then it's a radio OP. Clear the status field */
if((cmd & 0x03) == 0) {
is_radio_op = true;
((rfc_radioOp_t *)cmd)->status = RF_CORE_RADIO_OP_STATUS_IDLE;
}
/*
* Make sure ContikiMAC doesn't turn us off from within an interrupt while
* we are accessing RF Core registers
*/
interrupts_disabled = ti_lib_int_master_disable();
if(!rf_core_is_accessible()) {
PRINTF("rf_core_send_cmd: RF was off\n");
if(!interrupts_disabled) {
ti_lib_int_master_enable();
}
return RF_CORE_CMD_ERROR;
}
if(is_radio_op) {
uint16_t command_no = ((rfc_radioOp_t *)cmd)->commandNo;
if((command_no & RF_CORE_COMMAND_PROTOCOL_MASK) != RF_CORE_COMMAND_PROTOCOL_COMMON &&
(command_no & RF_CORE_COMMAND_TYPE_MASK) == RF_CORE_COMMAND_TYPE_RADIO_OP) {
last_radio_op = (rfc_radioOp_t *)cmd;
}
}
HWREG(RFC_DBELL_BASE + RFC_DBELL_O_CMDR) = cmd;
do {
*status = HWREG(RFC_DBELL_BASE + RFC_DBELL_O_CMDSTA);
if(++timeout_count > 50000) {
PRINTF("rf_core_send_cmd: 0x%08lx Timeout\n", cmd);
if(!interrupts_disabled) {
ti_lib_int_master_enable();
}
return RF_CORE_CMD_ERROR;
}
} while(*status == RF_CORE_CMDSTA_PENDING);
if(!interrupts_disabled) {
ti_lib_int_master_enable();
}
/*
* If we reach here the command is no longer pending. It is either completed
* successfully or with error
*/
return (*status & RF_CORE_CMDSTA_RESULT_MASK) == RF_CORE_CMDSTA_DONE;
}
/*---------------------------------------------------------------------------*/
uint_fast8_t
rf_core_wait_cmd_done(void *cmd)
{
volatile rfc_radioOp_t *command = (rfc_radioOp_t *)cmd;
uint32_t timeout_cnt = 0;
/*
* 0xn4nn=DONE, 0x0400=DONE_OK while all other "DONE" values means done
* but with some kind of error (ref. "Common radio operation status codes")
*/
do {
if(++timeout_cnt > 500000) {
return RF_CORE_CMD_ERROR;
}
} while((command->status & RF_CORE_RADIO_OP_MASKED_STATUS)
!= RF_CORE_RADIO_OP_MASKED_STATUS_DONE);
return (command->status & RF_CORE_RADIO_OP_MASKED_STATUS)
== RF_CORE_RADIO_OP_STATUS_DONE_OK;
}
/*---------------------------------------------------------------------------*/
int
rf_core_power_up()
{
uint32_t cmd_status;
bool interrupts_disabled = ti_lib_int_master_disable();
ti_lib_int_pend_clear(INT_RF_CPE0);
ti_lib_int_pend_clear(INT_RF_CPE1);
ti_lib_int_disable(INT_RF_CPE0);
ti_lib_int_disable(INT_RF_CPE1);
/* Enable RF Core power domain */
ti_lib_prcm_power_domain_on(PRCM_DOMAIN_RFCORE);
while(ti_lib_prcm_power_domain_status(PRCM_DOMAIN_RFCORE)
!= PRCM_DOMAIN_POWER_ON);
ti_lib_prcm_domain_enable(PRCM_DOMAIN_RFCORE);
ti_lib_prcm_load_set();
while(!ti_lib_prcm_load_get());
while(!rf_core_is_accessible()) {
PRINTF("rf_core_power_up: Not ready\n");
}
HWREG(RFC_DBELL_NONBUF_BASE + RFC_DBELL_O_RFCPEIFG) = 0x0;
HWREG(RFC_DBELL_NONBUF_BASE + RFC_DBELL_O_RFCPEIEN) = 0x0;
ti_lib_int_enable(INT_RF_CPE0);
ti_lib_int_enable(INT_RF_CPE1);
if(!interrupts_disabled) {
ti_lib_int_master_enable();
}
/* Let CPE boot */
HWREG(RFC_PWR_NONBUF_BASE + RFC_PWR_O_PWMCLKEN) = RF_CORE_CLOCKS_MASK;
/* Send ping (to verify RFCore is ready and alive) */
if(rf_core_send_cmd(CMDR_DIR_CMD(CMD_PING), &cmd_status) != RF_CORE_CMD_OK) {
PRINTF("rf_core_power_up: CMD_PING fail, CMDSTA=0x%08lx\n", cmd_status);
return RF_CORE_CMD_ERROR;
}
return RF_CORE_CMD_OK;
}
/*---------------------------------------------------------------------------*/
void
rf_core_power_down()
{
bool interrupts_disabled = ti_lib_int_master_disable();
ti_lib_int_disable(INT_RF_CPE0);
ti_lib_int_disable(INT_RF_CPE1);
if(rf_core_is_accessible()) {
HWREG(RFC_DBELL_NONBUF_BASE + RFC_DBELL_O_RFCPEIFG) = 0x0;
HWREG(RFC_DBELL_NONBUF_BASE + RFC_DBELL_O_RFCPEIEN) = 0x0;
}
/* Shut down the RFCORE clock domain in the MCU VD */
ti_lib_prcm_domain_disable(PRCM_DOMAIN_RFCORE);
ti_lib_prcm_load_set();
while(!ti_lib_prcm_load_get());
/* Turn off RFCORE PD */
ti_lib_prcm_power_domain_off(PRCM_DOMAIN_RFCORE);
while(ti_lib_prcm_power_domain_status(PRCM_DOMAIN_RFCORE)
!= PRCM_DOMAIN_POWER_OFF);
ti_lib_int_pend_clear(INT_RF_CPE0);
ti_lib_int_pend_clear(INT_RF_CPE1);
ti_lib_int_enable(INT_RF_CPE0);
ti_lib_int_enable(INT_RF_CPE1);
if(!interrupts_disabled) {
ti_lib_int_master_enable();
}
}
/*---------------------------------------------------------------------------*/
uint8_t
rf_core_set_modesel()
{
uint8_t rv = RF_CORE_CMD_ERROR;
if(ti_lib_chipinfo_chip_family_is_cc26xx()) {
if(ti_lib_chipinfo_supports_ble() == true &&
ti_lib_chipinfo_supports_ieee_802_15_4() == true) {
/* CC2650 */
HWREG(PRCM_BASE + PRCM_O_RFCMODESEL) = PRCM_RFCMODESEL_CURR_MODE5;
rv = RF_CORE_CMD_OK;
} else if(ti_lib_chipinfo_supports_ble() == false &&
ti_lib_chipinfo_supports_ieee_802_15_4() == true) {
/* CC2630 */
HWREG(PRCM_BASE + PRCM_O_RFCMODESEL) = PRCM_RFCMODESEL_CURR_MODE2;
rv = RF_CORE_CMD_OK;
}
} else if(ti_lib_chipinfo_chip_family_is_cc13xx()) {
if(ti_lib_chipinfo_supports_ble() == false &&
ti_lib_chipinfo_supports_ieee_802_15_4() == false) {
/* CC1310 */
HWREG(PRCM_BASE + PRCM_O_RFCMODESEL) = PRCM_RFCMODESEL_CURR_MODE3;
rv = RF_CORE_CMD_OK;
}
}
return rv;
}
/*---------------------------------------------------------------------------*/
uint8_t
rf_core_start_rat()
{
uint32_t cmd_status;
/* Start radio timer (RAT) */
if(rf_core_send_cmd(CMDR_DIR_CMD(CMD_START_RAT), &cmd_status)
!= RF_CORE_CMD_OK) {
PRINTF("rf_core_apply_patches: START_RAT fail, CMDSTA=0x%08lx\n",
cmd_status);
return RF_CORE_CMD_ERROR;
}
return RF_CORE_CMD_OK;
}
/*---------------------------------------------------------------------------*/
uint8_t
rf_core_boot()
{
if(rf_core_power_up() != RF_CORE_CMD_OK) {
PRINTF("rf_core_boot: rf_core_power_up() failed\n");
rf_core_power_down();
return RF_CORE_CMD_ERROR;
}
if(rf_core_start_rat() != RF_CORE_CMD_OK) {
PRINTF("rf_core_boot: rf_core_start_rat() failed\n");
rf_core_power_down();
return RF_CORE_CMD_ERROR;
}
return RF_CORE_CMD_OK;
}
/*---------------------------------------------------------------------------*/
void
rf_core_setup_interrupts()
{
bool interrupts_disabled;
/* We are already turned on by the caller, so this should not happen */
if(!rf_core_is_accessible()) {
PRINTF("setup_interrupts: No access\n");
return;
}
/* Disable interrupts */
interrupts_disabled = ti_lib_int_master_disable();
/* Set all interrupt channels to CPE0 channel, error to CPE1 */
HWREG(RFC_DBELL_NONBUF_BASE + RFC_DBELL_O_RFCPEISL) = ERROR_IRQ;
/* Acknowledge configured interrupts */
HWREG(RFC_DBELL_NONBUF_BASE + RFC_DBELL_O_RFCPEIEN) = ENABLED_IRQS;
/* Clear interrupt flags, active low clear(?) */
HWREG(RFC_DBELL_NONBUF_BASE + RFC_DBELL_O_RFCPEIFG) = 0x0;
ti_lib_int_pend_clear(INT_RF_CPE0);
ti_lib_int_pend_clear(INT_RF_CPE1);
ti_lib_int_enable(INT_RF_CPE0);
ti_lib_int_enable(INT_RF_CPE1);
if(!interrupts_disabled) {
ti_lib_int_master_enable();
}
}
/*---------------------------------------------------------------------------*/
void
rf_core_cmd_done_en()
{
HWREG(RFC_DBELL_NONBUF_BASE + RFC_DBELL_O_RFCPEIFG) = ENABLED_IRQS;
HWREG(RFC_DBELL_NONBUF_BASE + RFC_DBELL_O_RFCPEIEN) = ENABLED_IRQS +
IRQ_LAST_COMMAND_DONE;
}
/*---------------------------------------------------------------------------*/
void
rf_core_cmd_done_dis()
{
HWREG(RFC_DBELL_NONBUF_BASE + RFC_DBELL_O_RFCPEIEN) = ENABLED_IRQS;
}
/*---------------------------------------------------------------------------*/
rfc_radioOp_t *
rf_core_get_last_radio_op()
{
return last_radio_op;
}
/*---------------------------------------------------------------------------*/
void
rf_core_init_radio_op(rfc_radioOp_t *op, uint16_t len, uint16_t command)
{
memset(op, 0, len);
op->commandNo = command;
op->condition.rule = COND_NEVER;
}
/*---------------------------------------------------------------------------*/
void
rf_core_primary_mode_register(const rf_core_primary_mode_t *mode)
{
primary_mode = mode;
}
/*---------------------------------------------------------------------------*/
void
rf_core_primary_mode_abort()
{
if(primary_mode) {
if(primary_mode->abort) {
primary_mode->abort();
}
}
}
/*---------------------------------------------------------------------------*/
uint8_t
rf_core_primary_mode_restore()
{
if(primary_mode) {
if(primary_mode->restore) {
return primary_mode->restore();
}
}
return RF_CORE_CMD_ERROR;
}
/*---------------------------------------------------------------------------*/
PROCESS_THREAD(rf_core_process, ev, data)
{
int len;
PROCESS_BEGIN();
while(1) {
PROCESS_YIELD_UNTIL(ev == PROCESS_EVENT_POLL);
do {
watchdog_periodic();
packetbuf_clear();
len = NETSTACK_RADIO.read(packetbuf_dataptr(), PACKETBUF_SIZE);
if(len > 0) {
packetbuf_set_datalen(len);
NETSTACK_RDC.input();
}
} while(len > 0);
}
PROCESS_END();
}
/*---------------------------------------------------------------------------*/
static void
rx_nok_isr(void)
{
RIMESTATS_ADD(badcrc);
PRINTF("RF: Bad CRC\n");
}
/*---------------------------------------------------------------------------*/
void
cc26xx_rf_cpe1_isr(void)
{
ENERGEST_ON(ENERGEST_TYPE_IRQ);
PRINTF("RF Error\n");
if(!rf_core_is_accessible()) {
if(rf_core_power_up() != RF_CORE_CMD_OK) {
return;
}
}
/* Clear interrupt flags */
HWREG(RFC_DBELL_NONBUF_BASE + RFC_DBELL_O_RFCPEIFG) = 0x0;
ENERGEST_OFF(ENERGEST_TYPE_IRQ);
}
/*---------------------------------------------------------------------------*/
void
cc26xx_rf_cpe0_isr(void)
{
ENERGEST_ON(ENERGEST_TYPE_IRQ);
if(!rf_core_is_accessible()) {
printf("RF ISR called but RF not ready... PANIC!!\n");
if(rf_core_power_up() != RF_CORE_CMD_OK) {
PRINTF("rf_core_power_up() failed\n");
return;
}
}
ti_lib_int_master_disable();
if(HWREG(RFC_DBELL_NONBUF_BASE + RFC_DBELL_O_RFCPEIFG) & RX_FRAME_IRQ) {
process_poll(&rf_core_process);
}
if(RF_CORE_DEBUG_CRC) {
if(HWREG(RFC_DBELL_NONBUF_BASE + RFC_DBELL_O_RFCPEIFG) & RX_NOK_IRQ) {
rx_nok_isr();
}
}
/* Clear interrupt flags */
HWREG(RFC_DBELL_NONBUF_BASE + RFC_DBELL_O_RFCPEIFG) = 0x0;
ti_lib_int_master_enable();
ENERGEST_OFF(ENERGEST_TYPE_IRQ);
}
/*---------------------------------------------------------------------------*/
/** @} */

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/*
* Copyright (c) 2015, Texas Instruments Incorporated - http://www.ti.com/
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. Neither the name of the copyright holder nor the names of its
* contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
* OF THE POSSIBILITY OF SUCH DAMAGE.
*/
/*---------------------------------------------------------------------------*/
/**
* \addtogroup cc26xx
* @{
*
* \defgroup rf-core CC13xx/CC26xx RF core
*
* Different flavours of chips of the CC13xx/CC26xx family have different
* radio capability. For example, the CC2650 can operate in IEEE 802.15.4 mode
* at 2.4GHz, but it can also operate in BLE mode. The CC1310 only supports
* sub-ghz mode.
*
* However, there are many radio functionalities that are identical across
* all chips. The rf-core driver provides support for this common functionality
*
* @{
*
* \file
* Header file for the CC13xx/CC26xx RF core driver
*/
/*---------------------------------------------------------------------------*/
#ifndef RF_CORE_H_
#define RF_CORE_H_
/*---------------------------------------------------------------------------*/
#include "contiki-conf.h"
#include "rf-core/api/common_cmd.h"
#include <stdint.h>
#include <stdbool.h>
/*---------------------------------------------------------------------------*/
/* The channel to use in IEEE or prop mode. */
#ifdef RF_CORE_CONF_CHANNEL
#define RF_CORE_CHANNEL RF_CORE_CONF_CHANNEL
#else
#define RF_CORE_CHANNEL 25
#endif /* RF_CORE_CONF_IEEE_MODE_CHANNEL */
/*---------------------------------------------------------------------------*/
#define RF_CORE_CMD_ERROR 0
#define RF_CORE_CMD_OK 1
/*---------------------------------------------------------------------------*/
/**
* \brief A data strcuture representing the radio's primary mode of operation
*
* The CC13xx / CC26xx radio supports up to potentially 3 modes: IEEE, Prop and
* BLE. Within Contiki, we assume that the radio is by default in one of IEEE
* or Prop in order to support standard 6LoWPAN / .15.4 operation. The BLE
* mode interrupts this so called "primary" mode in order to send BLE adv
* messages. Once BLE is done advertising, we need to be able to restore the
* previous .15.4 mode. Unfortunately, the only way this can be done with
* NETSTACK_RADIO API is by fully power-cycling the radio, which is something
* we do not want to do.
*
* Thus, we declare a secondary data structure for primary mode drivers (IEEE
* or Prop). We use this data structure to issue "soft off" and "back on"
* commands. Soft off in this context means stopping RX (e.g. the respective
* IEEE RX operation), but without shutting down the RF core (which is what
* NETSTACK_RADIO.off() would have done). We then remember what mode we were
* using in order to be able to re-enter RX mode for this mode.
*
* A NETSTACK_RADIO driver will declare those two functions somewhere within
* its module of implementation. During its init() routine, it will notify
* the RF core module so that the latter can abort and restore operations.
*/
typedef struct rf_core_primary_mode_s {
/**
* \brief A pointer to a function used to abort the current radio op
*/
void (*abort)(void);
/**
* \brief A pointer to a function that will restore the previous radio op
* \return RF_CORE_CMD_OK or RF_CORE_CMD_ERROR
*/
uint8_t (*restore)(void);
} rf_core_primary_mode_t;
/*---------------------------------------------------------------------------*/
/* RF Command status constants - Correspond to values in the CMDSTA register */
#define RF_CORE_CMDSTA_PENDING 0x00
#define RF_CORE_CMDSTA_DONE 0x01
#define RF_CORE_CMDSTA_ILLEGAL_PTR 0x81
#define RF_CORE_CMDSTA_UNKNOWN_CMD 0x82
#define RF_CORE_CMDSTA_UNKNOWN_DIR_CMD 0x83
#define RF_CORE_CMDSTA_CONTEXT_ERR 0x85
#define RF_CORE_CMDSTA_SCHEDULING_ERR 0x86
#define RF_CORE_CMDSTA_PAR_ERR 0x87
#define RF_CORE_CMDSTA_QUEUE_ERR 0x88
#define RF_CORE_CMDSTA_QUEUE_BUSY 0x89
/* Status values starting with 0x8 correspond to errors */
#define RF_CORE_CMDSTA_ERR_MASK 0x80
/* CMDSTA is 32-bits. Return value in bits 7:0 */
#define RF_CORE_CMDSTA_RESULT_MASK 0xFF
#define RF_CORE_RADIO_OP_STATUS_IDLE 0x0000
/*---------------------------------------------------------------------------*/
#define RF_CORE_NOT_ACCESSIBLE 0x00
#define RF_CORE_ACCESSIBLE 0x01
/*---------------------------------------------------------------------------*/
/* RF Radio Op status constants. Field 'status' in Radio Op command struct */
#define RF_CORE_RADIO_OP_STATUS_IDLE 0x0000
#define RF_CORE_RADIO_OP_STATUS_PENDING 0x0001
#define RF_CORE_RADIO_OP_STATUS_ACTIVE 0x0002
#define RF_CORE_RADIO_OP_STATUS_SKIPPED 0x0003
#define RF_CORE_RADIO_OP_STATUS_DONE_OK 0x0400
#define RF_CORE_RADIO_OP_STATUS_DONE_COUNTDOWN 0x0401
#define RF_CORE_RADIO_OP_STATUS_DONE_RXERR 0x0402
#define RF_CORE_RADIO_OP_STATUS_DONE_TIMEOUT 0x0403
#define RF_CORE_RADIO_OP_STATUS_DONE_STOPPED 0x0404
#define RF_CORE_RADIO_OP_STATUS_DONE_ABORT 0x0405
#define RF_CORE_RADIO_OP_STATUS_ERROR_PAST_START 0x0800
#define RF_CORE_RADIO_OP_STATUS_ERROR_START_TRIG 0x0801
#define RF_CORE_RADIO_OP_STATUS_ERROR_CONDITION 0x0802
#define RF_CORE_RADIO_OP_STATUS_ERROR_PAR 0x0803
#define RF_CORE_RADIO_OP_STATUS_ERROR_POINTER 0x0804
#define RF_CORE_RADIO_OP_STATUS_ERROR_CMDID 0x0805
#define RF_CORE_RADIO_OP_STATUS_ERROR_NO_SETUP 0x0807
#define RF_CORE_RADIO_OP_STATUS_ERROR_NO_FS 0x0808
#define RF_CORE_RADIO_OP_STATUS_ERROR_SYNTH_PROG 0x0809
/* Additional Op status values for IEEE mode */
#define RF_CORE_RADIO_OP_STATUS_IEEE_SUSPENDED 0x2001
#define RF_CORE_RADIO_OP_STATUS_IEEE_DONE_OK 0x2400
#define RF_CORE_RADIO_OP_STATUS_IEEE_DONE_BUSY 0x2401
#define RF_CORE_RADIO_OP_STATUS_IEEE_DONE_STOPPED 0x2402
#define RF_CORE_RADIO_OP_STATUS_IEEE_DONE_ACK 0x2403
#define RF_CORE_RADIO_OP_STATUS_IEEE_DONE_ACKPEND 0x2404
#define RF_CORE_RADIO_OP_STATUS_IEEE_DONE_TIMEOUT 0x2405
#define RF_CORE_RADIO_OP_STATUS_IEEE_DONE_BGEND 0x2406
#define RF_CORE_RADIO_OP_STATUS_IEEE_DONE_ABORT 0x2407
#define RF_CORE_RADIO_OP_STATUS_ERROR_WRONG_BG 0x0806
#define RF_CORE_RADIO_OP_STATUS_IEEE_ERROR_PAR 0x2800
#define RF_CORE_RADIO_OP_STATUS_IEEE_ERROR_NO_SETUP 0x2801
#define RF_CORE_RADIO_OP_STATUS_IEEE_ERROR_NO_FS 0x2802
#define RF_CORE_RADIO_OP_STATUS_IEEE_ERROR_SYNTH_PROG 0x2803
#define RF_CORE_RADIO_OP_STATUS_IEEE_ERROR_RXOVF 0x2804
#define RF_CORE_RADIO_OP_STATUS_IEEE_ERROR_TXUNF 0x2805
/* Op status values for BLE mode */
#define RF_CORE_RADIO_OP_STATUS_BLE_DONE_OK 0x1400
#define RF_CORE_RADIO_OP_STATUS_BLE_DONE_RXTIMEOUT 0x1401
#define RF_CORE_RADIO_OP_STATUS_BLE_DONE_NOSYNC 0x1402
#define RF_CORE_RADIO_OP_STATUS_BLE_DONE_RXERR 0x1403
#define RF_CORE_RADIO_OP_STATUS_BLE_DONE_CONNECT 0x1404
#define RF_CORE_RADIO_OP_STATUS_BLE_DONE_MAXNACK 0x1405
#define RF_CORE_RADIO_OP_STATUS_BLE_DONE_ENDED 0x1406
#define RF_CORE_RADIO_OP_STATUS_BLE_DONE_ABORT 0x1407
#define RF_CORE_RADIO_OP_STATUS_BLE_DONE_STOPPED 0x1408
#define RF_CORE_RADIO_OP_STATUS_BLE_ERROR_PAR 0x1800
#define RF_CORE_RADIO_OP_STATUS_BLE_ERROR_RXBUF 0x1801
#define RF_CORE_RADIO_OP_STATUS_BLE_ERROR_NO_SETUP 0x1802
#define RF_CORE_RADIO_OP_STATUS_BLE_ERROR_NO_FS 0x1803
#define RF_CORE_RADIO_OP_STATUS_BLE_ERROR_SYNTH_PROG 0x1804
#define RF_CORE_RADIO_OP_STATUS_BLE_ERROR_RXOVF 0x1805
#define RF_CORE_RADIO_OP_STATUS_BLE_ERROR_TXUNF 0x1806
/* Op status values for proprietary mode */
#define RF_CORE_RADIO_OP_STATUS_PROP_DONE_OK 0x3400
#define RF_CORE_RADIO_OP_STATUS_PROP_DONE_RXTIMEOUT 0x3401
#define RF_CORE_RADIO_OP_STATUS_PROP_DONE_BREAK 0x3402
#define RF_CORE_RADIO_OP_STATUS_PROP_DONE_ENDED 0x3403
#define RF_CORE_RADIO_OP_STATUS_PROP_DONE_STOPPED 0x3404
#define RF_CORE_RADIO_OP_STATUS_PROP_DONE_ABORT 0x3405
#define RF_CORE_RADIO_OP_STATUS_PROP_DONE_RXERR 0x3406
#define RF_CORE_RADIO_OP_STATUS_PROP_DONE_IDLE 0x3407
#define RF_CORE_RADIO_OP_STATUS_PROP_DONE_BUSY 0x3408
#define RF_CORE_RADIO_OP_STATUS_PROP_DONE_IDLETIMEOUT 0x3409
#define RF_CORE_RADIO_OP_STATUS_PROP_DONE_BUSYTIMEOUT 0x340A
#define RF_CORE_RADIO_OP_STATUS_PROP_ERROR_PAR 0x3800
#define RF_CORE_RADIO_OP_STATUS_PROP_ERROR_RXBUF 0x3801
#define RF_CORE_RADIO_OP_STATUS_PROP_ERROR_RXFULL 0x3802
#define RF_CORE_RADIO_OP_STATUS_PROP_ERROR_NO_SETUP 0x3803
#define RF_CORE_RADIO_OP_STATUS_PROP_ERROR_NO_FS 0x3804
#define RF_CORE_RADIO_OP_STATUS_PROP_ERROR_RXOVF 0x3805
#define RF_CORE_RADIO_OP_STATUS_PROP_ERROR_TXUNF 0x3806
/* Bits 15:12 signify the protocol */
#define RF_CORE_RADIO_OP_STATUS_PROTO_MASK 0xF000
#define RF_CORE_RADIO_OP_STATUS_PROTO_GENERIC 0x0000
#define RF_CORE_RADIO_OP_STATUS_PROTO_BLE 0x1000
#define RF_CORE_RADIO_OP_STATUS_PROTO_IEEE 0x2000
#define RF_CORE_RADIO_OP_STATUS_PROTO_PROP 0x3000
/* Bits 11:10 signify Running / Done OK / Done with error */
#define RF_CORE_RADIO_OP_MASKED_STATUS 0x0C00
#define RF_CORE_RADIO_OP_MASKED_STATUS_RUNNING 0x0000
#define RF_CORE_RADIO_OP_MASKED_STATUS_DONE 0x0400
#define RF_CORE_RADIO_OP_MASKED_STATUS_ERROR 0x0800
/*---------------------------------------------------------------------------*/
/* Command Types */
#define RF_CORE_COMMAND_TYPE_MASK 0x0C00
#define RF_CORE_COMMAND_TYPE_IMMEDIATE 0x0000
#define RF_CORE_COMMAND_TYPE_RADIO_OP 0x0800
#define RF_CORE_COMMAND_TYPE_IEEE_BG_RADIO_OP 0x0800
#define RF_CORE_COMMAND_TYPE_IEEE_FG_RADIO_OP 0x0C00
#define RF_CORE_COMMAND_PROTOCOL_MASK 0x3000
#define RF_CORE_COMMAND_PROTOCOL_COMMON 0x0000
#define RF_CORE_COMMAND_PROTOCOL_BLE 0x1000
#define RF_CORE_COMMAND_PROTOCOL_IEEE 0x2000
#define RF_CORE_COMMAND_PROTOCOL_PROP 0x3000
/*---------------------------------------------------------------------------*/
/* Make the main driver process visible to mode drivers */
PROCESS_NAME(rf_core_process);
/*---------------------------------------------------------------------------*/
/**
* \brief Check whether the RF core is accessible
* \retval RF_CORE_ACCESSIBLE The core is powered and ready for access
* \retval RF_CORE_NOT_ACCESSIBLE The core is not ready
*
* If this function returns RF_CORE_NOT_ACCESSIBLE, rf_core_power_up() must be
* called before any attempt to access the core.
*/
uint8_t rf_core_is_accessible(void);
/**
* \brief Sends a command to the RF core.
*
* \param cmd The command value or a pointer to a command buffer
* \param status A pointer to a variable which will hold the status
* \return RF_CORE_CMD_OK or RF_CORE_CMD_ERROR
*
* This function supports all three types of command (Radio OP, immediate and
* direct)
*
* For immediate and Radio OPs, cmd is a pointer to the data structure
* containing the command and its parameters. This data structure must be
* 4-byte aligned.
*
* For direct commands, cmd contains the value of the command alongside its
* parameters. This value will be written to CMDSTA verbatim, so the command
* ID must be in the 16 high bits, and the 2 LS bits must be set to 01 by the
* caller.
*
* The caller is responsible of allocating and populating cmd for Radio OP and
* immediate commands
*
* The caller is responsible for allocating status
*
* For immediate commands and radio Ops, this function will set the command's
* status field to RF_CORE_RADIO_OP_STATUS_IDLE before sending it to the RF
*/
uint_fast8_t rf_core_send_cmd(uint32_t cmd, uint32_t *status);
/**
* \brief Block and wait for a Radio op to complete
* \param cmd A pointer to any command's structure
* \retval RF_CORE_CMD_OK the command completed with status _DONE_OK
* \retval RF_CORE_CMD_ERROR Timeout exceeded or the command completed with
* status _DONE_xxx (e.g. RF_CORE_RADIO_OP_STATUS_DONE_TIMEOUT)
*/
uint_fast8_t rf_core_wait_cmd_done(void *cmd);
/**
* \brief Turn on power to the RFC and boot it.
* \return RF_CORE_CMD_OK or RF_CORE_CMD_ERROR
*/
int rf_core_power_up(void);
/**
* \brief Disable RFCORE clock domain in the MCU VD and turn off the RFCORE PD
*/
void rf_core_power_down(void);
/**
* \brief Initialise RF APIs in the RF core
* \return RF_CORE_CMD_OK or RF_CORE_CMD_ERROR
*
* Depending on chip family and capability, this function will set the correct
* value to PRCM.RFCMODESEL
*/
uint8_t rf_core_set_modesel(void);
/**
* \brief Start the CM0 RAT
* \return RF_CORE_CMD_OK or RF_CORE_CMD_ERROR
*
* This function must be called each time the CM0 boots. The boot sequence
* can be performed automatically by calling rf_core_boot() if patches are not
* required. If patches are required then the patches must be applied after
* power up and before calling this function.
*/
uint8_t rf_core_start_rat(void);
/**
* \brief Boot the RF Core
* \return RF_CORE_CMD_OK or RF_CORE_CMD_ERROR
*
* This function will perform the CM0 boot sequence. It will first power it up
* and then start the RAT. If a patch is required, then the mode driver must
* not call this function and perform the sequence manually, applying patches
* after boot and before calling rf_core_start_rat().
*
* The function will return RF_CORE_CMD_ERROR if any of those steps fails. If
* the boot sequence fails to complete, the RF Core will be powered down.
*/
uint8_t rf_core_boot(void);
/**
* \brief Setup RF core interrupts
*/
void rf_core_setup_interrupts(void);
/**
* \brief Enable the LAST_CMD_DONE interrupt.
*
* This is used within TX routines in order to be able to sleep the CM3 and
* wake up after TX has finished
*
* \sa rf_core_cmd_done_dis()
*/
void rf_core_cmd_done_en(void);
/**
* \brief Disable the LAST_CMD_DONE interrupt.
*
* This is used within TX routines after TX has completed
*
* \sa rf_core_cmd_done_en()
*/
void rf_core_cmd_done_dis(void);
/**
* \brief Returns a pointer to the most recent proto-dependent Radio Op
* \return The pointer
*
* The RF Core driver will remember the most recent proto-dependent Radio OP
* issued, so that other modules can inspect its type and state at a subsequent
* stage. The assumption is that those commands will be issued by a function
* that will then return. The following commands will be "remembered"
*
* - All BLE Radio Ops (0x18nn)
* - All Prop Radio Ops (0x38nn)
* - IEEE BG Radio Ops (0x28nn)
*
* The following commands are assumed to be executed synchronously and will
* thus not be remembered by the core and not returned by this function:
*
* - Direct commands
* - Proto-independent commands (including Radio Ops and Immediate ones)
* - IEEE FG Radio Ops (0x2Cxx)
*
* This assumes that all commands will be sent to the radio using
* rf_core_send_cmd()
*/
rfc_radioOp_t *rf_core_get_last_radio_op(void);
/**
* \brief Prepare a buffer to host a Radio Op
* \param buf A pointer to the buffer that will host the Radio Op
* \param len The buffer's length
* \param command The command ID
*
* The caller is responsible to allocate the buffer
*
* This function will not check whether the buffer is large enough to hold the
* command. This is the caller's responsibility
*
* This function will wipe out the buffer's contents.
*/
void rf_core_init_radio_op(rfc_radioOp_t *buf, uint16_t len, uint16_t command);
/**
* \brief Register a primary mode for radio operation
* \param mode A pointer to the struct representing the mode
*
* A normal NESTACK_RADIO driver will normally register itself by calling
* this function during its own init().
*
* \sa rf_core_primary_mode_t
*/
void rf_core_primary_mode_register(const rf_core_primary_mode_t *mode);
/**
* \brief Abort the currently running primary radio op
*/
void rf_core_primary_mode_abort(void);
/**
* \brief Abort the currently running primary radio op
*/
uint8_t rf_core_primary_mode_restore(void);
/*---------------------------------------------------------------------------*/
#endif /* RF_CORE_H_ */
/*---------------------------------------------------------------------------*/
/**
* @}
* @}
*/

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/*
* Copyright (c) 2015, Texas Instruments Incorporated - http://www.ti.com/
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. Neither the name of the copyright holder nor the names of its
* contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
* OF THE POSSIBILITY OF SUCH DAMAGE.
*/
/*---------------------------------------------------------------------------*/
#include "rf-core/api/mailbox.h"
#include "rf-core/api/common_cmd.h"
#include "rf-core/api/prop_cmd.h"
/*---------------------------------------------------------------------------*/
/* Overrides for CMD_PROP_RADIO_DIV_SETUP */
uint32_t overrides[] =
{
/* override_synth.xml */
HW32_ARRAY_OVERRIDE(0x6088, 1),
(uint32_t)0x0000001A,
ADI_HALFREG_OVERRIDE(0, 61, 0xF, 0xD),
HW32_ARRAY_OVERRIDE(0x4038, 1),
(uint32_t)0x0000003A,
HW_REG_OVERRIDE(0x4020, 0x7F00),
HW_REG_OVERRIDE(0x4064, 0x0040),
(uint32_t)0x684A3,
(uint32_t)0xC0040141,
(uint32_t)0x0533B107,
(uint32_t)0xA480583,
(uint32_t)0x7AB80603,
ADI_REG_OVERRIDE(1, 4, 0x1F),
ADI_HALFREG_OVERRIDE(1, 7, 0x4, 0x4),
HW_REG_OVERRIDE(0x6084, 0x35F1),
(uint32_t)0x00038883,
(uint32_t)0x00FB88A3,
/* TX power override */
ADI_REG_OVERRIDE(0, 12, 0xF9),
/* Overrides for CRC16 functionality */
(uint32_t)0x943,
(uint32_t)0x963,
(uint32_t)0xFFFFFFFF,
};
/*---------------------------------------------------------------------------*/
/* CMD_PROP_RADIO_DIV_SETUP */
rfc_CMD_PROP_RADIO_DIV_SETUP_t smartrf_settings_cmd_prop_radio_div_setup =
{
.commandNo = 0x3807,
.status = 0x0000,
.pNextOp = 0,
.startTime = 0x00000000,
.startTrigger.triggerType = 0x0,
.startTrigger.bEnaCmd = 0x0,
.startTrigger.triggerNo = 0x0,
.startTrigger.pastTrig = 0x0,
.condition.rule = 0x1,
.condition.nSkip = 0x0,
.modulation.modType = 0x1,
.modulation.deviation = 0x64,
.symbolRate.preScale = 0xf,
.symbolRate.rateWord = 0x8000,
.rxBw = 0x24,
.preamConf.nPreamBytes = 0x3,
.preamConf.preamMode = 0x0,
.formatConf.nSwBits = 0x18,
.formatConf.bBitReversal = 0x0,
.formatConf.bMsbFirst = 0x1,
.formatConf.fecMode = 0x0,
/* 7: .4g mode with dynamic whitening and CRC choice */
.formatConf.whitenMode = 0x7,
.config.frontEndMode = 0x0, /* Differential mode */
.config.biasMode = 0x1, /* External bias*/
.config.bNoFsPowerUp = 0x0,
.txPower = 0x00, /* Driver sets correct value */
.pRegOverride = overrides,
.intFreq = 0x8000,
.centerFreq = 868,
.loDivider = 0x05,
};
/*---------------------------------------------------------------------------*/
/* CMD_FS */
rfc_CMD_FS_t smartrf_settings_cmd_fs =
{
.commandNo = 0x0803,
.status = 0x0000,
.pNextOp = 0,
.startTime = 0x00000000,
.startTrigger.triggerType = 0x0,
.startTrigger.bEnaCmd = 0x0,
.startTrigger.triggerNo = 0x0,
.startTrigger.pastTrig = 0x0,
.condition.rule = 0x1,
.condition.nSkip = 0x0,
.frequency = 868,
.fractFreq = 0x0000,
.synthConf.bTxMode = 0x0,
.synthConf.refFreq = 0x0,
.__dummy0 = 0x00,
.midPrecal = 0x00,
.ktPrecal = 0x00,
.tdcPrecal = 0x0000,
};
/*---------------------------------------------------------------------------*/
/* CMD_PROP_TX_ADV */
rfc_CMD_PROP_TX_ADV_t smartrf_settings_cmd_prop_tx_adv =
{
.commandNo = 0x3803,
.status = 0x0000,
.pNextOp = 0,
.startTime = 0x00000000,
.startTrigger.triggerType = 0x0,
.startTrigger.bEnaCmd = 0x0,
.startTrigger.triggerNo = 0x0,
.startTrigger.pastTrig = 0x0,
.condition.rule = 0x1,
.condition.nSkip = 0x0,
.pktConf.bFsOff = 0x0,
.pktConf.bUseCrc = 0x1,
.pktConf.bCrcIncSw = 0x0, /* .4g mode */
.pktConf.bCrcIncHdr = 0x0, /* .4g mode */
.numHdrBits = 0x10 /* 16: .4g mode */,
.pktLen = 0x0000,
.startConf.bExtTxTrig = 0x0,
.startConf.inputMode = 0x0,
.startConf.source = 0x0,
.preTrigger.triggerType = TRIG_REL_START,
.preTrigger.bEnaCmd = 0x0,
.preTrigger.triggerNo = 0x0,
.preTrigger.pastTrig = 0x1,
.preTime = 0x00000000,
.syncWord = 0x0055904e,
.pPkt = 0,
};
/*---------------------------------------------------------------------------*/
/* CMD_PROP_RX_ADV */
rfc_CMD_PROP_RX_ADV_t smartrf_settings_cmd_prop_rx_adv =
{
.commandNo = 0x3804,
.status = 0x0000,
.pNextOp = 0,
.startTime = 0x00000000,
.startTrigger.triggerType = 0x0,
.startTrigger.bEnaCmd = 0x0,
.startTrigger.triggerNo = 0x0,
.startTrigger.pastTrig = 0x0,
.condition.rule = 0x1,
.condition.nSkip = 0x0,
.pktConf.bFsOff = 0x0,
.pktConf.bRepeatOk = 0x1,
.pktConf.bRepeatNok = 0x1,
.pktConf.bUseCrc = 0x1,
.pktConf.bCrcIncSw = 0x0, /* .4g mode */
.pktConf.bCrcIncHdr = 0x0, /* .4g mode */
.pktConf.endType = 0x0,
.pktConf.filterOp = 0x1,
.rxConf.bAutoFlushIgnored = 0x1,
.rxConf.bAutoFlushCrcErr = 0x1,
.rxConf.bIncludeHdr = 0x0,
.rxConf.bIncludeCrc = 0x0,
.rxConf.bAppendRssi = 0x1,
.rxConf.bAppendTimestamp = 0x0,
.rxConf.bAppendStatus = 0x1,
.syncWord0 = 0x0055904e,
.syncWord1 = 0x00000000,
.maxPktLen = 0x0000, /* To be populated by the driver. */
.hdrConf.numHdrBits = 0x10, /* 16: .4g mode */
.hdrConf.lenPos = 0x0, /* .4g mode */
.hdrConf.numLenBits = 0x0B, /* 11 = 0x0B .4g mode */
.addrConf.addrType = 0x0,
.addrConf.addrSize = 0x0,
.addrConf.addrPos = 0x0,
.addrConf.numAddr = 0x0,
.lenOffset = -4, /* .4g mode */
.endTrigger.triggerType = TRIG_NEVER,
.endTrigger.bEnaCmd = 0x0,
.endTrigger.triggerNo = 0x0,
.endTrigger.pastTrig = 0x0,
.endTime = 0x00000000,
.pAddr = 0,
.pQueue = 0,
.pOutput = 0,
};
/*---------------------------------------------------------------------------*/

50
cpu/cc26xx/cc26xx-model.h → cpu/cc26xx-cc13xx/rf-core/smartrf-settings.h
View File

@ -10,7 +10,6 @@
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* 3. Neither the name of the copyright holder nor the names of its
* contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
@ -29,46 +28,17 @@
* OF THE POSSIBILITY OF SUCH DAMAGE.
*/
/*---------------------------------------------------------------------------*/
/**
* \addtogroup cc26xx
* @{
*
* \defgroup cc26xx-models CC26xx models
*
* The CC26xx comes out in various flavours. Most notable within the context
* of this Contiki port: The CC2630 with IEEE (but no BLE) support and the
* CC2650 with IEEE and BLE support.
*
* This port supports both models and will automatically turn off the BLE code
* if the CC2630 is selected.
*
* @{
*/
/**
* \file
* Header file with definitions relating to various CC26xx variants
*/
#ifndef SMARTRF_SETTINGS_H_
#define SMARTRF_SETTINGS_H_
/*---------------------------------------------------------------------------*/
#ifndef CC26XX_MODEL_H_
#define CC26XX_MODEL_H_
#include "rf-core/api/mailbox.h"
#include "rf-core/api/common_cmd.h"
#include "rf-core/api/prop_cmd.h"
/*---------------------------------------------------------------------------*/
#include "contiki-conf.h"
extern rfc_CMD_PROP_RADIO_DIV_SETUP_t smartrf_settings_cmd_prop_radio_div_setup;
extern rfc_CMD_FS_t smartrf_settings_cmd_fs;
extern rfc_CMD_PROP_TX_ADV_t smartrf_settings_cmd_prop_tx_adv;
extern rfc_CMD_PROP_RX_ADV_t smartrf_settings_cmd_prop_rx_adv;
/*---------------------------------------------------------------------------*/
#ifdef CC26XX_MODEL_CONF_CPU_VARIANT
#define CC26XX_MODEL_CPU_VARIANT CC26XX_MODEL_CONF_CPU_VARIANT
#else
#define CC26XX_MODEL_CPU_VARIANT 2650
#endif
#if (CC26XX_MODEL_CPU_VARIANT != 2630) && (CC26XX_MODEL_CPU_VARIANT != 2650)
#error Incorrect CC26xx variant selected.
#error Check the value of CC26XX_MODEL_CONF_CPU_VARIANT
#error Supported values: 2630 and 2650
#endif
#endif // SMARTRF_SETTINGS_H_
/*---------------------------------------------------------------------------*/
#endif /* CC26XX_MODEL_H_ */
/*---------------------------------------------------------------------------*/
/**
* @}
* @}
*/

7
cpu/cc26xx/rtimer-arch.c → cpu/cc26xx-cc13xx/rtimer-arch.c
View File

@ -33,15 +33,14 @@
* @{
*
* \file
* Implementation of the arch-specific rtimer functions for the cc26xx
*
* Implementation of the arch-specific rtimer functions for the CC13xx/CC26xx
*/
/*---------------------------------------------------------------------------*/
#include "contiki.h"
#include "sys/energest.h"
#include "sys/rtimer.h"
#include "cpu.h"
#include "dev/cc26xx-rtc.h"
#include "dev/soc-rtc.h"
#include "ti-lib.h"
@ -72,7 +71,7 @@ void
rtimer_arch_schedule(rtimer_clock_t t)
{
/* Convert the rtimer tick value to a value suitable for the AON RTC */
cc26xx_rtc_schedule_one_shot(t);
soc_rtc_schedule_one_shot(AON_RTC_CH0, t);
}
/*---------------------------------------------------------------------------*/
/**

12
cpu/cc26xx/rtimer-arch.h → cpu/cc26xx-cc13xx/rtimer-arch.h
View File

@ -32,20 +32,14 @@
* \addtogroup cc26xx-clocks
* @{
*
* \defgroup cc26xx-rtimer CC26xx rtimer
* \defgroup cc26xx-rtimer CC13xx/CC26xx rtimer
*
* Implementation of the rtimer module for the CC26xx
*
* The rtimer runs on the AON RTC. We set the RTC's channel 2 to continuous
* compare mode, instead of scheduling the next tick interrupt by software.
* This gives us completely equidistant events.
*
* The RTC runs in all power modes (except shutdown)
* Implementation of the rtimer module for the CC13xx/CC26xx
* @{
*/
/**
* \file
* Header file for the CC26xx rtimer driver
* Header file for the CC13xx/CC26xx rtimer driver
*/
/*---------------------------------------------------------------------------*/
#ifndef RTIMER_ARCH_H_

2
cpu/cc26xx/slip-arch.c → cpu/cc26xx-cc13xx/slip-arch.c
View File

@ -34,7 +34,7 @@
* @{
*
* \file
* Arch-specific SLIP functions for the cc26xx
* Arch-specific SLIP functions for the CC13xx/CC26xx
*/
/*---------------------------------------------------------------------------*/
#include "contiki-conf.h"

40
cpu/cc26xx/ti-lib.h → cpu/cc26xx-cc13xx/ti-lib.h
View File

@ -31,7 +31,7 @@
* \addtogroup cc26xx
* @{
*
* \defgroup cc26xx-ti-lib TI CC26xxware Glue
* \defgroup cc26xx-ti-lib TI CC26xxware/CC13xxware Glue
*
* Glue file which renames TI CC26xxware functions. Thus, for example,
* PowerCtrlIOFreezeDisable() becomes power_ctrl_io_freeze_disable()
@ -89,7 +89,8 @@
#define ti_lib_aon_rtc_enable(...) AONRTCEnable(__VA_ARGS__)
#define ti_lib_aon_rtc_disable(...) AONRTCDisable(__VA_ARGS__)
#define ti_lib_aon_rtc_status(...) AONRTCStatus(__VA_ARGS__)
#define ti_lib_aon_rtc_active(...) AONRTCActive(__VA_ARGS__)
#define ti_lib_aon_rtc_channel_active(...) AONRTCChannelActive(__VA_ARGS__)
#define ti_lib_aon_rtc_reset(...) AONRTCReset(__VA_ARGS__)
#define ti_lib_aon_rtc_delay_config(...) AONRTCDelayConfig(__VA_ARGS__)
#define ti_lib_aon_rtc_combined_event_config(...) AONRTCCombinedEventConfig(__VA_ARGS__)
@ -107,6 +108,7 @@
#define ti_lib_aon_rtc_compare_value_set(...) AONRTCCompareValueSet(__VA_ARGS__)
#define ti_lib_aon_rtc_compare_value_get(...) AONRTCCompareValueGet(__VA_ARGS__)
#define ti_lib_aon_rtc_current_compare_value_get(...) AONRTCCurrentCompareValueGet(__VA_ARGS__)
#define ti_lib_aon_rtc_current_64_bit_value_get(...) AONRTCCurrent64BitValueGet(__VA_ARGS__)
#define ti_lib_aon_rtc_inc_value_ch2_set(...) AONRTCIncValueCh2Set(__VA_ARGS__)
#define ti_lib_aon_rtc_inc_value_ch2_get(...) AONRTCIncValueCh2Get(__VA_ARGS__)
#define ti_lib_aon_rtc_capture_value_ch1_get(...) AONRTCCaptureValueCh1Get(__VA_ARGS__)
@ -161,6 +163,29 @@
#define ti_lib_cpu_base_pri_set(...) CPUbasepriSet(__VA_ARGS__)
#define ti_lib_cpu_delay(...) CPUdelay(__VA_ARGS__)
/*---------------------------------------------------------------------------*/
/* chipinfo.h */
#include "driverlib/chipinfo.h"
#define ti_lib_chipinfo_get_supported_protocol_bv(...) ChipInfo_GetSupportedProtocol_BV(__VA_ARGS__)
#define ti_lib_chipinfo_supports_ble(...) ChipInfo_SupportsBLE(__VA_ARGS__)
#define ti_lib_chipinfo_supports_ieee_802_15_4(...) ChipInfo_SupportsIEEE_802_15_4(__VA_ARGS__)
#define ti_lib_chipinfo_supports_proprietary(...) ChipInfo_SupportsPROPRIETARY(__VA_ARGS__)
#define ti_lib_chipinfo_get_package_type(...) ChipInfo_GetPackageType(__VA_ARGS__)
#define ti_lib_chipinfo_package_type_is_4x4(...) ChipInfo_PackageTypeIs4x4(__VA_ARGS__)
#define ti_lib_chipinfo_package_type_is_5x5(...) ChipInfo_PackageTypeIs5x5(__VA_ARGS__)
#define ti_lib_chipinfo_package_type_is_7x7(...) ChipInfo_PackageTypeIs7x7(__VA_ARGS__)
#define ti_lib_chipinfo_get_device_id_hw_rev_code(...) ChipInfo_GetDeviceIdHwRevCode(__VA_ARGS__)
#define ti_lib_chipinfo_get_chip_family(...) ChipInfo_GetChipFamily(__VA_ARGS__)
#define ti_lib_chipinfo_chip_family_is_cc26xx(...) ChipInfo_ChipFamilyIsCC26xx(__VA_ARGS__)
#define ti_lib_chipinfo_chip_family_is_cc13xx(...) ChipInfo_ChipFamilyIsCC13xx(__VA_ARGS__)
#define ti_lib_chipinfo_get_hw_revision(...) ChipInfo_GetHwRevision(__VA_ARGS__)
#define ti_lib_chipinfo_hw_revision_is_1_0(...) ChipInfo_HwRevisionIs_1_0(__VA_ARGS__)
#define ti_lib_chipinfo_hw_revision_is_gteq_2_0(...) ChipInfo_HwRevisionIs_GTEQ_2_0(__VA_ARGS__)
#define ti_lib_chipinfo_hw_revision_is_2_0(...) ChipInfo_HwRevisionIs_2_0(__VA_ARGS__)
#define ti_lib_chipinfo_hw_revision_is_2_1(...) ChipInfo_HwRevisionIs_2_1(__VA_ARGS__)
#define ti_lib_chipinfo_hw_revision_is_2_2(...) ChipInfo_HwRevisionIs_2_2(__VA_ARGS__)
#define ti_lib_chipinfo_hw_revision_is_gteq_2_2(...) ChipInfo_HwRevisionIs_GTEQ_2_2( __VA_ARGS__ )
/*---------------------------------------------------------------------------*/
/* ddi.h */
#include "driverlib/ddi.h"
@ -309,7 +334,6 @@
#define ti_lib_prcm_peripheral_deep_sleep_disable(...) PRCMPeripheralDeepSleepDisable(__VA_ARGS__)
#define ti_lib_prcm_power_domain_status(...) PRCMPowerDomainStatus(__VA_ARGS__)
#define ti_lib_prcm_rf_ready(...) PRCMRfReady(__VA_ARGS__)
#define ti_lib_prcm_wdt_reset_status(...) PRCMWdtResetStatus(__VA_ARGS__)
#define ti_lib_prcm_sleep(...) PRCMSleep(__VA_ARGS__)
#define ti_lib_prcm_deep_sleep(...) PRCMDeepSleep(__VA_ARGS__)
#define ti_lib_prcm_cache_retention_enable(...) PRCMCacheRetentionEnable(__VA_ARGS__)
@ -384,10 +408,6 @@
#define ti_lib_rom_flash_protection_set ROM_FlashProtectionSet
#define ti_lib_rom_flash_protection_get ROM_FlashProtectionGet
#define ti_lib_rom_flash_protection_save ROM_FlashProtectionSave
#define ti_lib_rom_flash_sector_erase ROM_FlashSectorErase
#define ti_lib_rom_flash_program ROM_FlashProgram
#define ti_lib_rom_flash_program_nowait ROM_FlashProgramNowait
#define ti_lib_rom_flash_efuse_read_row ROM_FlashEfuseReadRow
#define ti_lib_rom_flash_disable_sectors_for_write ROM_FlashDisableSectorsForWrite
@ -507,8 +527,6 @@
#define ti_lib_hapi_max_value(a, b) HapiMaxValue(a,b)
#define ti_lib_hapi_mean_value(a, b) HapiMeanValue(a,b)
#define ti_lib_hapi_stand_deviation_value(a, b) HapiStandDeviationValue(a,b)
#define ti_lib_hapi_reset_peripheral(a) HapiResetPeripheral(a)
#define ti_lib_hapi_reset_domain(a) HapiResetDomain(a)
#define ti_lib_hapi_hf_source_safe_switch() HapiHFSourceSafeSwitch()
#define ti_lib_hapi_select_comp_a_input(a) HapiSelectCompAInput(a)
#define ti_lib_hapi_select_comp_a_ref(a) HapiSelectCompARef(a)
@ -517,9 +535,6 @@
#define ti_lib_hapi_get_flash_size() HapiGetFlashSize()
#define ti_lib_hapi_sector_erase(a) HapiSectorErase(a)
#define ti_lib_hapi_program_flash(a, b, c) HapiProgramFlash(a, b, c)
#define ti_lib_hapi_get_flash_size() HapiGetFlashSize()
#define ti_lib_hapi_sector_erase(a) HapiSectorErase(a)
#define ti_lib_hapi_program_flash(a, b, c) HapiProgramFlash(a, b, c)
/*---------------------------------------------------------------------------*/
/* sys_ctrl.h */
#include "driverlib/sys_ctrl.h"
@ -578,7 +593,6 @@
#define ti_lib_timer_disable(...) TimerDisable(__VA_ARGS__)
#define ti_lib_timer_configure(...) TimerConfigure(__VA_ARGS__)
#define ti_lib_timer_level_control(...) TimerLevelControl(__VA_ARGS__)
#define ti_lib_timer_trigger_control(...) TimerTriggerControl(__VA_ARGS__)
#define ti_lib_timer_event_control(...) TimerEventControl(__VA_ARGS__)
#define ti_lib_timer_stall_control(...) TimerStallControl(__VA_ARGS__)
#define ti_lib_timer_wait_on_trigger_control(...) TimerWaitOnTriggerControl(__VA_ARGS__)

2192
cpu/cc26xx/dev/cc26xx-rf.c
View File

File diff suppressed because it is too large Load Diff

623
cpu/cc26xx/dev/rfc-api/ble_cmd_field.h
View File

@ -1,623 +0,0 @@
/******************************************************************************
* Filename: ble_cmd_field.h
* Revised: $ $
* Revision: $ $
*
* Description: CC26xx/CC13xx API for Bluetooth Low Energy commands
*
* Copyright (C) 2015 Texas Instruments Incorporated - http://www.ti.com/
*
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* Neither the name of Texas Instruments Incorporated nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************/
#ifndef __BLE_CMD_FIELD_H
#define __BLE_CMD_FIELD_H
#include <stdint.h>
#include "mailbox.h"
#include "common_cmd.h"
#define _POSITION_bleRadioOp_channel 14
#define _TYPE_bleRadioOp_channel uint8_t
#define _POSITION_bleRadioOp_whitening 15
#define _TYPE_bleRadioOp_whitening uint8_t
#define _BITPOS_bleRadioOp_whitening_init 0
#define _NBITS_bleRadioOp_whitening_init 7
#define _BITPOS_bleRadioOp_whitening_bOverride 7
#define _NBITS_bleRadioOp_whitening_bOverride 1
#define _POSITION_bleRadioOp_pParams 16
#define _TYPE_bleRadioOp_pParams uint8_t*
#define _POSITION_bleRadioOp_pOutput 20
#define _TYPE_bleRadioOp_pOutput uint8_t*
#define _SIZEOF_bleRadioOp 24
#define _SIZEOF_CMD_BLE_SLAVE 24
#define _SIZEOF_CMD_BLE_MASTER 24
#define _SIZEOF_CMD_BLE_ADV 24
#define _SIZEOF_CMD_BLE_ADV_DIR 24
#define _SIZEOF_CMD_BLE_ADV_NC 24
#define _SIZEOF_CMD_BLE_ADV_SCAN 24
#define _SIZEOF_CMD_BLE_SCANNER 24
#define _SIZEOF_CMD_BLE_INITIATOR 24
#define _SIZEOF_CMD_BLE_GENERIC_RX 24
#define _SIZEOF_CMD_BLE_TX_TEST 24
#define _POSITION_CMD_BLE_ADV_PAYLOAD_payloadType 2
#define _TYPE_CMD_BLE_ADV_PAYLOAD_payloadType uint8_t
#define _POSITION_CMD_BLE_ADV_PAYLOAD_newLen 3
#define _TYPE_CMD_BLE_ADV_PAYLOAD_newLen uint8_t
#define _POSITION_CMD_BLE_ADV_PAYLOAD_pNewData 4
#define _TYPE_CMD_BLE_ADV_PAYLOAD_pNewData uint8_t*
#define _POSITION_CMD_BLE_ADV_PAYLOAD_pParams 8
#define _TYPE_CMD_BLE_ADV_PAYLOAD_pParams uint8_t*
#define _SIZEOF_CMD_BLE_ADV_PAYLOAD 12
#define _POSITION_bleMasterSlavePar_pRxQ 0
#define _TYPE_bleMasterSlavePar_pRxQ dataQueue_t*
#define _POSITION_bleMasterSlavePar_pTxQ 4
#define _TYPE_bleMasterSlavePar_pTxQ dataQueue_t*
#define _POSITION_bleMasterSlavePar_rxConfig 8
#define _TYPE_bleMasterSlavePar_rxConfig uint8_t
#define _BITPOS_bleMasterSlavePar_rxConfig_bAutoFlushIgnored 0
#define _NBITS_bleMasterSlavePar_rxConfig_bAutoFlushIgnored 1
#define _BITPOS_bleMasterSlavePar_rxConfig_bAutoFlushCrcErr 1
#define _NBITS_bleMasterSlavePar_rxConfig_bAutoFlushCrcErr 1
#define _BITPOS_bleMasterSlavePar_rxConfig_bAutoFlushEmpty 2
#define _NBITS_bleMasterSlavePar_rxConfig_bAutoFlushEmpty 1
#define _BITPOS_bleMasterSlavePar_rxConfig_bIncludeLenByte 3
#define _NBITS_bleMasterSlavePar_rxConfig_bIncludeLenByte 1
#define _BITPOS_bleMasterSlavePar_rxConfig_bIncludeCrc 4
#define _NBITS_bleMasterSlavePar_rxConfig_bIncludeCrc 1
#define _BITPOS_bleMasterSlavePar_rxConfig_bAppendRssi 5
#define _NBITS_bleMasterSlavePar_rxConfig_bAppendRssi 1
#define _BITPOS_bleMasterSlavePar_rxConfig_bAppendStatus 6
#define _NBITS_bleMasterSlavePar_rxConfig_bAppendStatus 1
#define _BITPOS_bleMasterSlavePar_rxConfig_bAppendTimestamp 7
#define _NBITS_bleMasterSlavePar_rxConfig_bAppendTimestamp 1
#define _POSITION_bleMasterSlavePar_seqStat 9
#define _TYPE_bleMasterSlavePar_seqStat uint8_t
#define _BITPOS_bleMasterSlavePar_seqStat_lastRxSn 0
#define _NBITS_bleMasterSlavePar_seqStat_lastRxSn 1
#define _BITPOS_bleMasterSlavePar_seqStat_lastTxSn 1
#define _NBITS_bleMasterSlavePar_seqStat_lastTxSn 1
#define _BITPOS_bleMasterSlavePar_seqStat_nextTxSn 2
#define _NBITS_bleMasterSlavePar_seqStat_nextTxSn 1
#define _BITPOS_bleMasterSlavePar_seqStat_bFirstPkt 3
#define _NBITS_bleMasterSlavePar_seqStat_bFirstPkt 1
#define _BITPOS_bleMasterSlavePar_seqStat_bAutoEmpty 4
#define _NBITS_bleMasterSlavePar_seqStat_bAutoEmpty 1
#define _BITPOS_bleMasterSlavePar_seqStat_bLlCtrlTx 5
#define _NBITS_bleMasterSlavePar_seqStat_bLlCtrlTx 1
#define _BITPOS_bleMasterSlavePar_seqStat_bLlCtrlAckRx 6
#define _NBITS_bleMasterSlavePar_seqStat_bLlCtrlAckRx 1
#define _BITPOS_bleMasterSlavePar_seqStat_bLlCtrlAckPending 7
#define _NBITS_bleMasterSlavePar_seqStat_bLlCtrlAckPending 1
#define _POSITION_bleMasterSlavePar_maxNack 10
#define _TYPE_bleMasterSlavePar_maxNack uint8_t
#define _POSITION_bleMasterSlavePar_maxPkt 11
#define _TYPE_bleMasterSlavePar_maxPkt uint8_t
#define _POSITION_bleMasterSlavePar_accessAddress 12
#define _TYPE_bleMasterSlavePar_accessAddress uint32_t
#define _POSITION_bleMasterSlavePar_crcInit0 16
#define _TYPE_bleMasterSlavePar_crcInit0 uint8_t
#define _POSITION_bleMasterSlavePar_crcInit1 17
#define _TYPE_bleMasterSlavePar_crcInit1 uint8_t
#define _POSITION_bleMasterSlavePar_crcInit2 18
#define _TYPE_bleMasterSlavePar_crcInit2 uint8_t
#define _POSITION_bleMasterSlavePar_crcInit 16
#define _TYPE_bleMasterSlavePar_crcInit uint32_t
#define _SIZEOF_bleMasterSlavePar 20
#define _POSITION_bleMasterPar_endTrigger 19
#define _TYPE_bleMasterPar_endTrigger uint8_t
#define _BITPOS_bleMasterPar_endTrigger_triggerType 0
#define _NBITS_bleMasterPar_endTrigger_triggerType 4
#define _BITPOS_bleMasterPar_endTrigger_bEnaCmd 4
#define _NBITS_bleMasterPar_endTrigger_bEnaCmd 1
#define _BITPOS_bleMasterPar_endTrigger_triggerNo 5
#define _NBITS_bleMasterPar_endTrigger_triggerNo 2
#define _BITPOS_bleMasterPar_endTrigger_pastTrig 7
#define _NBITS_bleMasterPar_endTrigger_pastTrig 1
#define _POSITION_bleMasterPar_endTime 20
#define _TYPE_bleMasterPar_endTime ratmr_t
#define _SIZEOF_bleMasterPar 24
#define _POSITION_bleSlavePar_timeoutTrigger 19
#define _TYPE_bleSlavePar_timeoutTrigger uint8_t
#define _BITPOS_bleSlavePar_timeoutTrigger_triggerType 0
#define _NBITS_bleSlavePar_timeoutTrigger_triggerType 4
#define _BITPOS_bleSlavePar_timeoutTrigger_bEnaCmd 4
#define _NBITS_bleSlavePar_timeoutTrigger_bEnaCmd 1
#define _BITPOS_bleSlavePar_timeoutTrigger_triggerNo 5
#define _NBITS_bleSlavePar_timeoutTrigger_triggerNo 2
#define _BITPOS_bleSlavePar_timeoutTrigger_pastTrig 7
#define _NBITS_bleSlavePar_timeoutTrigger_pastTrig 1
#define _POSITION_bleSlavePar_timeoutTime 20
#define _TYPE_bleSlavePar_timeoutTime ratmr_t
#define _POSITION_bleSlavePar_endTrigger 27
#define _TYPE_bleSlavePar_endTrigger uint8_t
#define _BITPOS_bleSlavePar_endTrigger_triggerType 0
#define _NBITS_bleSlavePar_endTrigger_triggerType 4
#define _BITPOS_bleSlavePar_endTrigger_bEnaCmd 4
#define _NBITS_bleSlavePar_endTrigger_bEnaCmd 1
#define _BITPOS_bleSlavePar_endTrigger_triggerNo 5
#define _NBITS_bleSlavePar_endTrigger_triggerNo 2
#define _BITPOS_bleSlavePar_endTrigger_pastTrig 7
#define _NBITS_bleSlavePar_endTrigger_pastTrig 1
#define _POSITION_bleSlavePar_endTime 28
#define _TYPE_bleSlavePar_endTime ratmr_t
#define _SIZEOF_bleSlavePar 32
#define _POSITION_bleAdvPar_pRxQ 0
#define _TYPE_bleAdvPar_pRxQ dataQueue_t*
#define _POSITION_bleAdvPar_rxConfig 4
#define _TYPE_bleAdvPar_rxConfig uint8_t
#define _BITPOS_bleAdvPar_rxConfig_bAutoFlushIgnored 0
#define _NBITS_bleAdvPar_rxConfig_bAutoFlushIgnored 1
#define _BITPOS_bleAdvPar_rxConfig_bAutoFlushCrcErr 1
#define _NBITS_bleAdvPar_rxConfig_bAutoFlushCrcErr 1
#define _BITPOS_bleAdvPar_rxConfig_bAutoFlushEmpty 2
#define _NBITS_bleAdvPar_rxConfig_bAutoFlushEmpty 1
#define _BITPOS_bleAdvPar_rxConfig_bIncludeLenByte 3
#define _NBITS_bleAdvPar_rxConfig_bIncludeLenByte 1
#define _BITPOS_bleAdvPar_rxConfig_bIncludeCrc 4
#define _NBITS_bleAdvPar_rxConfig_bIncludeCrc 1
#define _BITPOS_bleAdvPar_rxConfig_bAppendRssi 5
#define _NBITS_bleAdvPar_rxConfig_bAppendRssi 1
#define _BITPOS_bleAdvPar_rxConfig_bAppendStatus 6
#define _NBITS_bleAdvPar_rxConfig_bAppendStatus 1
#define _BITPOS_bleAdvPar_rxConfig_bAppendTimestamp 7
#define _NBITS_bleAdvPar_rxConfig_bAppendTimestamp 1
#define _POSITION_bleAdvPar_advConfig 5
#define _TYPE_bleAdvPar_advConfig uint8_t
#define _BITPOS_bleAdvPar_advConfig_advFilterPolicy 0
#define _NBITS_bleAdvPar_advConfig_advFilterPolicy 2
#define _BITPOS_bleAdvPar_advConfig_deviceAddrType 2
#define _NBITS_bleAdvPar_advConfig_deviceAddrType 1
#define _BITPOS_bleAdvPar_advConfig_peerAddrType 3
#define _NBITS_bleAdvPar_advConfig_peerAddrType 1
#define _BITPOS_bleAdvPar_advConfig_bStrictLenFilter 4
#define _NBITS_bleAdvPar_advConfig_bStrictLenFilter 1
#define _POSITION_bleAdvPar_advLen 6
#define _TYPE_bleAdvPar_advLen uint8_t
#define _POSITION_bleAdvPar_scanRspLen 7
#define _TYPE_bleAdvPar_scanRspLen uint8_t
#define _POSITION_bleAdvPar_pAdvData 8
#define _TYPE_bleAdvPar_pAdvData uint8_t*
#define _POSITION_bleAdvPar_pScanRspData 12
#define _TYPE_bleAdvPar_pScanRspData uint8_t*
#define _POSITION_bleAdvPar_pDeviceAddress 16
#define _TYPE_bleAdvPar_pDeviceAddress uint16_t*
#define _POSITION_bleAdvPar_pWhiteList 20
#define _TYPE_bleAdvPar_pWhiteList uint32_t*
#define _POSITION_bleAdvPar_endTrigger 27
#define _TYPE_bleAdvPar_endTrigger uint8_t
#define _BITPOS_bleAdvPar_endTrigger_triggerType 0
#define _NBITS_bleAdvPar_endTrigger_triggerType 4
#define _BITPOS_bleAdvPar_endTrigger_bEnaCmd 4
#define _NBITS_bleAdvPar_endTrigger_bEnaCmd 1
#define _BITPOS_bleAdvPar_endTrigger_triggerNo 5
#define _NBITS_bleAdvPar_endTrigger_triggerNo 2
#define _BITPOS_bleAdvPar_endTrigger_pastTrig 7
#define _NBITS_bleAdvPar_endTrigger_pastTrig 1
#define _POSITION_bleAdvPar_endTime 28
#define _TYPE_bleAdvPar_endTime ratmr_t
#define _SIZEOF_bleAdvPar 32
#define _POSITION_bleScannerPar_pRxQ 0
#define _TYPE_bleScannerPar_pRxQ dataQueue_t*
#define _POSITION_bleScannerPar_rxConfig 4
#define _TYPE_bleScannerPar_rxConfig uint8_t
#define _BITPOS_bleScannerPar_rxConfig_bAutoFlushIgnored 0
#define _NBITS_bleScannerPar_rxConfig_bAutoFlushIgnored 1
#define _BITPOS_bleScannerPar_rxConfig_bAutoFlushCrcErr 1
#define _NBITS_bleScannerPar_rxConfig_bAutoFlushCrcErr 1
#define _BITPOS_bleScannerPar_rxConfig_bAutoFlushEmpty 2
#define _NBITS_bleScannerPar_rxConfig_bAutoFlushEmpty 1
#define _BITPOS_bleScannerPar_rxConfig_bIncludeLenByte 3
#define _NBITS_bleScannerPar_rxConfig_bIncludeLenByte 1
#define _BITPOS_bleScannerPar_rxConfig_bIncludeCrc 4
#define _NBITS_bleScannerPar_rxConfig_bIncludeCrc 1
#define _BITPOS_bleScannerPar_rxConfig_bAppendRssi 5
#define _NBITS_bleScannerPar_rxConfig_bAppendRssi 1
#define _BITPOS_bleScannerPar_rxConfig_bAppendStatus 6
#define _NBITS_bleScannerPar_rxConfig_bAppendStatus 1
#define _BITPOS_bleScannerPar_rxConfig_bAppendTimestamp 7
#define _NBITS_bleScannerPar_rxConfig_bAppendTimestamp 1
#define _POSITION_bleScannerPar_scanConfig 5
#define _TYPE_bleScannerPar_scanConfig uint8_t
#define _BITPOS_bleScannerPar_scanConfig_scanFilterPolicy 0
#define _NBITS_bleScannerPar_scanConfig_scanFilterPolicy 1
#define _BITPOS_bleScannerPar_scanConfig_bActiveScan 1
#define _NBITS_bleScannerPar_scanConfig_bActiveScan 1
#define _BITPOS_bleScannerPar_scanConfig_deviceAddrType 2
#define _NBITS_bleScannerPar_scanConfig_deviceAddrType 1
#define _BITPOS_bleScannerPar_scanConfig_bStrictLenFilter 4
#define _NBITS_bleScannerPar_scanConfig_bStrictLenFilter 1
#define _BITPOS_bleScannerPar_scanConfig_bAutoWlIgnore 5
#define _NBITS_bleScannerPar_scanConfig_bAutoWlIgnore 1
#define _BITPOS_bleScannerPar_scanConfig_bEndOnRpt 6
#define _NBITS_bleScannerPar_scanConfig_bEndOnRpt 1
#define _POSITION_bleScannerPar_randomState 6
#define _TYPE_bleScannerPar_randomState uint16_t
#define _POSITION_bleScannerPar_backoffCount 8
#define _TYPE_bleScannerPar_backoffCount uint16_t
#define _POSITION_bleScannerPar_backoffPar 10
#define _TYPE_bleScannerPar_backoffPar uint8_t
#define _BITPOS_bleScannerPar_backoffPar_logUpperLimit 0
#define _NBITS_bleScannerPar_backoffPar_logUpperLimit 4
#define _BITPOS_bleScannerPar_backoffPar_bLastSucceeded 4
#define _NBITS_bleScannerPar_backoffPar_bLastSucceeded 1
#define _BITPOS_bleScannerPar_backoffPar_bLastFailed 5
#define _NBITS_bleScannerPar_backoffPar_bLastFailed 1
#define _POSITION_bleScannerPar_scanReqLen 11
#define _TYPE_bleScannerPar_scanReqLen uint8_t
#define _POSITION_bleScannerPar_pScanReqData 12
#define _TYPE_bleScannerPar_pScanReqData uint8_t*
#define _POSITION_bleScannerPar_pDeviceAddress 16
#define _TYPE_bleScannerPar_pDeviceAddress uint16_t*
#define _POSITION_bleScannerPar_pWhiteList 20
#define _TYPE_bleScannerPar_pWhiteList uint32_t*
#define _POSITION_bleScannerPar_timeoutTrigger 26
#define _TYPE_bleScannerPar_timeoutTrigger uint8_t
#define _BITPOS_bleScannerPar_timeoutTrigger_triggerType 0
#define _NBITS_bleScannerPar_timeoutTrigger_triggerType 4
#define _BITPOS_bleScannerPar_timeoutTrigger_bEnaCmd 4
#define _NBITS_bleScannerPar_timeoutTrigger_bEnaCmd 1
#define _BITPOS_bleScannerPar_timeoutTrigger_triggerNo 5
#define _NBITS_bleScannerPar_timeoutTrigger_triggerNo 2
#define _BITPOS_bleScannerPar_timeoutTrigger_pastTrig 7
#define _NBITS_bleScannerPar_timeoutTrigger_pastTrig 1
#define _POSITION_bleScannerPar_endTrigger 27
#define _TYPE_bleScannerPar_endTrigger uint8_t
#define _BITPOS_bleScannerPar_endTrigger_triggerType 0
#define _NBITS_bleScannerPar_endTrigger_triggerType 4
#define _BITPOS_bleScannerPar_endTrigger_bEnaCmd 4
#define _NBITS_bleScannerPar_endTrigger_bEnaCmd 1
#define _BITPOS_bleScannerPar_endTrigger_triggerNo 5
#define _NBITS_bleScannerPar_endTrigger_triggerNo 2
#define _BITPOS_bleScannerPar_endTrigger_pastTrig 7
#define _NBITS_bleScannerPar_endTrigger_pastTrig 1
#define _POSITION_bleScannerPar_timeoutTime 28
#define _TYPE_bleScannerPar_timeoutTime ratmr_t
#define _POSITION_bleScannerPar_endTime 32
#define _TYPE_bleScannerPar_endTime ratmr_t
#define _SIZEOF_bleScannerPar 36
#define _POSITION_bleInitiatorPar_pRxQ 0
#define _TYPE_bleInitiatorPar_pRxQ dataQueue_t*
#define _POSITION_bleInitiatorPar_rxConfig 4
#define _TYPE_bleInitiatorPar_rxConfig uint8_t
#define _BITPOS_bleInitiatorPar_rxConfig_bAutoFlushIgnored 0
#define _NBITS_bleInitiatorPar_rxConfig_bAutoFlushIgnored 1
#define _BITPOS_bleInitiatorPar_rxConfig_bAutoFlushCrcErr 1
#define _NBITS_bleInitiatorPar_rxConfig_bAutoFlushCrcErr 1
#define _BITPOS_bleInitiatorPar_rxConfig_bAutoFlushEmpty 2
#define _NBITS_bleInitiatorPar_rxConfig_bAutoFlushEmpty 1
#define _BITPOS_bleInitiatorPar_rxConfig_bIncludeLenByte 3
#define _NBITS_bleInitiatorPar_rxConfig_bIncludeLenByte 1
#define _BITPOS_bleInitiatorPar_rxConfig_bIncludeCrc 4
#define _NBITS_bleInitiatorPar_rxConfig_bIncludeCrc 1
#define _BITPOS_bleInitiatorPar_rxConfig_bAppendRssi 5
#define _NBITS_bleInitiatorPar_rxConfig_bAppendRssi 1
#define _BITPOS_bleInitiatorPar_rxConfig_bAppendStatus 6
#define _NBITS_bleInitiatorPar_rxConfig_bAppendStatus 1
#define _BITPOS_bleInitiatorPar_rxConfig_bAppendTimestamp 7
#define _NBITS_bleInitiatorPar_rxConfig_bAppendTimestamp 1
#define _POSITION_bleInitiatorPar_initConfig 5
#define _TYPE_bleInitiatorPar_initConfig uint8_t
#define _BITPOS_bleInitiatorPar_initConfig_bUseWhiteList 0
#define _NBITS_bleInitiatorPar_initConfig_bUseWhiteList 1
#define _BITPOS_bleInitiatorPar_initConfig_bDynamicWinOffset 1
#define _NBITS_bleInitiatorPar_initConfig_bDynamicWinOffset 1
#define _BITPOS_bleInitiatorPar_initConfig_deviceAddrType 2
#define _NBITS_bleInitiatorPar_initConfig_deviceAddrType 1
#define _BITPOS_bleInitiatorPar_initConfig_peerAddrType 3
#define _NBITS_bleInitiatorPar_initConfig_peerAddrType 1
#define _BITPOS_bleInitiatorPar_initConfig_bStrictLenFilter 4
#define _NBITS_bleInitiatorPar_initConfig_bStrictLenFilter 1
#define _POSITION_bleInitiatorPar_connectReqLen 7
#define _TYPE_bleInitiatorPar_connectReqLen uint8_t
#define _POSITION_bleInitiatorPar_pConnectReqData 8
#define _TYPE_bleInitiatorPar_pConnectReqData uint8_t*
#define _POSITION_bleInitiatorPar_pDeviceAddress 12
#define _TYPE_bleInitiatorPar_pDeviceAddress uint16_t*
#define _POSITION_bleInitiatorPar_pWhiteList 16
#define _TYPE_bleInitiatorPar_pWhiteList uint32_t*
#define _POSITION_bleInitiatorPar_connectTime 20
#define _TYPE_bleInitiatorPar_connectTime ratmr_t
#define _POSITION_bleInitiatorPar_timeoutTrigger 26
#define _TYPE_bleInitiatorPar_timeoutTrigger uint8_t
#define _BITPOS_bleInitiatorPar_timeoutTrigger_triggerType 0
#define _NBITS_bleInitiatorPar_timeoutTrigger_triggerType 4
#define _BITPOS_bleInitiatorPar_timeoutTrigger_bEnaCmd 4
#define _NBITS_bleInitiatorPar_timeoutTrigger_bEnaCmd 1
#define _BITPOS_bleInitiatorPar_timeoutTrigger_triggerNo 5
#define _NBITS_bleInitiatorPar_timeoutTrigger_triggerNo 2
#define _BITPOS_bleInitiatorPar_timeoutTrigger_pastTrig 7
#define _NBITS_bleInitiatorPar_timeoutTrigger_pastTrig 1
#define _POSITION_bleInitiatorPar_endTrigger 27
#define _TYPE_bleInitiatorPar_endTrigger uint8_t
#define _BITPOS_bleInitiatorPar_endTrigger_triggerType 0
#define _NBITS_bleInitiatorPar_endTrigger_triggerType 4
#define _BITPOS_bleInitiatorPar_endTrigger_bEnaCmd 4
#define _NBITS_bleInitiatorPar_endTrigger_bEnaCmd 1
#define _BITPOS_bleInitiatorPar_endTrigger_triggerNo 5
#define _NBITS_bleInitiatorPar_endTrigger_triggerNo 2
#define _BITPOS_bleInitiatorPar_endTrigger_pastTrig 7
#define _NBITS_bleInitiatorPar_endTrigger_pastTrig 1
#define _POSITION_bleInitiatorPar_timeoutTime 28
#define _TYPE_bleInitiatorPar_timeoutTime ratmr_t
#define _POSITION_bleInitiatorPar_endTime 32
#define _TYPE_bleInitiatorPar_endTime ratmr_t
#define _SIZEOF_bleInitiatorPar 36
#define _POSITION_bleGenericRxPar_pRxQ 0
#define _TYPE_bleGenericRxPar_pRxQ dataQueue_t*
#define _POSITION_bleGenericRxPar_rxConfig 4
#define _TYPE_bleGenericRxPar_rxConfig uint8_t
#define _BITPOS_bleGenericRxPar_rxConfig_bAutoFlushIgnored 0
#define _NBITS_bleGenericRxPar_rxConfig_bAutoFlushIgnored 1
#define _BITPOS_bleGenericRxPar_rxConfig_bAutoFlushCrcErr 1
#define _NBITS_bleGenericRxPar_rxConfig_bAutoFlushCrcErr 1
#define _BITPOS_bleGenericRxPar_rxConfig_bAutoFlushEmpty 2
#define _NBITS_bleGenericRxPar_rxConfig_bAutoFlushEmpty 1
#define _BITPOS_bleGenericRxPar_rxConfig_bIncludeLenByte 3
#define _NBITS_bleGenericRxPar_rxConfig_bIncludeLenByte 1
#define _BITPOS_bleGenericRxPar_rxConfig_bIncludeCrc 4
#define _NBITS_bleGenericRxPar_rxConfig_bIncludeCrc 1
#define _BITPOS_bleGenericRxPar_rxConfig_bAppendRssi 5
#define _NBITS_bleGenericRxPar_rxConfig_bAppendRssi 1
#define _BITPOS_bleGenericRxPar_rxConfig_bAppendStatus 6
#define _NBITS_bleGenericRxPar_rxConfig_bAppendStatus 1
#define _BITPOS_bleGenericRxPar_rxConfig_bAppendTimestamp 7
#define _NBITS_bleGenericRxPar_rxConfig_bAppendTimestamp 1
#define _POSITION_bleGenericRxPar_bRepeat 5
#define _TYPE_bleGenericRxPar_bRepeat uint8_t
#define _POSITION_bleGenericRxPar_accessAddress 8
#define _TYPE_bleGenericRxPar_accessAddress uint32_t
#define _POSITION_bleGenericRxPar_crcInit0 12
#define _TYPE_bleGenericRxPar_crcInit0 uint8_t
#define _POSITION_bleGenericRxPar_crcInit1 13
#define _TYPE_bleGenericRxPar_crcInit1 uint8_t
#define _POSITION_bleGenericRxPar_crcInit2 14
#define _TYPE_bleGenericRxPar_crcInit2 uint8_t
#define _POSITION_bleGenericRxPar_crcInit 12
#define _TYPE_bleGenericRxPar_crcInit uint32_t
#define _POSITION_bleGenericRxPar_endTrigger 15
#define _TYPE_bleGenericRxPar_endTrigger uint8_t
#define _BITPOS_bleGenericRxPar_endTrigger_triggerType 0
#define _NBITS_bleGenericRxPar_endTrigger_triggerType 4
#define _BITPOS_bleGenericRxPar_endTrigger_bEnaCmd 4
#define _NBITS_bleGenericRxPar_endTrigger_bEnaCmd 1
#define _BITPOS_bleGenericRxPar_endTrigger_triggerNo 5
#define _NBITS_bleGenericRxPar_endTrigger_triggerNo 2
#define _BITPOS_bleGenericRxPar_endTrigger_pastTrig 7
#define _NBITS_bleGenericRxPar_endTrigger_pastTrig 1
#define _POSITION_bleGenericRxPar_endTime 16
#define _TYPE_bleGenericRxPar_endTime ratmr_t
#define _SIZEOF_bleGenericRxPar 20
#define _POSITION_bleTxTestPar_numPackets 0
#define _TYPE_bleTxTestPar_numPackets uint16_t
#define _POSITION_bleTxTestPar_payloadLength 2
#define _TYPE_bleTxTestPar_payloadLength uint8_t
#define _POSITION_bleTxTestPar_packetType 3
#define _TYPE_bleTxTestPar_packetType uint8_t
#define _POSITION_bleTxTestPar_period 4
#define _TYPE_bleTxTestPar_period ratmr_t
#define _POSITION_bleTxTestPar_config 8
#define _TYPE_bleTxTestPar_config uint8_t
#define _BITPOS_bleTxTestPar_config_bOverrideDefault 0
#define _NBITS_bleTxTestPar_config_bOverrideDefault 1
#define _BITPOS_bleTxTestPar_config_bUsePrbs9 1
#define _NBITS_bleTxTestPar_config_bUsePrbs9 1
#define _BITPOS_bleTxTestPar_config_bUsePrbs15 2
#define _NBITS_bleTxTestPar_config_bUsePrbs15 1
#define _POSITION_bleTxTestPar_byteVal 9
#define _TYPE_bleTxTestPar_byteVal uint8_t
#define _POSITION_bleTxTestPar_endTrigger 11
#define _TYPE_bleTxTestPar_endTrigger uint8_t
#define _BITPOS_bleTxTestPar_endTrigger_triggerType 0
#define _NBITS_bleTxTestPar_endTrigger_triggerType 4
#define _BITPOS_bleTxTestPar_endTrigger_bEnaCmd 4
#define _NBITS_bleTxTestPar_endTrigger_bEnaCmd 1
#define _BITPOS_bleTxTestPar_endTrigger_triggerNo 5
#define _NBITS_bleTxTestPar_endTrigger_triggerNo 2
#define _BITPOS_bleTxTestPar_endTrigger_pastTrig 7
#define _NBITS_bleTxTestPar_endTrigger_pastTrig 1
#define _POSITION_bleTxTestPar_endTime 12
#define _TYPE_bleTxTestPar_endTime ratmr_t
#define _SIZEOF_bleTxTestPar 16
#define _POSITION_bleMasterSlaveOutput_nTx 0
#define _TYPE_bleMasterSlaveOutput_nTx uint8_t
#define _POSITION_bleMasterSlaveOutput_nTxAck 1
#define _TYPE_bleMasterSlaveOutput_nTxAck uint8_t
#define _POSITION_bleMasterSlaveOutput_nTxCtrl 2
#define _TYPE_bleMasterSlaveOutput_nTxCtrl uint8_t
#define _POSITION_bleMasterSlaveOutput_nTxCtrlAck 3
#define _TYPE_bleMasterSlaveOutput_nTxCtrlAck uint8_t
#define _POSITION_bleMasterSlaveOutput_nTxCtrlAckAck 4
#define _TYPE_bleMasterSlaveOutput_nTxCtrlAckAck uint8_t
#define _POSITION_bleMasterSlaveOutput_nTxRetrans 5
#define _TYPE_bleMasterSlaveOutput_nTxRetrans uint8_t
#define _POSITION_bleMasterSlaveOutput_nTxEntryDone 6
#define _TYPE_bleMasterSlaveOutput_nTxEntryDone uint8_t
#define _POSITION_bleMasterSlaveOutput_nRxOk 7
#define _TYPE_bleMasterSlaveOutput_nRxOk uint8_t
#define _POSITION_bleMasterSlaveOutput_nRxCtrl 8
#define _TYPE_bleMasterSlaveOutput_nRxCtrl uint8_t
#define _POSITION_bleMasterSlaveOutput_nRxCtrlAck 9
#define _TYPE_bleMasterSlaveOutput_nRxCtrlAck uint8_t
#define _POSITION_bleMasterSlaveOutput_nRxNok 10
#define _TYPE_bleMasterSlaveOutput_nRxNok uint8_t
#define _POSITION_bleMasterSlaveOutput_nRxIgnored 11
#define _TYPE_bleMasterSlaveOutput_nRxIgnored uint8_t
#define _POSITION_bleMasterSlaveOutput_nRxEmpty 12
#define _TYPE_bleMasterSlaveOutput_nRxEmpty uint8_t
#define _POSITION_bleMasterSlaveOutput_nRxBufFull 13
#define _TYPE_bleMasterSlaveOutput_nRxBufFull uint8_t
#define _POSITION_bleMasterSlaveOutput_lastRssi 14
#define _TYPE_bleMasterSlaveOutput_lastRssi int8_t
#define _POSITION_bleMasterSlaveOutput_pktStatus 15
#define _TYPE_bleMasterSlaveOutput_pktStatus uint8_t
#define _BITPOS_bleMasterSlaveOutput_pktStatus_bTimeStampValid 0
#define _NBITS_bleMasterSlaveOutput_pktStatus_bTimeStampValid 1
#define _BITPOS_bleMasterSlaveOutput_pktStatus_bLastCrcErr 1
#define _NBITS_bleMasterSlaveOutput_pktStatus_bLastCrcErr 1
#define _BITPOS_bleMasterSlaveOutput_pktStatus_bLastIgnored 2
#define _NBITS_bleMasterSlaveOutput_pktStatus_bLastIgnored 1
#define _BITPOS_bleMasterSlaveOutput_pktStatus_bLastEmpty 3
#define _NBITS_bleMasterSlaveOutput_pktStatus_bLastEmpty 1
#define _BITPOS_bleMasterSlaveOutput_pktStatus_bLastCtrl 4
#define _NBITS_bleMasterSlaveOutput_pktStatus_bLastCtrl 1
#define _BITPOS_bleMasterSlaveOutput_pktStatus_bLastMd 5
#define _NBITS_bleMasterSlaveOutput_pktStatus_bLastMd 1
#define _BITPOS_bleMasterSlaveOutput_pktStatus_bLastAck 6
#define _NBITS_bleMasterSlaveOutput_pktStatus_bLastAck 1
#define _POSITION_bleMasterSlaveOutput_timeStamp 16
#define _TYPE_bleMasterSlaveOutput_timeStamp ratmr_t
#define _SIZEOF_bleMasterSlaveOutput 20
#define _POSITION_bleAdvOutput_nTxAdvInd 0
#define _TYPE_bleAdvOutput_nTxAdvInd uint16_t
#define _POSITION_bleAdvOutput_nTxScanRsp 2
#define _TYPE_bleAdvOutput_nTxScanRsp uint8_t
#define _POSITION_bleAdvOutput_nRxScanReq 3
#define _TYPE_bleAdvOutput_nRxScanReq uint8_t
#define _POSITION_bleAdvOutput_nRxConnectReq 4
#define _TYPE_bleAdvOutput_nRxConnectReq uint8_t
#define _POSITION_bleAdvOutput_nRxNok 6
#define _TYPE_bleAdvOutput_nRxNok uint16_t
#define _POSITION_bleAdvOutput_nRxIgnored 8
#define _TYPE_bleAdvOutput_nRxIgnored uint16_t
#define _POSITION_bleAdvOutput_nRxBufFull 10
#define _TYPE_bleAdvOutput_nRxBufFull uint8_t
#define _POSITION_bleAdvOutput_lastRssi 11
#define _TYPE_bleAdvOutput_lastRssi int8_t
#define _POSITION_bleAdvOutput_timeStamp 12
#define _TYPE_bleAdvOutput_timeStamp ratmr_t
#define _SIZEOF_bleAdvOutput 16
#define _POSITION_bleScannerOutput_nTxScanReq 0
#define _TYPE_bleScannerOutput_nTxScanReq uint16_t
#define _POSITION_bleScannerOutput_nBackedOffScanReq 2
#define _TYPE_bleScannerOutput_nBackedOffScanReq uint16_t
#define _POSITION_bleScannerOutput_nRxAdvOk 4
#define _TYPE_bleScannerOutput_nRxAdvOk uint16_t
#define _POSITION_bleScannerOutput_nRxAdvIgnored 6
#define _TYPE_bleScannerOutput_nRxAdvIgnored uint16_t
#define _POSITION_bleScannerOutput_nRxAdvNok 8
#define _TYPE_bleScannerOutput_nRxAdvNok uint16_t
#define _POSITION_bleScannerOutput_nRxScanRspOk 10
#define _TYPE_bleScannerOutput_nRxScanRspOk uint16_t
#define _POSITION_bleScannerOutput_nRxScanRspIgnored 12
#define _TYPE_bleScannerOutput_nRxScanRspIgnored uint16_t
#define _POSITION_bleScannerOutput_nRxScanRspNok 14
#define _TYPE_bleScannerOutput_nRxScanRspNok uint16_t
#define _POSITION_bleScannerOutput_nRxAdvBufFull 16
#define _TYPE_bleScannerOutput_nRxAdvBufFull uint8_t
#define _POSITION_bleScannerOutput_nRxScanRspBufFull 17
#define _TYPE_bleScannerOutput_nRxScanRspBufFull uint8_t
#define _POSITION_bleScannerOutput_lastRssi 18
#define _TYPE_bleScannerOutput_lastRssi int8_t
#define _POSITION_bleScannerOutput_timeStamp 20
#define _TYPE_bleScannerOutput_timeStamp ratmr_t
#define _SIZEOF_bleScannerOutput 24
#define _POSITION_bleInitiatorOutput_nTxConnectReq 0
#define _TYPE_bleInitiatorOutput_nTxConnectReq uint8_t
#define _POSITION_bleInitiatorOutput_nRxAdvOk 1
#define _TYPE_bleInitiatorOutput_nRxAdvOk uint8_t
#define _POSITION_bleInitiatorOutput_nRxAdvIgnored 2
#define _TYPE_bleInitiatorOutput_nRxAdvIgnored uint16_t
#define _POSITION_bleInitiatorOutput_nRxAdvNok 4
#define _TYPE_bleInitiatorOutput_nRxAdvNok uint16_t
#define _POSITION_bleInitiatorOutput_nRxAdvBufFull 6
#define _TYPE_bleInitiatorOutput_nRxAdvBufFull uint8_t
#define _POSITION_bleInitiatorOutput_lastRssi 7
#define _TYPE_bleInitiatorOutput_lastRssi int8_t
#define _POSITION_bleInitiatorOutput_timeStamp 8
#define _TYPE_bleInitiatorOutput_timeStamp ratmr_t
#define _SIZEOF_bleInitiatorOutput 12
#define _POSITION_bleGenericRxOutput_nRxOk 0
#define _TYPE_bleGenericRxOutput_nRxOk uint16_t
#define _POSITION_bleGenericRxOutput_nRxNok 2
#define _TYPE_bleGenericRxOutput_nRxNok uint16_t
#define _POSITION_bleGenericRxOutput_nRxBufFull 4
#define _TYPE_bleGenericRxOutput_nRxBufFull uint16_t
#define _POSITION_bleGenericRxOutput_lastRssi 6
#define _TYPE_bleGenericRxOutput_lastRssi int8_t
#define _POSITION_bleGenericRxOutput_timeStamp 8
#define _TYPE_bleGenericRxOutput_timeStamp ratmr_t
#define _SIZEOF_bleGenericRxOutput 12
#define _POSITION_bleTxTestOutput_nTx 0
#define _TYPE_bleTxTestOutput_nTx uint16_t
#define _SIZEOF_bleTxTestOutput 2
#define _POSITION_bleWhiteListEntry_size 0
#define _TYPE_bleWhiteListEntry_size uint8_t
#define _POSITION_bleWhiteListEntry_conf 1
#define _TYPE_bleWhiteListEntry_conf uint8_t
#define _BITPOS_bleWhiteListEntry_conf_bEnable 0
#define _NBITS_bleWhiteListEntry_conf_bEnable 1
#define _BITPOS_bleWhiteListEntry_conf_addrType 1
#define _NBITS_bleWhiteListEntry_conf_addrType 1
#define _BITPOS_bleWhiteListEntry_conf_bWlIgn 2
#define _NBITS_bleWhiteListEntry_conf_bWlIgn 1
#define _POSITION_bleWhiteListEntry_address 2
#define _TYPE_bleWhiteListEntry_address uint16_t
#define _POSITION_bleWhiteListEntry_addressHi 4
#define _TYPE_bleWhiteListEntry_addressHi uint32_t
#define _SIZEOF_bleWhiteListEntry 8
#define _POSITION_bleRxStatus_status 0
#define _TYPE_bleRxStatus_status uint8_t
#define _BITPOS_bleRxStatus_status_channel 0
#define _NBITS_bleRxStatus_status_channel 6
#define _BITPOS_bleRxStatus_status_bIgnore 6
#define _NBITS_bleRxStatus_status_bIgnore 1
#define _BITPOS_bleRxStatus_status_bCrcErr 7
#define _NBITS_bleRxStatus_status_bCrcErr 1
#define _SIZEOF_bleRxStatus 1
#endif

448
cpu/cc26xx/dev/rfc-api/common_cmd_field.h
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@ -1,448 +0,0 @@
/******************************************************************************
* Filename: common_cmd_field.h
* Revised: $ $
* Revision: $ $
*
* Description: CC26xx API for common/generic commands
*
* Copyright (C) 2015 Texas Instruments Incorporated - http://www.ti.com/
*
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* Neither the name of Texas Instruments Incorporated nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************/
#ifndef __COMMON_CMD_FIELD_H
#define __COMMON_CMD_FIELD_H
#include <stdint.h>
#include "mailbox.h"
#define _POSITION_command_commandNo 0
#define _TYPE_command_commandNo uint16_t
#define _SIZEOF_command 2
#define _POSITION_radioOp_commandNo 0
#define _TYPE_radioOp_commandNo uint16_t
#define _POSITION_radioOp_status 2
#define _TYPE_radioOp_status uint16_t
#define _POSITION_radioOp_pNextOp 4
#define _TYPE_radioOp_pNextOp uint8_t*
#define _POSITION_radioOp_startTime 8
#define _TYPE_radioOp_startTime ratmr_t
#define _POSITION_radioOp_startTrigger 12
#define _TYPE_radioOp_startTrigger uint8_t
#define _BITPOS_radioOp_startTrigger_triggerType 0
#define _NBITS_radioOp_startTrigger_triggerType 4
#define _BITPOS_radioOp_startTrigger_bEnaCmd 4
#define _NBITS_radioOp_startTrigger_bEnaCmd 1
#define _BITPOS_radioOp_startTrigger_triggerNo 5
#define _NBITS_radioOp_startTrigger_triggerNo 2
#define _BITPOS_radioOp_startTrigger_pastTrig 7
#define _NBITS_radioOp_startTrigger_pastTrig 1
#define _POSITION_radioOp_condition 13
#define _TYPE_radioOp_condition uint8_t
#define _BITPOS_radioOp_condition_rule 0
#define _NBITS_radioOp_condition_rule 4
#define _BITPOS_radioOp_condition_nSkip 4
#define _NBITS_radioOp_condition_nSkip 4
#define _SIZEOF_radioOp 14
#define _SIZEOF_CMD_NOP 14
#define _POSITION_CMD_RADIO_SETUP_mode 14
#define _TYPE_CMD_RADIO_SETUP_mode uint8_t
#define _POSITION_CMD_RADIO_SETUP_config 16
#define _TYPE_CMD_RADIO_SETUP_config uint16_t
#define _BITPOS_CMD_RADIO_SETUP_config_frontEndMode 0
#define _NBITS_CMD_RADIO_SETUP_config_frontEndMode 3
#define _BITPOS_CMD_RADIO_SETUP_config_biasMode 3
#define _NBITS_CMD_RADIO_SETUP_config_biasMode 1
#define _BITPOS_CMD_RADIO_SETUP_config_bNoAdi0Setup 4
#define _NBITS_CMD_RADIO_SETUP_config_bNoAdi0Setup 1
#define _BITPOS_CMD_RADIO_SETUP_config_bNoAdi0Trim 5
#define _NBITS_CMD_RADIO_SETUP_config_bNoAdi0Trim 1
#define _BITPOS_CMD_RADIO_SETUP_config_bNoAdi0Ovr 6
#define _NBITS_CMD_RADIO_SETUP_config_bNoAdi0Ovr 1
#define _BITPOS_CMD_RADIO_SETUP_config_bNoAdi1Setup 7
#define _NBITS_CMD_RADIO_SETUP_config_bNoAdi1Setup 1
#define _BITPOS_CMD_RADIO_SETUP_config_bNoAdi1Trim 8
#define _NBITS_CMD_RADIO_SETUP_config_bNoAdi1Trim 1
#define _BITPOS_CMD_RADIO_SETUP_config_bNoAdi1Ovr 9
#define _NBITS_CMD_RADIO_SETUP_config_bNoAdi1Ovr 1
#define _BITPOS_CMD_RADIO_SETUP_config_bNoFsPowerUp 10
#define _NBITS_CMD_RADIO_SETUP_config_bNoFsPowerUp 1
#define _POSITION_CMD_RADIO_SETUP_txPower 18
#define _TYPE_CMD_RADIO_SETUP_txPower uint16_t
#define _BITPOS_CMD_RADIO_SETUP_txPower_IB 0
#define _NBITS_CMD_RADIO_SETUP_txPower_IB 6
#define _BITPOS_CMD_RADIO_SETUP_txPower_GC 6
#define _NBITS_CMD_RADIO_SETUP_txPower_GC 2
#define _BITPOS_CMD_RADIO_SETUP_txPower_tempCoeff 8
#define _NBITS_CMD_RADIO_SETUP_txPower_tempCoeff 8
#define _POSITION_CMD_RADIO_SETUP_pRegOverride 20
#define _TYPE_CMD_RADIO_SETUP_pRegOverride uint32_t*
#define _SIZEOF_CMD_RADIO_SETUP 24
#define _POSITION_CMD_FS_frequency 14
#define _TYPE_CMD_FS_frequency uint16_t
#define _POSITION_CMD_FS_fractFreq 16
#define _TYPE_CMD_FS_fractFreq uint16_t
#define _POSITION_CMD_FS_synthConf 18
#define _TYPE_CMD_FS_synthConf uint8_t
#define _BITPOS_CMD_FS_synthConf_bTxMode 0
#define _NBITS_CMD_FS_synthConf_bTxMode 1
#define _BITPOS_CMD_FS_synthConf_refFreq 1
#define _NBITS_CMD_FS_synthConf_refFreq 6
#define _POSITION_CMD_FS_calibConf 19
#define _TYPE_CMD_FS_calibConf uint8_t
#define _BITPOS_CMD_FS_calibConf_bOverrideCalib 0
#define _NBITS_CMD_FS_calibConf_bOverrideCalib 1
#define _BITPOS_CMD_FS_calibConf_bSkipTdcCalib 1
#define _NBITS_CMD_FS_calibConf_bSkipTdcCalib 1
#define _BITPOS_CMD_FS_calibConf_bSkipCoarseCalib 2
#define _NBITS_CMD_FS_calibConf_bSkipCoarseCalib 1
#define _BITPOS_CMD_FS_calibConf_bSkipMidCalib 3
#define _NBITS_CMD_FS_calibConf_bSkipMidCalib 1
#define _BITPOS_CMD_FS_calibConf_coarsePrecal 4
#define _NBITS_CMD_FS_calibConf_coarsePrecal 4
#define _POSITION_CMD_FS_midPrecal 20
#define _TYPE_CMD_FS_midPrecal uint8_t
#define _POSITION_CMD_FS_ktPrecal 21
#define _TYPE_CMD_FS_ktPrecal uint8_t
#define _POSITION_CMD_FS_tdcPrecal 22
#define _TYPE_CMD_FS_tdcPrecal uint16_t
#define _SIZEOF_CMD_FS 24
#define _SIZEOF_CMD_FS_OFF 14
#define _POSITION_CMD_RX_pktConfig 14
#define _TYPE_CMD_RX_pktConfig uint16_t
#define _BITPOS_CMD_RX_pktConfig_endianness 0
#define _NBITS_CMD_RX_pktConfig_endianness 1
#define _BITPOS_CMD_RX_pktConfig_numHdrBits 1
#define _NBITS_CMD_RX_pktConfig_numHdrBits 6
#define _BITPOS_CMD_RX_pktConfig_bFsOff 7
#define _NBITS_CMD_RX_pktConfig_bFsOff 1
#define _BITPOS_CMD_RX_pktConfig_bUseCrc 8
#define _NBITS_CMD_RX_pktConfig_bUseCrc 1
#define _BITPOS_CMD_RX_pktConfig_bCrcIncSw 9
#define _NBITS_CMD_RX_pktConfig_bCrcIncSw 1
#define _BITPOS_CMD_RX_pktConfig_bCrcIncHdr 10
#define _NBITS_CMD_RX_pktConfig_bCrcIncHdr 1
#define _BITPOS_CMD_RX_pktConfig_bReportCrc 11
#define _NBITS_CMD_RX_pktConfig_bReportCrc 1
#define _BITPOS_CMD_RX_pktConfig_endType 12
#define _NBITS_CMD_RX_pktConfig_endType 1
#define _BITPOS_CMD_RX_pktConfig_bDualSw 13
#define _NBITS_CMD_RX_pktConfig_bDualSw 1
#define _POSITION_CMD_RX_syncWord 16
#define _TYPE_CMD_RX_syncWord uint32_t
#define _POSITION_CMD_RX_syncWord2 20
#define _TYPE_CMD_RX_syncWord2 uint32_t
#define _POSITION_CMD_RX_lenConfig 24
#define _TYPE_CMD_RX_lenConfig uint16_t
#define _BITPOS_CMD_RX_lenConfig_numLenBits 0
#define _NBITS_CMD_RX_lenConfig_numLenBits 4
#define _BITPOS_CMD_RX_lenConfig_lenFieldPos 4
#define _NBITS_CMD_RX_lenConfig_lenFieldPos 5
#define _BITPOS_CMD_RX_lenConfig_lenOffset 9
#define _NBITS_CMD_RX_lenConfig_lenOffset 7
#define _POSITION_CMD_RX_maxLen 26
#define _TYPE_CMD_RX_maxLen uint16_t
#define _POSITION_CMD_RX_pRecPkt 28
#define _TYPE_CMD_RX_pRecPkt uint8_t*
#define _POSITION_CMD_RX_endTime 32
#define _TYPE_CMD_RX_endTime ratmr_t
#define _POSITION_CMD_RX_endTrigger 36
#define _TYPE_CMD_RX_endTrigger uint8_t
#define _BITPOS_CMD_RX_endTrigger_triggerType 0
#define _NBITS_CMD_RX_endTrigger_triggerType 4
#define _BITPOS_CMD_RX_endTrigger_bEnaCmd 4
#define _NBITS_CMD_RX_endTrigger_bEnaCmd 1
#define _BITPOS_CMD_RX_endTrigger_triggerNo 5
#define _NBITS_CMD_RX_endTrigger_triggerNo 2
#define _BITPOS_CMD_RX_endTrigger_pastTrig 7
#define _NBITS_CMD_RX_endTrigger_pastTrig 1
#define _POSITION_CMD_RX_rssi 37
#define _TYPE_CMD_RX_rssi int8_t
#define _POSITION_CMD_RX_recLen 38
#define _TYPE_CMD_RX_recLen uint16_t
#define _POSITION_CMD_RX_timeStamp 40
#define _TYPE_CMD_RX_timeStamp ratmr_t
#define _POSITION_CMD_RX_nRxOk 44
#define _TYPE_CMD_RX_nRxOk uint16_t
#define _POSITION_CMD_RX_nRxNok 46
#define _TYPE_CMD_RX_nRxNok uint16_t
#define _POSITION_CMD_RX_nRx2Ok 48
#define _TYPE_CMD_RX_nRx2Ok uint16_t
#define _POSITION_CMD_RX_nRx2Nok 50
#define _TYPE_CMD_RX_nRx2Nok uint16_t
#define _SIZEOF_CMD_RX 52
#define _POSITION_CMD_TX_pktConfig 14
#define _TYPE_CMD_TX_pktConfig uint16_t
#define _BITPOS_CMD_TX_pktConfig_endianness 0
#define _NBITS_CMD_TX_pktConfig_endianness 1
#define _BITPOS_CMD_TX_pktConfig_numHdrBits 1
#define _NBITS_CMD_TX_pktConfig_numHdrBits 6
#define _BITPOS_CMD_TX_pktConfig_bFsOff 7
#define _NBITS_CMD_TX_pktConfig_bFsOff 1
#define _BITPOS_CMD_TX_pktConfig_bUseCrc 8
#define _NBITS_CMD_TX_pktConfig_bUseCrc 1
#define _BITPOS_CMD_TX_pktConfig_bCrcIncSw 9
#define _NBITS_CMD_TX_pktConfig_bCrcIncSw 1
#define _BITPOS_CMD_TX_pktConfig_bCrcIncHdr 10
#define _NBITS_CMD_TX_pktConfig_bCrcIncHdr 1
#define _POSITION_CMD_TX_syncWord 16
#define _TYPE_CMD_TX_syncWord uint32_t
#define _POSITION_CMD_TX_pTxPkt 20
#define _TYPE_CMD_TX_pTxPkt uint8_t*
#define _POSITION_CMD_TX_pktLen 24
#define _TYPE_CMD_TX_pktLen uint16_t
#define _SIZEOF_CMD_TX 26
#define _POSITION_CMD_RX_TEST_config 14
#define _TYPE_CMD_RX_TEST_config uint8_t
#define _BITPOS_CMD_RX_TEST_config_bEnaFifo 0
#define _NBITS_CMD_RX_TEST_config_bEnaFifo 1
#define _BITPOS_CMD_RX_TEST_config_bFsOff 1
#define _NBITS_CMD_RX_TEST_config_bFsOff 1
#define _BITPOS_CMD_RX_TEST_config_bNoSync 2
#define _NBITS_CMD_RX_TEST_config_bNoSync 1
#define _POSITION_CMD_RX_TEST_endTrigger 15
#define _TYPE_CMD_RX_TEST_endTrigger uint8_t
#define _BITPOS_CMD_RX_TEST_endTrigger_triggerType 0
#define _NBITS_CMD_RX_TEST_endTrigger_triggerType 4
#define _BITPOS_CMD_RX_TEST_endTrigger_bEnaCmd 4
#define _NBITS_CMD_RX_TEST_endTrigger_bEnaCmd 1
#define _BITPOS_CMD_RX_TEST_endTrigger_triggerNo 5
#define _NBITS_CMD_RX_TEST_endTrigger_triggerNo 2
#define _BITPOS_CMD_RX_TEST_endTrigger_pastTrig 7
#define _NBITS_CMD_RX_TEST_endTrigger_pastTrig 1
#define _POSITION_CMD_RX_TEST_syncWord 16
#define _TYPE_CMD_RX_TEST_syncWord uint32_t
#define _POSITION_CMD_RX_TEST_endTime 20
#define _TYPE_CMD_RX_TEST_endTime ratmr_t
#define _SIZEOF_CMD_RX_TEST 24
#define _POSITION_CMD_TX_TEST_config 14
#define _TYPE_CMD_TX_TEST_config uint8_t
#define _BITPOS_CMD_TX_TEST_config_bUseCw 0
#define _NBITS_CMD_TX_TEST_config_bUseCw 1
#define _BITPOS_CMD_TX_TEST_config_bFsOff 1
#define _NBITS_CMD_TX_TEST_config_bFsOff 1
#define _BITPOS_CMD_TX_TEST_config_whitenMode 2
#define _NBITS_CMD_TX_TEST_config_whitenMode 2
#define _POSITION_CMD_TX_TEST_txWord 16
#define _TYPE_CMD_TX_TEST_txWord uint16_t
#define _POSITION_CMD_TX_TEST_endTrigger 19
#define _TYPE_CMD_TX_TEST_endTrigger uint8_t
#define _BITPOS_CMD_TX_TEST_endTrigger_triggerType 0
#define _NBITS_CMD_TX_TEST_endTrigger_triggerType 4
#define _BITPOS_CMD_TX_TEST_endTrigger_bEnaCmd 4
#define _NBITS_CMD_TX_TEST_endTrigger_bEnaCmd 1
#define _BITPOS_CMD_TX_TEST_endTrigger_triggerNo 5
#define _NBITS_CMD_TX_TEST_endTrigger_triggerNo 2
#define _BITPOS_CMD_TX_TEST_endTrigger_pastTrig 7
#define _NBITS_CMD_TX_TEST_endTrigger_pastTrig 1
#define _POSITION_CMD_TX_TEST_syncWord 20
#define _TYPE_CMD_TX_TEST_syncWord uint32_t
#define _POSITION_CMD_TX_TEST_endTime 24
#define _TYPE_CMD_TX_TEST_endTime ratmr_t
#define _SIZEOF_CMD_TX_TEST 28
#define _POSITION_CMD_SYNC_STOP_RAT_rat0 16
#define _TYPE_CMD_SYNC_STOP_RAT_rat0 ratmr_t
#define _SIZEOF_CMD_SYNC_STOP_RAT 20
#define _POSITION_CMD_SYNC_START_RAT_rat0 16
#define _TYPE_CMD_SYNC_START_RAT_rat0 ratmr_t
#define _SIZEOF_CMD_SYNC_START_RAT 20
#define _POSITION_CMD_COUNT_counter 14
#define _TYPE_CMD_COUNT_counter uint16_t
#define _SIZEOF_CMD_COUNT 16
#define _POSITION_CMD_FS_POWERUP_pRegOverride 16
#define _TYPE_CMD_FS_POWERUP_pRegOverride uint32_t*
#define _SIZEOF_CMD_FS_POWERUP 20
#define _SIZEOF_CMD_FS_POWERDOWN 14
#define _POSITION_CMD_SCH_IMM_cmdrVal 16
#define _TYPE_CMD_SCH_IMM_cmdrVal uint32_t
#define _POSITION_CMD_SCH_IMM_cmdstaVal 20
#define _TYPE_CMD_SCH_IMM_cmdstaVal uint32_t
#define _SIZEOF_CMD_SCH_IMM 24
#define _POSITION_CMD_COUNT_BRANCH_counter 14
#define _TYPE_CMD_COUNT_BRANCH_counter uint16_t
#define _POSITION_CMD_COUNT_BRANCH_pNextOpIfOk 16
#define _TYPE_CMD_COUNT_BRANCH_pNextOpIfOk uint8_t*
#define _SIZEOF_CMD_COUNT_BRANCH 20
#define _POSITION_CMD_PATTERN_CHECK_patternOpt 14
#define _TYPE_CMD_PATTERN_CHECK_patternOpt uint16_t
#define _BITPOS_CMD_PATTERN_CHECK_patternOpt_operation 0
#define _NBITS_CMD_PATTERN_CHECK_patternOpt_operation 2
#define _BITPOS_CMD_PATTERN_CHECK_patternOpt_bByteRev 2
#define _NBITS_CMD_PATTERN_CHECK_patternOpt_bByteRev 1
#define _BITPOS_CMD_PATTERN_CHECK_patternOpt_bBitRev 3
#define _NBITS_CMD_PATTERN_CHECK_patternOpt_bBitRev 1
#define _BITPOS_CMD_PATTERN_CHECK_patternOpt_signExtend 4
#define _NBITS_CMD_PATTERN_CHECK_patternOpt_signExtend 5
#define _BITPOS_CMD_PATTERN_CHECK_patternOpt_bRxVal 9
#define _NBITS_CMD_PATTERN_CHECK_patternOpt_bRxVal 1
#define _POSITION_CMD_PATTERN_CHECK_pNextOpIfOk 16
#define _TYPE_CMD_PATTERN_CHECK_pNextOpIfOk uint8_t*
#define _POSITION_CMD_PATTERN_CHECK_pValue 20
#define _TYPE_CMD_PATTERN_CHECK_pValue uint8_t*
#define _POSITION_CMD_PATTERN_CHECK_mask 24
#define _TYPE_CMD_PATTERN_CHECK_mask uint32_t
#define _POSITION_CMD_PATTERN_CHECK_compareVal 28
#define _TYPE_CMD_PATTERN_CHECK_compareVal uint32_t
#define _SIZEOF_CMD_PATTERN_CHECK 32
#define _SIZEOF_CMD_ABORT 2
#define _SIZEOF_CMD_STOP 2
#define _SIZEOF_CMD_GET_RSSI 2
#define _POSITION_CMD_UPDATE_RADIO_SETUP_pRegOverride 4
#define _TYPE_CMD_UPDATE_RADIO_SETUP_pRegOverride uint32_t*
#define _SIZEOF_CMD_UPDATE_RADIO_SETUP 8
#define _POSITION_CMD_TRIGGER_triggerNo 2
#define _TYPE_CMD_TRIGGER_triggerNo uint8_t
#define _SIZEOF_CMD_TRIGGER 3
#define _POSITION_CMD_GET_FW_INFO_versionNo 2
#define _TYPE_CMD_GET_FW_INFO_versionNo uint16_t
#define _POSITION_CMD_GET_FW_INFO_startOffset 4
#define _TYPE_CMD_GET_FW_INFO_startOffset uint16_t
#define _POSITION_CMD_GET_FW_INFO_freeRamSz 6
#define _TYPE_CMD_GET_FW_INFO_freeRamSz uint16_t
#define _POSITION_CMD_GET_FW_INFO_availRatCh 8
#define _TYPE_CMD_GET_FW_INFO_availRatCh uint16_t
#define _SIZEOF_CMD_GET_FW_INFO 10
#define _SIZEOF_CMD_START_RAT 2
#define _SIZEOF_CMD_PING 2
#define _POSITION_CMD_ADD_DATA_ENTRY_pQueue 4
#define _TYPE_CMD_ADD_DATA_ENTRY_pQueue dataQueue_t*
#define _POSITION_CMD_ADD_DATA_ENTRY_pEntry 8
#define _TYPE_CMD_ADD_DATA_ENTRY_pEntry uint8_t*
#define _SIZEOF_CMD_ADD_DATA_ENTRY 12
#define _POSITION_CMD_REMOVE_DATA_ENTRY_pQueue 4
#define _TYPE_CMD_REMOVE_DATA_ENTRY_pQueue dataQueue_t*
#define _POSITION_CMD_REMOVE_DATA_ENTRY_pEntry 8
#define _TYPE_CMD_REMOVE_DATA_ENTRY_pEntry uint8_t*
#define _SIZEOF_CMD_REMOVE_DATA_ENTRY 12
#define _POSITION_CMD_FLUSH_QUEUE_pQueue 4
#define _TYPE_CMD_FLUSH_QUEUE_pQueue dataQueue_t*
#define _POSITION_CMD_FLUSH_QUEUE_pFirstEntry 8
#define _TYPE_CMD_FLUSH_QUEUE_pFirstEntry uint8_t*
#define _SIZEOF_CMD_FLUSH_QUEUE 12
#define _POSITION_CMD_CLEAR_RX_pQueue 4
#define _TYPE_CMD_CLEAR_RX_pQueue dataQueue_t*
#define _SIZEOF_CMD_CLEAR_RX 8
#define _POSITION_CMD_REMOVE_PENDING_ENTRIES_pQueue 4
#define _TYPE_CMD_REMOVE_PENDING_ENTRIES_pQueue dataQueue_t*
#define _POSITION_CMD_REMOVE_PENDING_ENTRIES_pFirstEntry 8
#define _TYPE_CMD_REMOVE_PENDING_ENTRIES_pFirstEntry uint8_t*
#define _SIZEOF_CMD_REMOVE_PENDING_ENTRIES 12
#define _POSITION_CMD_SET_RAT_CMP_ratCh 2
#define _TYPE_CMD_SET_RAT_CMP_ratCh uint8_t
#define _POSITION_CMD_SET_RAT_CMP_compareTime 4
#define _TYPE_CMD_SET_RAT_CMP_compareTime ratmr_t
#define _SIZEOF_CMD_SET_RAT_CMP 8
#define _POSITION_CMD_SET_RAT_CPT_config 2
#define _TYPE_CMD_SET_RAT_CPT_config uint16_t
#define _BITPOS_CMD_SET_RAT_CPT_config_inputSrc 3
#define _NBITS_CMD_SET_RAT_CPT_config_inputSrc 5
#define _BITPOS_CMD_SET_RAT_CPT_config_ratCh 8
#define _NBITS_CMD_SET_RAT_CPT_config_ratCh 4
#define _BITPOS_CMD_SET_RAT_CPT_config_bRepeated 12
#define _NBITS_CMD_SET_RAT_CPT_config_bRepeated 1
#define _BITPOS_CMD_SET_RAT_CPT_config_inputMode 13
#define _NBITS_CMD_SET_RAT_CPT_config_inputMode 2
#define _SIZEOF_CMD_SET_RAT_CPT 4
#define _POSITION_CMD_DISABLE_RAT_CH_ratCh 2
#define _TYPE_CMD_DISABLE_RAT_CH_ratCh uint8_t
#define _SIZEOF_CMD_DISABLE_RAT_CH 3
#define _POSITION_CMD_SET_RAT_OUTPUT_config 2
#define _TYPE_CMD_SET_RAT_OUTPUT_config uint16_t
#define _BITPOS_CMD_SET_RAT_OUTPUT_config_outputSel 2
#define _NBITS_CMD_SET_RAT_OUTPUT_config_outputSel 3
#define _BITPOS_CMD_SET_RAT_OUTPUT_config_outputMode 5
#define _NBITS_CMD_SET_RAT_OUTPUT_config_outputMode 3
#define _BITPOS_CMD_SET_RAT_OUTPUT_config_ratCh 8
#define _NBITS_CMD_SET_RAT_OUTPUT_config_ratCh 4
#define _SIZEOF_CMD_SET_RAT_OUTPUT 4
#define _POSITION_CMD_ARM_RAT_CH_ratCh 2
#define _TYPE_CMD_ARM_RAT_CH_ratCh uint8_t
#define _SIZEOF_CMD_ARM_RAT_CH 3
#define _POSITION_CMD_DISARM_RAT_CH_ratCh 2
#define _TYPE_CMD_DISARM_RAT_CH_ratCh uint8_t
#define _SIZEOF_CMD_DISARM_RAT_CH 3
#define _POSITION_CMD_SET_TX_POWER_txPower 2
#define _TYPE_CMD_SET_TX_POWER_txPower uint16_t
#define _BITPOS_CMD_SET_TX_POWER_txPower_IB 0
#define _NBITS_CMD_SET_TX_POWER_txPower_IB 6
#define _BITPOS_CMD_SET_TX_POWER_txPower_GC 6
#define _NBITS_CMD_SET_TX_POWER_txPower_GC 2
#define _BITPOS_CMD_SET_TX_POWER_txPower_tempCoeff 8
#define _NBITS_CMD_SET_TX_POWER_txPower_tempCoeff 8
#define _SIZEOF_CMD_SET_TX_POWER 4
#define _POSITION_CMD_UPDATE_FS_frequency 2
#define _TYPE_CMD_UPDATE_FS_frequency uint16_t
#define _POSITION_CMD_UPDATE_FS_fractFreq 4
#define _TYPE_CMD_UPDATE_FS_fractFreq uint16_t
#define _SIZEOF_CMD_UPDATE_FS 6
#define _POSITION_CMD_BUS_REQUEST_bSysBusNeeded 2
#define _TYPE_CMD_BUS_REQUEST_bSysBusNeeded uint8_t
#define _SIZEOF_CMD_BUS_REQUEST 3
#endif

91
cpu/cc26xx/dev/rfc-api/data_entry.h
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@ -1,91 +0,0 @@
/*
* Copyright (c) 2014, Texas Instruments Incorporated - http://www.ti.com/
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. Neither the name of the copyright holder nor the names of its
* contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
* OF THE POSSIBILITY OF SUCH DAMAGE.
*/
/*---------------------------------------------------------------------------*/
#ifndef __DATA_ENTRY_H
#define __DATA_ENTRY_H
#include <stdint.h>
#include "mailbox.h"
typedef struct rfc_dataEntry_s rfc_dataEntry_t;
#define _POSITION_dataEntry_pNextEntry 0
#define _TYPE_dataEntry_pNextEntry uint8_t*
#define _POSITION_dataEntry_status 4
#define _TYPE_dataEntry_status uint8_t
#define _POSITION_dataEntry_config 5
#define _TYPE_dataEntry_config uint8_t
#define _BITPOS_dataEntry_config_type 0
#define _NBITS_dataEntry_config_type 2
#define _BITPOS_dataEntry_config_lenSz 2
#define _NBITS_dataEntry_config_lenSz 2
#define _BITPOS_dataEntry_config_irqIntv 4
#define _NBITS_dataEntry_config_irqIntv 4
#define _POSITION_dataEntry_length 6
#define _TYPE_dataEntry_length uint16_t
#define _POSITION_dataEntry_data 8
#define _TYPE_dataEntry_data uint8_t
#define _POSITION_dataEntry_pData 8
#define _TYPE_dataEntry_pData uint8_t*
#define _POSITION_dataEntry_numElements 8
#define _TYPE_dataEntry_numElements uint16_t
#define _POSITION_dataEntry_pktStatus 8
#define _TYPE_dataEntry_pktStatus uint16_t
#define _BITPOS_dataEntry_pktStatus_numElements 0
#define _NBITS_dataEntry_pktStatus_numElements 13
#define _BITPOS_dataEntry_pktStatus_bEntryOpen 13
#define _NBITS_dataEntry_pktStatus_bEntryOpen 1
#define _BITPOS_dataEntry_pktStatus_bFirstCont 14
#define _NBITS_dataEntry_pktStatus_bFirstCont 1
#define _BITPOS_dataEntry_pktStatus_bLastCont 15
#define _NBITS_dataEntry_pktStatus_bLastCont 1
#define _POSITION_dataEntry_nextIndex 10
#define _TYPE_dataEntry_nextIndex uint16_t
#define _POSITION_dataEntry_rxData 12
#define _TYPE_dataEntry_rxData uint8_t
#define _LAST_POSITION_dataEntry 12
#define _LAST_TYPE_dataEntry uint8_t
struct rfc_dataEntry_s {
uint8_t* pNextEntry;
uint8_t status;
struct {
uint8_t type:2;
uint8_t lenSz:2;
uint8_t irqIntv:4;
} config;
uint16_t length;
uint8_t data;
uint8_t __dummy0;
uint16_t nextIndex;
uint8_t rxData;
};
#endif

403
cpu/cc26xx/dev/rfc-api/ieee_cmd_field.h
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@ -1,403 +0,0 @@
/******************************************************************************
* Filename: ieee_cmd_field.h
* Revised: $ $
* Revision: $ $
*
* Description: CC26xx/CC13xx API for IEEE 802.15.4 commands
*
* Copyright (C) 2015 Texas Instruments Incorporated - http://www.ti.com/
*
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* Neither the name of Texas Instruments Incorporated nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************/
#ifndef __IEEE_CMD_FIELD_H
#define __IEEE_CMD_FIELD_H
#include <stdint.h>
#include "mailbox.h"
#include "common_cmd.h"
#define _POSITION_CMD_IEEE_RX_channel 14
#define _TYPE_CMD_IEEE_RX_channel uint8_t
#define _POSITION_CMD_IEEE_RX_rxConfig 15
#define _TYPE_CMD_IEEE_RX_rxConfig uint8_t
#define _BITPOS_CMD_IEEE_RX_rxConfig_bAutoFlushCrc 0
#define _NBITS_CMD_IEEE_RX_rxConfig_bAutoFlushCrc 1
#define _BITPOS_CMD_IEEE_RX_rxConfig_bAutoFlushIgn 1
#define _NBITS_CMD_IEEE_RX_rxConfig_bAutoFlushIgn 1
#define _BITPOS_CMD_IEEE_RX_rxConfig_bIncludePhyHdr 2
#define _NBITS_CMD_IEEE_RX_rxConfig_bIncludePhyHdr 1
#define _BITPOS_CMD_IEEE_RX_rxConfig_bIncludeCrc 3
#define _NBITS_CMD_IEEE_RX_rxConfig_bIncludeCrc 1
#define _BITPOS_CMD_IEEE_RX_rxConfig_bAppendRssi 4
#define _NBITS_CMD_IEEE_RX_rxConfig_bAppendRssi 1
#define _BITPOS_CMD_IEEE_RX_rxConfig_bAppendCorrCrc 5
#define _NBITS_CMD_IEEE_RX_rxConfig_bAppendCorrCrc 1
#define _BITPOS_CMD_IEEE_RX_rxConfig_bAppendSrcInd 6
#define _NBITS_CMD_IEEE_RX_rxConfig_bAppendSrcInd 1
#define _BITPOS_CMD_IEEE_RX_rxConfig_bAppendTimestamp 7
#define _NBITS_CMD_IEEE_RX_rxConfig_bAppendTimestamp 1
#define _POSITION_CMD_IEEE_RX_pRxQ 16
#define _TYPE_CMD_IEEE_RX_pRxQ dataQueue_t*
#define _POSITION_CMD_IEEE_RX_pOutput 20
#define _TYPE_CMD_IEEE_RX_pOutput uint8_t*
#define _POSITION_CMD_IEEE_RX_frameFiltOpt 24
#define _TYPE_CMD_IEEE_RX_frameFiltOpt uint16_t
#define _BITPOS_CMD_IEEE_RX_frameFiltOpt_frameFiltEn 0
#define _NBITS_CMD_IEEE_RX_frameFiltOpt_frameFiltEn 1
#define _BITPOS_CMD_IEEE_RX_frameFiltOpt_frameFiltStop 1
#define _NBITS_CMD_IEEE_RX_frameFiltOpt_frameFiltStop 1
#define _BITPOS_CMD_IEEE_RX_frameFiltOpt_autoAckEn 2
#define _NBITS_CMD_IEEE_RX_frameFiltOpt_autoAckEn 1
#define _BITPOS_CMD_IEEE_RX_frameFiltOpt_slottedAckEn 3
#define _NBITS_CMD_IEEE_RX_frameFiltOpt_slottedAckEn 1
#define _BITPOS_CMD_IEEE_RX_frameFiltOpt_autoPendEn 4
#define _NBITS_CMD_IEEE_RX_frameFiltOpt_autoPendEn 1
#define _BITPOS_CMD_IEEE_RX_frameFiltOpt_defaultPend 5
#define _NBITS_CMD_IEEE_RX_frameFiltOpt_defaultPend 1
#define _BITPOS_CMD_IEEE_RX_frameFiltOpt_bPendDataReqOnly 6
#define _NBITS_CMD_IEEE_RX_frameFiltOpt_bPendDataReqOnly 1
#define _BITPOS_CMD_IEEE_RX_frameFiltOpt_bPanCoord 7
#define _NBITS_CMD_IEEE_RX_frameFiltOpt_bPanCoord 1
#define _BITPOS_CMD_IEEE_RX_frameFiltOpt_maxFrameVersion 8
#define _NBITS_CMD_IEEE_RX_frameFiltOpt_maxFrameVersion 2
#define _BITPOS_CMD_IEEE_RX_frameFiltOpt_fcfReservedMask 10
#define _NBITS_CMD_IEEE_RX_frameFiltOpt_fcfReservedMask 3
#define _BITPOS_CMD_IEEE_RX_frameFiltOpt_modifyFtFilter 13
#define _NBITS_CMD_IEEE_RX_frameFiltOpt_modifyFtFilter 2
#define _BITPOS_CMD_IEEE_RX_frameFiltOpt_bStrictLenFilter 15
#define _NBITS_CMD_IEEE_RX_frameFiltOpt_bStrictLenFilter 1
#define _POSITION_CMD_IEEE_RX_frameTypes 26
#define _TYPE_CMD_IEEE_RX_frameTypes uint8_t
#define _BITPOS_CMD_IEEE_RX_frameTypes_bAcceptFt0Beacon 0
#define _NBITS_CMD_IEEE_RX_frameTypes_bAcceptFt0Beacon 1
#define _BITPOS_CMD_IEEE_RX_frameTypes_bAcceptFt1Data 1
#define _NBITS_CMD_IEEE_RX_frameTypes_bAcceptFt1Data 1
#define _BITPOS_CMD_IEEE_RX_frameTypes_bAcceptFt2Ack 2
#define _NBITS_CMD_IEEE_RX_frameTypes_bAcceptFt2Ack 1
#define _BITPOS_CMD_IEEE_RX_frameTypes_bAcceptFt3MacCmd 3
#define _NBITS_CMD_IEEE_RX_frameTypes_bAcceptFt3MacCmd 1
#define _BITPOS_CMD_IEEE_RX_frameTypes_bAcceptFt4Reserved 4
#define _NBITS_CMD_IEEE_RX_frameTypes_bAcceptFt4Reserved 1
#define _BITPOS_CMD_IEEE_RX_frameTypes_bAcceptFt5Reserved 5
#define _NBITS_CMD_IEEE_RX_frameTypes_bAcceptFt5Reserved 1
#define _BITPOS_CMD_IEEE_RX_frameTypes_bAcceptFt6Reserved 6
#define _NBITS_CMD_IEEE_RX_frameTypes_bAcceptFt6Reserved 1
#define _BITPOS_CMD_IEEE_RX_frameTypes_bAcceptFt7Reserved 7
#define _NBITS_CMD_IEEE_RX_frameTypes_bAcceptFt7Reserved 1
#define _POSITION_CMD_IEEE_RX_ccaOpt 27
#define _TYPE_CMD_IEEE_RX_ccaOpt uint8_t
#define _BITPOS_CMD_IEEE_RX_ccaOpt_ccaEnEnergy 0
#define _NBITS_CMD_IEEE_RX_ccaOpt_ccaEnEnergy 1
#define _BITPOS_CMD_IEEE_RX_ccaOpt_ccaEnCorr 1
#define _NBITS_CMD_IEEE_RX_ccaOpt_ccaEnCorr 1
#define _BITPOS_CMD_IEEE_RX_ccaOpt_ccaEnSync 2
#define _NBITS_CMD_IEEE_RX_ccaOpt_ccaEnSync 1
#define _BITPOS_CMD_IEEE_RX_ccaOpt_ccaCorrOp 3
#define _NBITS_CMD_IEEE_RX_ccaOpt_ccaCorrOp 1
#define _BITPOS_CMD_IEEE_RX_ccaOpt_ccaSyncOp 4
#define _NBITS_CMD_IEEE_RX_ccaOpt_ccaSyncOp 1
#define _BITPOS_CMD_IEEE_RX_ccaOpt_ccaCorrThr 5
#define _NBITS_CMD_IEEE_RX_ccaOpt_ccaCorrThr 2
#define _POSITION_CMD_IEEE_RX_ccaRssiThr 28
#define _TYPE_CMD_IEEE_RX_ccaRssiThr int8_t
#define _POSITION_CMD_IEEE_RX_numExtEntries 30
#define _TYPE_CMD_IEEE_RX_numExtEntries uint8_t
#define _POSITION_CMD_IEEE_RX_numShortEntries 31
#define _TYPE_CMD_IEEE_RX_numShortEntries uint8_t
#define _POSITION_CMD_IEEE_RX_pExtEntryList 32
#define _TYPE_CMD_IEEE_RX_pExtEntryList uint32_t*
#define _POSITION_CMD_IEEE_RX_pShortEntryList 36
#define _TYPE_CMD_IEEE_RX_pShortEntryList uint32_t*
#define _POSITION_CMD_IEEE_RX_localExtAddr 40
#define _TYPE_CMD_IEEE_RX_localExtAddr uint64_t
#define _POSITION_CMD_IEEE_RX_localShortAddr 48
#define _TYPE_CMD_IEEE_RX_localShortAddr uint16_t
#define _POSITION_CMD_IEEE_RX_localPanID 50
#define _TYPE_CMD_IEEE_RX_localPanID uint16_t
#define _POSITION_CMD_IEEE_RX_endTrigger 55
#define _TYPE_CMD_IEEE_RX_endTrigger uint8_t
#define _BITPOS_CMD_IEEE_RX_endTrigger_triggerType 0
#define _NBITS_CMD_IEEE_RX_endTrigger_triggerType 4
#define _BITPOS_CMD_IEEE_RX_endTrigger_bEnaCmd 4
#define _NBITS_CMD_IEEE_RX_endTrigger_bEnaCmd 1
#define _BITPOS_CMD_IEEE_RX_endTrigger_triggerNo 5
#define _NBITS_CMD_IEEE_RX_endTrigger_triggerNo 2
#define _BITPOS_CMD_IEEE_RX_endTrigger_pastTrig 7
#define _NBITS_CMD_IEEE_RX_endTrigger_pastTrig 1
#define _POSITION_CMD_IEEE_RX_endTime 56
#define _TYPE_CMD_IEEE_RX_endTime ratmr_t
#define _SIZEOF_CMD_IEEE_RX 60
#define _POSITION_CMD_IEEE_ED_SCAN_channel 14
#define _TYPE_CMD_IEEE_ED_SCAN_channel uint8_t
#define _POSITION_CMD_IEEE_ED_SCAN_ccaOpt 15
#define _TYPE_CMD_IEEE_ED_SCAN_ccaOpt uint8_t
#define _BITPOS_CMD_IEEE_ED_SCAN_ccaOpt_ccaEnEnergy 0
#define _NBITS_CMD_IEEE_ED_SCAN_ccaOpt_ccaEnEnergy 1
#define _BITPOS_CMD_IEEE_ED_SCAN_ccaOpt_ccaEnCorr 1
#define _NBITS_CMD_IEEE_ED_SCAN_ccaOpt_ccaEnCorr 1
#define _BITPOS_CMD_IEEE_ED_SCAN_ccaOpt_ccaEnSync 2
#define _NBITS_CMD_IEEE_ED_SCAN_ccaOpt_ccaEnSync 1
#define _BITPOS_CMD_IEEE_ED_SCAN_ccaOpt_ccaCorrOp 3
#define _NBITS_CMD_IEEE_ED_SCAN_ccaOpt_ccaCorrOp 1
#define _BITPOS_CMD_IEEE_ED_SCAN_ccaOpt_ccaSyncOp 4
#define _NBITS_CMD_IEEE_ED_SCAN_ccaOpt_ccaSyncOp 1
#define _BITPOS_CMD_IEEE_ED_SCAN_ccaOpt_ccaCorrThr 5
#define _NBITS_CMD_IEEE_ED_SCAN_ccaOpt_ccaCorrThr 2
#define _POSITION_CMD_IEEE_ED_SCAN_ccaRssiThr 16
#define _TYPE_CMD_IEEE_ED_SCAN_ccaRssiThr int8_t
#define _POSITION_CMD_IEEE_ED_SCAN_maxRssi 18
#define _TYPE_CMD_IEEE_ED_SCAN_maxRssi int8_t
#define _POSITION_CMD_IEEE_ED_SCAN_endTrigger 19
#define _TYPE_CMD_IEEE_ED_SCAN_endTrigger uint8_t
#define _BITPOS_CMD_IEEE_ED_SCAN_endTrigger_triggerType 0
#define _NBITS_CMD_IEEE_ED_SCAN_endTrigger_triggerType 4
#define _BITPOS_CMD_IEEE_ED_SCAN_endTrigger_bEnaCmd 4
#define _NBITS_CMD_IEEE_ED_SCAN_endTrigger_bEnaCmd 1
#define _BITPOS_CMD_IEEE_ED_SCAN_endTrigger_triggerNo 5
#define _NBITS_CMD_IEEE_ED_SCAN_endTrigger_triggerNo 2
#define _BITPOS_CMD_IEEE_ED_SCAN_endTrigger_pastTrig 7
#define _NBITS_CMD_IEEE_ED_SCAN_endTrigger_pastTrig 1
#define _POSITION_CMD_IEEE_ED_SCAN_endTime 20
#define _TYPE_CMD_IEEE_ED_SCAN_endTime ratmr_t
#define _SIZEOF_CMD_IEEE_ED_SCAN 24
#define _POSITION_CMD_IEEE_TX_txOpt 14
#define _TYPE_CMD_IEEE_TX_txOpt uint8_t
#define _BITPOS_CMD_IEEE_TX_txOpt_bIncludePhyHdr 0
#define _NBITS_CMD_IEEE_TX_txOpt_bIncludePhyHdr 1
#define _BITPOS_CMD_IEEE_TX_txOpt_bIncludeCrc 1
#define _NBITS_CMD_IEEE_TX_txOpt_bIncludeCrc 1
#define _BITPOS_CMD_IEEE_TX_txOpt_payloadLenMsb 3
#define _NBITS_CMD_IEEE_TX_txOpt_payloadLenMsb 5
#define _POSITION_CMD_IEEE_TX_payloadLen 15
#define _TYPE_CMD_IEEE_TX_payloadLen uint8_t
#define _POSITION_CMD_IEEE_TX_pPayload 16
#define _TYPE_CMD_IEEE_TX_pPayload uint8_t*
#define _POSITION_CMD_IEEE_TX_timeStamp 20
#define _TYPE_CMD_IEEE_TX_timeStamp ratmr_t
#define _SIZEOF_CMD_IEEE_TX 24
#define _POSITION_CMD_IEEE_CSMA_randomState 14
#define _TYPE_CMD_IEEE_CSMA_randomState uint16_t
#define _POSITION_CMD_IEEE_CSMA_macMaxBE 16
#define _TYPE_CMD_IEEE_CSMA_macMaxBE uint8_t
#define _POSITION_CMD_IEEE_CSMA_macMaxCSMABackoffs 17
#define _TYPE_CMD_IEEE_CSMA_macMaxCSMABackoffs uint8_t
#define _POSITION_CMD_IEEE_CSMA_csmaConfig 18
#define _TYPE_CMD_IEEE_CSMA_csmaConfig uint8_t
#define _BITPOS_CMD_IEEE_CSMA_csmaConfig_initCW 0
#define _NBITS_CMD_IEEE_CSMA_csmaConfig_initCW 5
#define _BITPOS_CMD_IEEE_CSMA_csmaConfig_bSlotted 5
#define _NBITS_CMD_IEEE_CSMA_csmaConfig_bSlotted 1
#define _BITPOS_CMD_IEEE_CSMA_csmaConfig_rxOffMode 6
#define _NBITS_CMD_IEEE_CSMA_csmaConfig_rxOffMode 2
#define _POSITION_CMD_IEEE_CSMA_NB 19
#define _TYPE_CMD_IEEE_CSMA_NB uint8_t
#define _POSITION_CMD_IEEE_CSMA_BE 20
#define _TYPE_CMD_IEEE_CSMA_BE uint8_t
#define _POSITION_CMD_IEEE_CSMA_remainingPeriods 21
#define _TYPE_CMD_IEEE_CSMA_remainingPeriods uint8_t
#define _POSITION_CMD_IEEE_CSMA_lastRssi 22
#define _TYPE_CMD_IEEE_CSMA_lastRssi int8_t
#define _POSITION_CMD_IEEE_CSMA_endTrigger 23
#define _TYPE_CMD_IEEE_CSMA_endTrigger uint8_t
#define _BITPOS_CMD_IEEE_CSMA_endTrigger_triggerType 0
#define _NBITS_CMD_IEEE_CSMA_endTrigger_triggerType 4
#define _BITPOS_CMD_IEEE_CSMA_endTrigger_bEnaCmd 4
#define _NBITS_CMD_IEEE_CSMA_endTrigger_bEnaCmd 1
#define _BITPOS_CMD_IEEE_CSMA_endTrigger_triggerNo 5
#define _NBITS_CMD_IEEE_CSMA_endTrigger_triggerNo 2
#define _BITPOS_CMD_IEEE_CSMA_endTrigger_pastTrig 7
#define _NBITS_CMD_IEEE_CSMA_endTrigger_pastTrig 1
#define _POSITION_CMD_IEEE_CSMA_lastTimeStamp 24
#define _TYPE_CMD_IEEE_CSMA_lastTimeStamp ratmr_t
#define _POSITION_CMD_IEEE_CSMA_endTime 28
#define _TYPE_CMD_IEEE_CSMA_endTime ratmr_t
#define _SIZEOF_CMD_IEEE_CSMA 32
#define _POSITION_CMD_IEEE_RX_ACK_seqNo 14
#define _TYPE_CMD_IEEE_RX_ACK_seqNo uint8_t
#define _POSITION_CMD_IEEE_RX_ACK_endTrigger 15
#define _TYPE_CMD_IEEE_RX_ACK_endTrigger uint8_t
#define _BITPOS_CMD_IEEE_RX_ACK_endTrigger_triggerType 0
#define _NBITS_CMD_IEEE_RX_ACK_endTrigger_triggerType 4
#define _BITPOS_CMD_IEEE_RX_ACK_endTrigger_bEnaCmd 4
#define _NBITS_CMD_IEEE_RX_ACK_endTrigger_bEnaCmd 1
#define _BITPOS_CMD_IEEE_RX_ACK_endTrigger_triggerNo 5
#define _NBITS_CMD_IEEE_RX_ACK_endTrigger_triggerNo 2
#define _BITPOS_CMD_IEEE_RX_ACK_endTrigger_pastTrig 7
#define _NBITS_CMD_IEEE_RX_ACK_endTrigger_pastTrig 1
#define _POSITION_CMD_IEEE_RX_ACK_endTime 16
#define _TYPE_CMD_IEEE_RX_ACK_endTime ratmr_t
#define _SIZEOF_CMD_IEEE_RX_ACK 20
#define _SIZEOF_CMD_IEEE_ABORT_BG 14
#define _POSITION_CMD_IEEE_MOD_CCA_newCcaOpt 2
#define _TYPE_CMD_IEEE_MOD_CCA_newCcaOpt uint8_t
#define _BITPOS_CMD_IEEE_MOD_CCA_newCcaOpt_ccaEnEnergy 0
#define _NBITS_CMD_IEEE_MOD_CCA_newCcaOpt_ccaEnEnergy 1
#define _BITPOS_CMD_IEEE_MOD_CCA_newCcaOpt_ccaEnCorr 1
#define _NBITS_CMD_IEEE_MOD_CCA_newCcaOpt_ccaEnCorr 1
#define _BITPOS_CMD_IEEE_MOD_CCA_newCcaOpt_ccaEnSync 2
#define _NBITS_CMD_IEEE_MOD_CCA_newCcaOpt_ccaEnSync 1
#define _BITPOS_CMD_IEEE_MOD_CCA_newCcaOpt_ccaCorrOp 3
#define _NBITS_CMD_IEEE_MOD_CCA_newCcaOpt_ccaCorrOp 1
#define _BITPOS_CMD_IEEE_MOD_CCA_newCcaOpt_ccaSyncOp 4
#define _NBITS_CMD_IEEE_MOD_CCA_newCcaOpt_ccaSyncOp 1
#define _BITPOS_CMD_IEEE_MOD_CCA_newCcaOpt_ccaCorrThr 5
#define _NBITS_CMD_IEEE_MOD_CCA_newCcaOpt_ccaCorrThr 2
#define _POSITION_CMD_IEEE_MOD_CCA_newCcaRssiThr 3
#define _TYPE_CMD_IEEE_MOD_CCA_newCcaRssiThr int8_t
#define _SIZEOF_CMD_IEEE_MOD_CCA 4
#define _POSITION_CMD_IEEE_MOD_FILT_newFrameFiltOpt 2
#define _TYPE_CMD_IEEE_MOD_FILT_newFrameFiltOpt uint16_t
#define _BITPOS_CMD_IEEE_MOD_FILT_newFrameFiltOpt_frameFiltEn 0
#define _NBITS_CMD_IEEE_MOD_FILT_newFrameFiltOpt_frameFiltEn 1
#define _BITPOS_CMD_IEEE_MOD_FILT_newFrameFiltOpt_frameFiltStop 1
#define _NBITS_CMD_IEEE_MOD_FILT_newFrameFiltOpt_frameFiltStop 1
#define _BITPOS_CMD_IEEE_MOD_FILT_newFrameFiltOpt_autoAckEn 2
#define _NBITS_CMD_IEEE_MOD_FILT_newFrameFiltOpt_autoAckEn 1
#define _BITPOS_CMD_IEEE_MOD_FILT_newFrameFiltOpt_slottedAckEn 3
#define _NBITS_CMD_IEEE_MOD_FILT_newFrameFiltOpt_slottedAckEn 1
#define _BITPOS_CMD_IEEE_MOD_FILT_newFrameFiltOpt_autoPendEn 4
#define _NBITS_CMD_IEEE_MOD_FILT_newFrameFiltOpt_autoPendEn 1
#define _BITPOS_CMD_IEEE_MOD_FILT_newFrameFiltOpt_defaultPend 5
#define _NBITS_CMD_IEEE_MOD_FILT_newFrameFiltOpt_defaultPend 1
#define _BITPOS_CMD_IEEE_MOD_FILT_newFrameFiltOpt_bPendDataReqOnly 6
#define _NBITS_CMD_IEEE_MOD_FILT_newFrameFiltOpt_bPendDataReqOnly 1
#define _BITPOS_CMD_IEEE_MOD_FILT_newFrameFiltOpt_bPanCoord 7
#define _NBITS_CMD_IEEE_MOD_FILT_newFrameFiltOpt_bPanCoord 1
#define _BITPOS_CMD_IEEE_MOD_FILT_newFrameFiltOpt_maxFrameVersion 8
#define _NBITS_CMD_IEEE_MOD_FILT_newFrameFiltOpt_maxFrameVersion 2
#define _BITPOS_CMD_IEEE_MOD_FILT_newFrameFiltOpt_fcfReservedMask 10
#define _NBITS_CMD_IEEE_MOD_FILT_newFrameFiltOpt_fcfReservedMask 3
#define _BITPOS_CMD_IEEE_MOD_FILT_newFrameFiltOpt_modifyFtFilter 13
#define _NBITS_CMD_IEEE_MOD_FILT_newFrameFiltOpt_modifyFtFilter 2
#define _BITPOS_CMD_IEEE_MOD_FILT_newFrameFiltOpt_bStrictLenFilter 15
#define _NBITS_CMD_IEEE_MOD_FILT_newFrameFiltOpt_bStrictLenFilter 1
#define _POSITION_CMD_IEEE_MOD_FILT_newFrameTypes 4
#define _TYPE_CMD_IEEE_MOD_FILT_newFrameTypes uint8_t
#define _BITPOS_CMD_IEEE_MOD_FILT_newFrameTypes_bAcceptFt0Beacon 0
#define _NBITS_CMD_IEEE_MOD_FILT_newFrameTypes_bAcceptFt0Beacon 1
#define _BITPOS_CMD_IEEE_MOD_FILT_newFrameTypes_bAcceptFt1Data 1
#define _NBITS_CMD_IEEE_MOD_FILT_newFrameTypes_bAcceptFt1Data 1
#define _BITPOS_CMD_IEEE_MOD_FILT_newFrameTypes_bAcceptFt2Ack 2
#define _NBITS_CMD_IEEE_MOD_FILT_newFrameTypes_bAcceptFt2Ack 1
#define _BITPOS_CMD_IEEE_MOD_FILT_newFrameTypes_bAcceptFt3MacCmd 3
#define _NBITS_CMD_IEEE_MOD_FILT_newFrameTypes_bAcceptFt3MacCmd 1
#define _BITPOS_CMD_IEEE_MOD_FILT_newFrameTypes_bAcceptFt4Reserved 4
#define _NBITS_CMD_IEEE_MOD_FILT_newFrameTypes_bAcceptFt4Reserved 1
#define _BITPOS_CMD_IEEE_MOD_FILT_newFrameTypes_bAcceptFt5Reserved 5
#define _NBITS_CMD_IEEE_MOD_FILT_newFrameTypes_bAcceptFt5Reserved 1
#define _BITPOS_CMD_IEEE_MOD_FILT_newFrameTypes_bAcceptFt6Reserved 6
#define _NBITS_CMD_IEEE_MOD_FILT_newFrameTypes_bAcceptFt6Reserved 1
#define _BITPOS_CMD_IEEE_MOD_FILT_newFrameTypes_bAcceptFt7Reserved 7
#define _NBITS_CMD_IEEE_MOD_FILT_newFrameTypes_bAcceptFt7Reserved 1
#define _SIZEOF_CMD_IEEE_MOD_FILT 5
#define _POSITION_CMD_IEEE_MOD_SRC_MATCH_options 2
#define _TYPE_CMD_IEEE_MOD_SRC_MATCH_options uint8_t
#define _BITPOS_CMD_IEEE_MOD_SRC_MATCH_options_bEnable 0
#define _NBITS_CMD_IEEE_MOD_SRC_MATCH_options_bEnable 1
#define _BITPOS_CMD_IEEE_MOD_SRC_MATCH_options_srcPend 1
#define _NBITS_CMD_IEEE_MOD_SRC_MATCH_options_srcPend 1
#define _BITPOS_CMD_IEEE_MOD_SRC_MATCH_options_entryType 2
#define _NBITS_CMD_IEEE_MOD_SRC_MATCH_options_entryType 1
#define _POSITION_CMD_IEEE_MOD_SRC_MATCH_entryNo 3
#define _TYPE_CMD_IEEE_MOD_SRC_MATCH_entryNo uint8_t
#define _SIZEOF_CMD_IEEE_MOD_SRC_MATCH 4
#define _SIZEOF_CMD_IEEE_ABORT_FG 2
#define _SIZEOF_CMD_IEEE_STOP_FG 2
#define _POSITION_CMD_IEEE_CCA_REQ_currentRssi 2
#define _TYPE_CMD_IEEE_CCA_REQ_currentRssi int8_t
#define _POSITION_CMD_IEEE_CCA_REQ_maxRssi 3
#define _TYPE_CMD_IEEE_CCA_REQ_maxRssi int8_t
#define _POSITION_CMD_IEEE_CCA_REQ_ccaInfo 4
#define _TYPE_CMD_IEEE_CCA_REQ_ccaInfo uint8_t
#define _BITPOS_CMD_IEEE_CCA_REQ_ccaInfo_ccaState 0
#define _NBITS_CMD_IEEE_CCA_REQ_ccaInfo_ccaState 2
#define _BITPOS_CMD_IEEE_CCA_REQ_ccaInfo_ccaEnergy 2
#define _NBITS_CMD_IEEE_CCA_REQ_ccaInfo_ccaEnergy 2
#define _BITPOS_CMD_IEEE_CCA_REQ_ccaInfo_ccaCorr 4
#define _NBITS_CMD_IEEE_CCA_REQ_ccaInfo_ccaCorr 2
#define _BITPOS_CMD_IEEE_CCA_REQ_ccaInfo_ccaSync 6
#define _NBITS_CMD_IEEE_CCA_REQ_ccaInfo_ccaSync 1
#define _SIZEOF_CMD_IEEE_CCA_REQ 5
#define _POSITION_ieeeRxOutput_nTxAck 0
#define _TYPE_ieeeRxOutput_nTxAck uint8_t
#define _POSITION_ieeeRxOutput_nRxBeacon 1
#define _TYPE_ieeeRxOutput_nRxBeacon uint8_t
#define _POSITION_ieeeRxOutput_nRxData 2
#define _TYPE_ieeeRxOutput_nRxData uint8_t
#define _POSITION_ieeeRxOutput_nRxAck 3
#define _TYPE_ieeeRxOutput_nRxAck uint8_t
#define _POSITION_ieeeRxOutput_nRxMacCmd 4
#define _TYPE_ieeeRxOutput_nRxMacCmd uint8_t
#define _POSITION_ieeeRxOutput_nRxReserved 5
#define _TYPE_ieeeRxOutput_nRxReserved uint8_t
#define _POSITION_ieeeRxOutput_nRxNok 6
#define _TYPE_ieeeRxOutput_nRxNok uint8_t
#define _POSITION_ieeeRxOutput_nRxIgnored 7
#define _TYPE_ieeeRxOutput_nRxIgnored uint8_t
#define _POSITION_ieeeRxOutput_nRxBufFull 8
#define _TYPE_ieeeRxOutput_nRxBufFull uint8_t
#define _POSITION_ieeeRxOutput_lastRssi 9
#define _TYPE_ieeeRxOutput_lastRssi int8_t
#define _POSITION_ieeeRxOutput_maxRssi 10
#define _TYPE_ieeeRxOutput_maxRssi int8_t
#define _POSITION_ieeeRxOutput_beaconTimeStamp 12
#define _TYPE_ieeeRxOutput_beaconTimeStamp ratmr_t
#define _SIZEOF_ieeeRxOutput 16
#define _POSITION_shortAddrEntry_shortAddr 0
#define _TYPE_shortAddrEntry_shortAddr uint16_t
#define _POSITION_shortAddrEntry_panId 2
#define _TYPE_shortAddrEntry_panId uint16_t
#define _SIZEOF_shortAddrEntry 4
#define _POSITION_ieeeRxCorrCrc_status 0
#define _TYPE_ieeeRxCorrCrc_status uint8_t
#define _BITPOS_ieeeRxCorrCrc_status_corr 0
#define _NBITS_ieeeRxCorrCrc_status_corr 6
#define _BITPOS_ieeeRxCorrCrc_status_bIgnore 6
#define _NBITS_ieeeRxCorrCrc_status_bIgnore 1
#define _BITPOS_ieeeRxCorrCrc_status_bCrcErr 7
#define _NBITS_ieeeRxCorrCrc_status_bCrcErr 1
#define _SIZEOF_ieeeRxCorrCrc 1
#endif

1
cpu/cc26xx/lib/cc26xxware

@ -1 +0,0 @@
Subproject commit 420ae3682c11619c1340697632b2dc49f7e53037

3
doc/Doxyfile
View File

@ -807,7 +807,8 @@ EXCLUDE_SYMLINKS = NO
# Note that the wildcards are matched against the file with absolute path, so to
# exclude all test directories for example use the pattern */test/*
EXCLUDE_PATTERNS = */cpu/cc26xx/lib/*
EXCLUDE_PATTERNS = */cpu/cc26xx-cc13xx/lib/* \
*/cpu/cc26xx-cc13xx/rf-core/api/*
# The EXCLUDE_SYMBOLS tag can be used to specify one or more symbol names
# (namespaces, classes, functions, etc.) that should be excluded from the