diff --git a/cpu/arm/openocd/arm7_wig.cfg b/cpu/arm/openocd/arm7_wig.cfg
new file mode 100644
index 000000000..5d6a4b597
--- /dev/null
+++ b/cpu/arm/openocd/arm7_wig.cfg
@@ -0,0 +1,19 @@
+
+     
+# Change the default telnet port...
+telnet_port 4444
+# GDB connects here
+gdb_port 3333
+# GDB can also flash my flash!
+gdb_memory_map enable
+gdb_flash_program enable
+
+# Wiggler interface
+interface parport
+parport_port 0
+parport_cable wiggler_ntrst_inverted
+jtag_speed 0
+set CPUTAPID 0x3BA00477
+set BSTAPID 0x16410041 
+source [find target/stm32F10xxx.cfg]
+
diff --git a/cpu/arm/openocd/target/stm32F10xxx.cfg b/cpu/arm/openocd/target/stm32F10xxx.cfg
new file mode 100644
index 000000000..ee6e79fb5
--- /dev/null
+++ b/cpu/arm/openocd/target/stm32F10xxx.cfg
@@ -0,0 +1,49 @@
+# STM32 Cortex M3
+
+if { [info exists CHIPNAME] } {	
+   set  _CHIPNAME $CHIPNAME    
+} else {	 
+   set  _CHIPNAME stm32F10xxx
+}
+
+if { [info exists ENDIAN] } {	
+   set  _ENDIAN $ENDIAN    
+} else {	 
+   set  _ENDIAN little
+}
+
+if { [info exists CPUTAPID ] } {
+   set _CPUTAPID $CPUTAPID
+} else {
+  # force an error till we get a good number
+   set _CPUTAPID 0xffffffff
+}
+
+#use combined on interfaces or targets that can't set TRST/SRST separately
+reset_config trst_and_srst
+jtag_nsrst_delay 1
+
+#jtag scan chain
+jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
+
+# The target
+set _TARGETNAME [format "%s.cpu" $_CHIPNAME]
+target create $_TARGETNAME cortex_m3 -endian $_ENDIAN -chain-position $_TARGETNAME -variant cortex_m3
+
+$_TARGETNAME configure -work-area-virt 0 -work-area-phys 0x20000000 -work-area-size 0x4000 -work-area-backup 0
+
+
+if { [info exists BSTAPID ] } {
+   set _BSTAPID $BSTAPID
+} else {
+  # force an error till we get a good number
+   set _BSTAPID 0xffffffff
+}
+
+#jtag scan chain
+jtag newtap $_CHIPNAME bs -irlen 5 -ircapture 0x1 -irmask 0xf -expected-id $_BSTAPID
+
+flash bank stm32x 0 0 0 0 0
+
+
+