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Merge pull request #825 from alignan/i2c_changes
Add function to change I2C baudrate and push relevant configuration valu...
This commit is contained in:
Nicolas Tsiftes
commit
10d444637e
@ -42,22 +42,13 @@
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#include "dev/i2cmaster.h"
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#include "dev/light-ziglet.h"
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#if 1
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#define PRINTF(...) printf(__VA_ARGS__)
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#else
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#define PRINTF(...)
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#endif
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#if 0
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#define PRINTFDEBUG(...) printf(__VA_ARGS__)
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#else
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#define PRINTFDEBUG(...)
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#endif
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#define SENSOR_READ_INTERVAL (CLOCK_SECOND)
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#define SENSOR_READ_INTERVAL (CLOCK_SECOND / 2)
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PROCESS(test_process, "Test light ziglet process");
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AUTOSTART_PROCESSES(&test_process);
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@ -70,7 +61,10 @@ PROCESS_THREAD(test_process, ev, data)
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uint16_t light;
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/* Initialize driver and set a slower data rate */
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light_ziglet_init();
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i2c_setrate(I2C_PRESC_100KHZ_LSB, I2C_PRESC_100KHZ_MSB);
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while(1) {
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etimer_set(&et, SENSOR_READ_INTERVAL);
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@ -41,98 +41,90 @@
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#include "i2cmaster.h"
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#include "isr_compat.h"
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signed char tx_byte_ctr, rx_byte_ctr;
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signed char tx_byte_ctr, rx_byte_ctr;
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unsigned char rx_buf[2];
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unsigned char* tx_buf_ptr;
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unsigned char* rx_buf_ptr;
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unsigned char *tx_buf_ptr;
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unsigned char *rx_buf_ptr;
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unsigned char receive_data;
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unsigned char transmit_data1;
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unsigned char transmit_data2;
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volatile unsigned int i; // volatile to prevent optimization
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unsigned char prescale_lsb = I2C_PRESC_Z1_LSB;
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unsigned char prescale_msb = I2C_PRESC_Z1_MSB;
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volatile unsigned int i; /* volatile to prevent optimization */
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//------------------------------------------------------------------------------
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// void i2c_receiveinit(unsigned char slave_address,
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// unsigned char prescale)
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//
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// This function initializes the USCI module for master-receive operation.
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//
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// IN: unsigned char slave_address => Slave Address
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// unsigned char prescale => SCL clock adjustment
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//-----------------------------------------------------------------------------
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/* ------------------------------------------------------------------------------
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* Change the data rate prior initializing transmission or reception
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* ----------------------------------------------------------------------------- */
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void
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i2c_receiveinit(uint8_t slave_address) {
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UCB1CTL1 = UCSWRST; // Enable SW reset
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UCB1CTL0 = UCMST + UCMODE_3 + UCSYNC; // I2C Master, synchronous mode
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UCB1CTL1 = UCSSEL_2 | UCSWRST; // Use SMCLK, keep SW reset
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UCB1BR0 = I2C_PRESC_400KHZ_LSB; // prescaler for 400 kHz data rate
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UCB1BR1 = I2C_PRESC_400KHZ_MSB;
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UCB1I2CSA = slave_address; // set slave address
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UCB1CTL1 &= ~UCTR; // I2C Receiver
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UCB1CTL1 &= ~UCSWRST; // Clear SW reset, resume operation
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i2c_setrate(uint8_t p_lsb, uint8_t p_msb)
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{
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prescale_lsb = p_lsb;
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prescale_lsb = p_msb;
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}
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/* ------------------------------------------------------------------------------
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* This function initializes the USCI module for master-receive operation.
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* ----------------------------------------------------------------------------- */
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void
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i2c_receiveinit(uint8_t slave_address)
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{
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UCB1CTL1 = UCSWRST; /* Enable SW reset */
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UCB1CTL0 = UCMST + UCMODE_3 + UCSYNC; /* I2C Master, synchronous mode */
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UCB1CTL1 = UCSSEL_2 | UCSWRST; /* Use SMCLK, keep SW reset */
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UCB1BR0 = prescale_lsb; /* prescaler (default 400 kHz) */
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UCB1BR1 = prescale_msb;
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UCB1I2CSA = slave_address; /* set slave address */
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UCB1CTL1 &= ~UCTR; /* I2C Receiver */
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UCB1CTL1 &= ~UCSWRST; /* Clear SW reset, resume operation */
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UCB1I2CIE = UCNACKIE;
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#if I2C_RX_WITH_INTERRUPT
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UC1IE = UCB1RXIE; // Enable RX interrupt if desired
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UC1IE = UCB1RXIE; /* Enable RX interrupt if desired */
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#endif
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}
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//------------------------------------------------------------------------------
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// void i2c_transmitinit(unsigned char slave_address,
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// unsigned char prescale)
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//
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// Initializes USCI for master-transmit operation.
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//
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// IN: unsigned char slave_address => Slave Address
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// unsigned char prescale => SCL clock adjustment
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//------------------------------------------------------------------------------
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/* ------------------------------------------------------------------------------
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* Initializes USCI for master-transmit operation.
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* ------------------------------------------------------------------------------ */
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void
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i2c_transmitinit(uint8_t slave_address) {
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UCB1CTL1 |= UCSWRST; // Enable SW reset
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UCB1CTL0 |= (UCMST | UCMODE_3 | UCSYNC); // I2C Master, synchronous mode
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UCB1CTL1 = UCSSEL_2 + UCSWRST; // Use SMCLK, keep SW reset
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UCB1BR0 = I2C_PRESC_400KHZ_LSB; // prescaler for 400 kHz data rate
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UCB1BR1 = I2C_PRESC_400KHZ_MSB;
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UCB1I2CSA = slave_address; // Set slave address
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UCB1CTL1 &= ~UCSWRST; // Clear SW reset, resume operation
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i2c_transmitinit(uint8_t slave_address)
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{
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UCB1CTL1 |= UCSWRST; /* Enable SW reset */
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UCB1CTL0 |= (UCMST | UCMODE_3 | UCSYNC); /* I2C Master, synchronous mode */
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UCB1CTL1 = UCSSEL_2 + UCSWRST; /* Use SMCLK, keep SW reset */
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UCB1BR0 = prescale_lsb; /* prescaler (default 400 kHz) */
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UCB1BR1 = prescale_msb;
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UCB1I2CSA = slave_address; /* Set slave address */
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UCB1CTL1 &= ~UCSWRST; /* Clear SW reset, resume operation */
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UCB1I2CIE = UCNACKIE;
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UC1IE = UCB1TXIE; // Enable TX ready interrupt
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UC1IE = UCB1TXIE; /* Enable TX ready interrupt */
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}
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//------------------------------------------------------------------------------
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// void i2c_receive_n(unsigned char byte_ctr, unsigned char * rx_buf)
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// This function is used to start an I2C communication in master-receiver mode WITHOUT INTERRUPTS
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// for more than 1 byte
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// IN: unsigned char byte_ctr => number of bytes to be read
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// OUT: unsigned char rx_buf => receive data buffer
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// OUT: int n_received => number of bytes read
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//------------------------------------------------------------------------------
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/* ------------------------------------------------------------------------------
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* This function is used to start an I2C communication in master-receiver mode WITHOUT INTERRUPTS
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* for more than 1 byte
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* ------------------------------------------------------------------------------ */
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static volatile uint8_t rx_byte_tot = 0;
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uint8_t
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i2c_receive_n(uint8_t byte_ctr, uint8_t *rx_buf) {
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i2c_receive_n(uint8_t byte_ctr, uint8_t *rx_buf)
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{
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rx_byte_tot = byte_ctr;
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rx_byte_ctr = byte_ctr;
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rx_buf_ptr = rx_buf;
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rx_buf_ptr = rx_buf;
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while ((UCB1CTL1 & UCTXSTT) || (UCB1STAT & UCNACKIFG)) // Slave acks address or not?
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PRINTFDEBUG ("____ UCTXSTT not clear OR NACK received\n");
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while((UCB1CTL1 & UCTXSTT) || (UCB1STAT & UCNACKIFG)) /* Slave acks address or not? */
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PRINTFDEBUG("____ UCTXSTT not clear OR NACK received\n");
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#if I2C_RX_WITH_INTERRUPT
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PRINTFDEBUG(" RX Interrupts: YES \n");
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// SPECIAL-CASE: Stop condition must be sent while receiving the 1st byte for 1-byte only read operations
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if(rx_byte_tot == 1){ // See page 537 of slau144e.pdf
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/* SPECIAL-CASE: Stop condition must be sent while receiving the 1st byte for 1-byte only read operations */
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if(rx_byte_tot == 1) { /* See page 537 of slau144e.pdf */
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dint();
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UCB1CTL1 |= UCTXSTT; // I2C start condition
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while(UCB1CTL1 & UCTXSTT) // Waiting for Start bit to clear
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PRINTFDEBUG ("____ STT clear wait\n");
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UCB1CTL1 |= UCTXSTP; // I2C stop condition
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UCB1CTL1 |= UCTXSTT; /* I2C start condition */
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while(UCB1CTL1 & UCTXSTT) /* Waiting for Start bit to clear */
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PRINTFDEBUG("____ STT clear wait\n");
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UCB1CTL1 |= UCTXSTP; /* I2C stop condition */
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eint();
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}
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else{ // all other cases
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UCB1CTL1 |= UCTXSTT; // I2C start condition
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} else { /* all other cases */
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UCB1CTL1 |= UCTXSTT; /* I2C start condition */
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}
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return 0;
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@ -141,98 +133,86 @@ i2c_receive_n(uint8_t byte_ctr, uint8_t *rx_buf) {
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PRINTFDEBUG(" RX Interrupts: NO \n");
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UCB1CTL1 |= UCTXSTT; // I2C start condition
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UCB1CTL1 |= UCTXSTT; /* I2C start condition */
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while (rx_byte_ctr > 0){
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if (UC1IFG & UCB1RXIFG) { // Waiting for Data
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while(rx_byte_ctr > 0) {
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if(UC1IFG & UCB1RXIFG) { /* Waiting for Data */
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rx_buf[rx_byte_tot - rx_byte_ctr] = UCB1RXBUF;
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rx_byte_ctr--;
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UC1IFG &= ~UCB1RXIFG; // Clear USCI_B1 RX int flag
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UC1IFG &= ~UCB1RXIFG; /* Clear USCI_B1 RX int flag */
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n_received++;
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}
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}
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UCB1CTL1 |= UCTXSTP; // I2C stop condition
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UCB1CTL1 |= UCTXSTP; /* I2C stop condition */
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return n_received;
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#endif
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}
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//------------------------------------------------------------------------------
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// uint8_t i2c_busy()
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//
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// This function is used to check if there is communication in progress.
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//
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// OUT: unsigned char => 0: I2C bus is idle,
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// 1: communication is in progress
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//------------------------------------------------------------------------------
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/* ------------------------------------------------------------------------------
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* This function is used to check if there is communication in progress.
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* ------------------------------------------------------------------------------ */
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uint8_t
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i2c_busy(void) {
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return (UCB1STAT & UCBBUSY);
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i2c_busy(void)
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{
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return UCB1STAT & UCBBUSY;
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}
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/*----------------------------------------------------------------------------*/
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/* Setup ports and pins for I2C use. */
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/*----------------------------------------------------------------------------
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* Setup ports and pins for I2C use.
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* ------------------------------------------------------------------------------ */
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void
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i2c_enable(void) {
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I2C_PxSEL |= (I2C_SDA | I2C_SCL); // Secondary function (USCI) selected
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I2C_PxSEL2 |= (I2C_SDA | I2C_SCL); // Secondary function (USCI) selected
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I2C_PxDIR |= I2C_SCL; // SCL is output (not needed?)
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I2C_PxDIR &= ~I2C_SDA; // SDA is input (not needed?)
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I2C_PxREN |= (I2C_SDA | I2C_SCL); // Activate internal pull-up/-down resistors
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I2C_PxOUT |= (I2C_SDA | I2C_SCL); // Select pull-up resistors
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i2c_enable(void)
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{
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I2C_PxSEL |= (I2C_SDA | I2C_SCL); /* Secondary function (USCI) selected */
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I2C_PxSEL2 |= (I2C_SDA | I2C_SCL); /* Secondary function (USCI) selected */
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I2C_PxDIR |= I2C_SCL; /* SCL is output (not needed?) */
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I2C_PxDIR &= ~I2C_SDA; /* SDA is input (not needed?) */
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I2C_PxREN |= (I2C_SDA | I2C_SCL); /* Activate internal pull-up/-down resistors */
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I2C_PxOUT |= (I2C_SDA | I2C_SCL); /* Select pull-up resistors */
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}
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void
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i2c_disable(void) {
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I2C_PxSEL &= ~(I2C_SDA | I2C_SCL); // GPIO function selected
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I2C_PxSEL2 &= ~(I2C_SDA | I2C_SCL); // GPIO function selected
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I2C_PxREN &= ~(I2C_SDA | I2C_SCL); // Deactivate internal pull-up/-down resistors
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I2C_PxOUT &= ~(I2C_SDA | I2C_SCL); // Select pull-up resistors
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i2c_disable(void)
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{
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I2C_PxSEL &= ~(I2C_SDA | I2C_SCL); /* GPIO function selected */
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I2C_PxSEL2 &= ~(I2C_SDA | I2C_SCL); /* GPIO function selected */
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I2C_PxREN &= ~(I2C_SDA | I2C_SCL); /* Deactivate internal pull-up/-down resistors */
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I2C_PxOUT &= ~(I2C_SDA | I2C_SCL); /* Select pull-up resistors */
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}
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/*----------------------------------------------------------------------------*/
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//------------------------------------------------------------------------------
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// void i2c_transmit_n(unsigned char byte_ctr, unsigned char *field)
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//
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// This function is used to start an I2C communication in master-transmit mode.
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//
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// IN: unsigned char byte_ctr => number of bytes to be transmitted
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// unsigned char *tx_buf => Content to transmit. Read and transmitted from [0] to [byte_ctr]
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//------------------------------------------------------------------------------
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/* ------------------------------------------------------------------------------
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* This function is used to start an I2C communication in master-transmit mode.
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* ------------------------------------------------------------------------------ */
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static volatile uint8_t tx_byte_tot = 0;
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void
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i2c_transmit_n(uint8_t byte_ctr, uint8_t *tx_buf) {
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i2c_transmit_n(uint8_t byte_ctr, uint8_t *tx_buf)
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{
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tx_byte_tot = byte_ctr;
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tx_byte_ctr = byte_ctr;
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tx_buf_ptr = tx_buf;
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UCB1CTL1 |= UCTR + UCTXSTT; // I2C TX, start condition
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tx_buf_ptr = tx_buf;
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UCB1CTL1 |= UCTR + UCTXSTT; /* I2C TX, start condition */
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}
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/*----------------------------------------------------------------------------*/
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ISR(USCIAB1TX, i2c_tx_interrupt)
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{
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// TX Part
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if (UC1IFG & UCB1TXIFG) { // TX int. condition
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if (tx_byte_ctr == 0) {
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UCB1CTL1 |= UCTXSTP; // I2C stop condition
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UC1IFG &= ~UCB1TXIFG; // Clear USCI_B1 TX int flag
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}
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else {
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/* TX Part */
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if(UC1IFG & UCB1TXIFG) { /* TX int. condition */
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if(tx_byte_ctr == 0) {
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UCB1CTL1 |= UCTXSTP; /* I2C stop condition */
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UC1IFG &= ~UCB1TXIFG; /* Clear USCI_B1 TX int flag */
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} else {
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UCB1TXBUF = tx_buf_ptr[tx_byte_tot - tx_byte_ctr];
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tx_byte_ctr--;
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}
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}
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// RX Part
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/* RX Part */
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#if I2C_RX_WITH_INTERRUPT
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else if (UC1IFG & UCB1RXIFG){ // RX int. condition
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else if(UC1IFG & UCB1RXIFG) { /* RX int. condition */
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rx_buf_ptr[rx_byte_tot - rx_byte_ctr] = UCB1RXBUF;
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rx_byte_ctr--;
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if (rx_byte_ctr == 1){ //stop condition should be set before receiving last byte
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// Only for 1-byte transmissions, STOP is handled in receive_n_int
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if (rx_byte_tot != 1)
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UCB1CTL1 |= UCTXSTP; // I2C stop condition
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UC1IFG &= ~UCB1RXIFG; // Clear USCI_B1 RX int flag. XXX Just in case, check if necessary
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if(rx_byte_ctr == 1) { /* stop condition should be set before receiving last byte */
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/* Only for 1-byte transmissions, STOP is handled in receive_n_int */
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if(rx_byte_tot != 1) {
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UCB1CTL1 |= UCTXSTP; /* I2C stop condition */
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}
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UC1IFG &= ~UCB1RXIFG; /* Clear USCI_B1 RX int flag. XXX Just in case, check if necessary */
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}
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}
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#endif
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@ -53,32 +53,7 @@ void i2c_transmitinit(uint8_t slave_address);
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void i2c_transmit_n(uint8_t byte_ctr, uint8_t *tx_buf);
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uint8_t i2c_busy(void);
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//XXX Should these defines be in the contiki-conf.h to make it more platform-independent?
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#define I2C_PxDIR P5DIR
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#define I2C_PxIN P5IN
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#define I2C_PxOUT P5OUT
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#define I2C_PxSEL P5SEL
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#define I2C_PxSEL2 P5SEL2
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#define I2C_PxREN P5REN
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#define I2C_SDA (1 << 1) //SDA == P5.1
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#define I2C_SCL (1 << 2) //SCL == P5.2
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#define I2C_PRESC_1KHZ_LSB 0x00
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#define I2C_PRESC_1KHZ_MSB 0x20
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#define I2C_PRESC_100KHZ_LSB 0x50
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#define I2C_PRESC_100KHZ_MSB 0x00
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#define I2C_PRESC_400KHZ_LSB 0x14
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#define I2C_PRESC_400KHZ_MSB 0x00
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// I2C configuration with RX interrupts
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#ifdef I2C_CONF_RX_WITH_INTERRUPT
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#define I2C_RX_WITH_INTERRUPT I2C_CONF_RX_WITH_INTERRUPT // XXX Move I2C_CONF_RX_WITH_INTERRUPT to contiki-conf.h or platform-conf.h
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#else /* I2C_CONF_RX_WITH_INTERRUPT */
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#define I2C_RX_WITH_INTERRUPT 1
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#endif /* I2C_CONF_RX_WITH_INTERRUPT */
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void i2c_setrate(uint8_t p_lsb, uint8_t p_msb);
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#if 0
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#include <stdio.h>
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@ -87,4 +62,4 @@ uint8_t i2c_busy(void);
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#define PRINTFDEBUG(...)
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#endif
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#endif /* #ifdef I2CMASTER_H_ */
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#endif /* #ifdef I2CMASTER_H_ */
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@ -33,6 +33,7 @@
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/**
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* \file
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* Device drivers for light ziglet sensor in Zolertia Z1.
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* It is recommended to use with a 100KHz data rate
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* \author
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* Antonio Lignan, Zolertia <alinan@zolertia.com>
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* Marcus Lundén, SICS <mlunden@sics.se>
|
||||
@ -49,8 +50,6 @@
|
||||
#define PRINTFDEBUG(...)
|
||||
#endif
|
||||
|
||||
#warning LIGHT SENSOR ZIGLET IS CURRENTLY BROKEN
|
||||
|
||||
/* Bitmasks and bit flag variable for keeping track of tmp102 status. */
|
||||
enum TSL2563_STATUSTYPES {
|
||||
/* must be a bit and not more, not using 0x00. */
|
||||
@ -171,7 +170,7 @@ tsl2563_read_reg(uint8_t reg)
|
||||
/* Receive the data */
|
||||
i2c_receiveinit(TSL2563_ADDR);
|
||||
while(i2c_busy());
|
||||
i2c_receive_n(4, &buf[0]);
|
||||
i2c_receive_n(4, buf);
|
||||
while(i2c_busy());
|
||||
|
||||
PRINTFDEBUG("\nb0 %u, b1 %u, b2 %u, b3 %u\n", buf[0], buf[1], buf[2], buf[3]);
|
||||
@ -179,25 +178,18 @@ tsl2563_read_reg(uint8_t reg)
|
||||
readBuf[0] = (buf[1] << 8 | (buf[0]));
|
||||
readBuf[1] = (buf[3] << 8 | (buf[2]));
|
||||
|
||||
/* XXX Quick hack, was receiving dups bytes */
|
||||
|
||||
if(readBuf[0] == readBuf[1]) {
|
||||
tsl2563_read_reg(TSL2563_READ);
|
||||
return 0x00;
|
||||
} else {
|
||||
retVal = calculateLux(readBuf);
|
||||
return retVal;
|
||||
}
|
||||
retVal = calculateLux(readBuf);
|
||||
return retVal;
|
||||
}
|
||||
uint16_t
|
||||
light_ziglet_on(void)
|
||||
{
|
||||
uint16_t data;
|
||||
uint8_t regon[] = { 0x00, TSL2563_PWRN };
|
||||
uint8_t regon = TSL2563_PWRN;
|
||||
/* Turn on the sensor */
|
||||
i2c_transmitinit(TSL2563_ADDR);
|
||||
while(i2c_busy());
|
||||
i2c_transmit_n(2, regon);
|
||||
i2c_transmit_n(1, ®on);
|
||||
while(i2c_busy());
|
||||
data = (uint16_t)tsl2563_read_reg(TSL2563_READ);
|
||||
return data;
|
||||
|
||||
@ -43,35 +43,33 @@
|
||||
#include <stdio.h>
|
||||
#include "i2cmaster.h"
|
||||
|
||||
/* -------------------------------------------------------------------------- */
|
||||
/* Init the light ziglet sensor: ports, pins, I2C, interrupts (XXX none so far),
|
||||
*/
|
||||
/* Init the light ziglet sensor: ports, pins, I2C, interrupts */
|
||||
void light_ziglet_init(void);
|
||||
|
||||
/* Write to a register.
|
||||
args:
|
||||
reg register to write to
|
||||
val value to write
|
||||
*/
|
||||
*/
|
||||
void tsl2563_write_reg(uint8_t reg, uint16_t val);
|
||||
|
||||
/* Read one register.
|
||||
args:
|
||||
reg what register to read
|
||||
returns the value of the read register
|
||||
*/
|
||||
*/
|
||||
uint16_t tsl2563_read_reg(uint8_t reg);
|
||||
|
||||
/* Takes a single light reading
|
||||
/* Takes a single light reading
|
||||
args: none
|
||||
returns a lux value
|
||||
*/
|
||||
*/
|
||||
uint16_t light_ziglet_read();
|
||||
|
||||
/* Calculates the lux values from the calibration table
|
||||
args: raw values from sensor
|
||||
returns a lux value
|
||||
*/
|
||||
*/
|
||||
uint16_t calculateLux(uint16_t *readRaw);
|
||||
|
||||
/* Turns the light ziglet ON and polls the sensor for a light reading */
|
||||
@ -85,7 +83,7 @@ uint16_t light_ziglet_on(void);
|
||||
|
||||
/* Registers */
|
||||
#define TSL2563_READ 0xAC
|
||||
#define TSL2563_PWRN 0x03
|
||||
#define TSL2563_PWRN 0x03
|
||||
|
||||
/* Calibration settings */
|
||||
#define K1T 0X0040
|
||||
@ -123,5 +121,3 @@ uint16_t light_ziglet_on(void);
|
||||
/* -------------------------------------------------------------------------- */
|
||||
#endif /* ifndef LIGHT_ZIGLET_H_ */
|
||||
|
||||
|
||||
|
||||
|
||||
@ -50,12 +50,11 @@
|
||||
|
||||
/* CPU target speed in Hz */
|
||||
#define F_CPU 8000000uL /* 8MHz by default */
|
||||
//Enric #define F_CPU 3900000uL /*2457600uL*/
|
||||
|
||||
/* Our clock resolution, this is the same as Unix HZ. */
|
||||
#define CLOCK_CONF_SECOND 128UL
|
||||
|
||||
#define BAUD2UBR(baud) ((F_CPU/baud))
|
||||
#define BAUD2UBR(baud) ((F_CPU / baud))
|
||||
|
||||
#define CCIF
|
||||
#define CLIF
|
||||
@ -67,21 +66,21 @@
|
||||
#ifdef __IAR_SYSTEMS_ICC__
|
||||
#ifndef P1SEL2_
|
||||
#define P1SEL2_ (0x0041u) /* Port 1 Selection 2*/
|
||||
DEFC( P1SEL2 , P1SEL2_)
|
||||
DEFC(P1SEL2, P1SEL2_)
|
||||
#endif
|
||||
#ifndef P5SEL2_
|
||||
#define P5SEL2_ (0x0045u) /* Port 5 Selection 2*/
|
||||
DEFC( P5SEL2 , P5SEL2_)
|
||||
DEFC(P5SEL2, P5SEL2_)
|
||||
#endif
|
||||
#else /* __IAR_SYSTEMS_ICC__ */
|
||||
#ifdef __GNUC__
|
||||
#ifndef P1SEL2_
|
||||
#define P1SEL2_ 0x0041 /* Port 1 Selection 2*/
|
||||
sfrb(P1SEL2, P1SEL2_);
|
||||
#define P1SEL2_ 0x0041 /* Port 1 Selection 2*/
|
||||
sfrb(P1SEL2, P1SEL2_);
|
||||
#endif
|
||||
#ifndef P5SEL2_
|
||||
#define P5SEL2_ 0x0045 /* Port 5 Selection 2*/
|
||||
sfrb(P5SEL2, P5SEL2_);
|
||||
#define P5SEL2_ 0x0045 /* Port 5 Selection 2*/
|
||||
sfrb(P5SEL2, P5SEL2_);
|
||||
#endif
|
||||
#endif /* __GNUC__ */
|
||||
#endif /* __IAR_SYSTEMS_ICC__ */
|
||||
@ -112,15 +111,14 @@ typedef unsigned long off_t;
|
||||
#define LEDS_CONF_RED 0x10
|
||||
#define LEDS_CONF_GREEN 0x40
|
||||
#define LEDS_CONF_YELLOW 0x20
|
||||
#endif // Z1_IS_Z1SP
|
||||
#endif /* Z1_IS_Z1SP */
|
||||
|
||||
/* DCO speed resynchronization for more robust UART, etc. */
|
||||
#define DCOSYNCH_CONF_ENABLED 0
|
||||
#define DCOSYNCH_CONF_PERIOD 30
|
||||
|
||||
#define ROM_ERASE_UNIT_SIZE 512
|
||||
#define XMEM_ERASE_UNIT_SIZE (64*1024L)
|
||||
|
||||
#define XMEM_ERASE_UNIT_SIZE (64 * 1024L)
|
||||
|
||||
#define CFS_CONF_OFFSET_TYPE long
|
||||
|
||||
@ -136,19 +134,19 @@ typedef unsigned long off_t;
|
||||
#define CFS_RAM_CONF_SIZE 4096
|
||||
|
||||
/*
|
||||
* SPI bus configuration for the TMote Sky.
|
||||
* SPI bus configuration for the Z1 mote.
|
||||
*/
|
||||
|
||||
/* SPI input/output registers. */
|
||||
#define SPI_TXBUF UCB0TXBUF
|
||||
#define SPI_RXBUF UCB0RXBUF
|
||||
|
||||
/* USART0 Tx ready? */
|
||||
#define SPI_WAITFOREOTx() while ((UCB0STAT & UCBUSY) != 0)
|
||||
/* USART0 Rx ready? */
|
||||
#define SPI_WAITFOREORx() while ((IFG2 & UCB0RXIFG) == 0)
|
||||
/* USART0 Tx buffer ready? */
|
||||
#define SPI_WAITFORTxREADY() while ((IFG2 & UCB0TXIFG) == 0)
|
||||
/* USART0 Tx ready? */
|
||||
#define SPI_WAITFOREOTx() while((UCB0STAT & UCBUSY) != 0)
|
||||
/* USART0 Rx ready? */
|
||||
#define SPI_WAITFOREORx() while((IFG2 & UCB0RXIFG) == 0)
|
||||
/* USART0 Tx buffer ready? */
|
||||
#define SPI_WAITFORTxREADY() while((IFG2 & UCB0TXIFG) == 0)
|
||||
|
||||
#define MOSI 1 /* P3.1 - Output: SPI Master out - slave in (MOSI) */
|
||||
#define MISO 2 /* P3.2 - Input: SPI Master in - slave out (MISO) */
|
||||
@ -157,24 +155,23 @@ typedef unsigned long off_t;
|
||||
/*
|
||||
* SPI bus - M25P80 external flash configuration.
|
||||
*/
|
||||
//#define FLASH_PWR 3 /* P4.3 Output */ ALWAYS POWERED ON Z1
|
||||
#define FLASH_CS 4 /* P4.4 Output */
|
||||
#define FLASH_HOLD 7 /* P5.7 Output */
|
||||
/* FLASH_PWR P4.3 Output ALWAYS POWERED ON Z1 */
|
||||
#define FLASH_CS 4 /* P4.4 Output */
|
||||
#define FLASH_HOLD 7 /* P5.7 Output */
|
||||
|
||||
/* Enable/disable flash access to the SPI bus (active low). */
|
||||
|
||||
#define SPI_FLASH_ENABLE() ( P4OUT &= ~BV(FLASH_CS) )
|
||||
#define SPI_FLASH_DISABLE() ( P4OUT |= BV(FLASH_CS) )
|
||||
|
||||
#define SPI_FLASH_HOLD() ( P5OUT &= ~BV(FLASH_HOLD) )
|
||||
#define SPI_FLASH_UNHOLD() ( P5OUT |= BV(FLASH_HOLD) )
|
||||
#define SPI_FLASH_ENABLE() (P4OUT &= ~BV(FLASH_CS))
|
||||
#define SPI_FLASH_DISABLE() (P4OUT |= BV(FLASH_CS))
|
||||
|
||||
#define SPI_FLASH_HOLD() (P5OUT &= ~BV(FLASH_HOLD))
|
||||
#define SPI_FLASH_UNHOLD() (P5OUT |= BV(FLASH_HOLD))
|
||||
|
||||
/*
|
||||
* SPI bus - CC2420 pin configuration.
|
||||
*/
|
||||
|
||||
#define CC2420_CONF_SYMBOL_LOOP_COUNT 1302 /* 326us msp430X @ 8MHz */
|
||||
#define CC2420_CONF_SYMBOL_LOOP_COUNT 1302 /* 326us msp430X @ 8MHz */
|
||||
|
||||
/* P1.2 - Input: FIFOP from CC2420 */
|
||||
#define CC2420_FIFOP_PORT(type) P1##type
|
||||
@ -188,7 +185,7 @@ typedef unsigned long off_t;
|
||||
/* P4.1 - Input: SFD from CC2420 */
|
||||
#define CC2420_SFD_PORT(type) P4##type
|
||||
#define CC2420_SFD_PIN 1
|
||||
/* P3.0 - Output: SPI Chip Select (CS_N) */
|
||||
/* P3.0 - Output: SPI Chip Select (CS_N) */
|
||||
#define CC2420_CSN_PORT(type) P3##type
|
||||
#define CC2420_CSN_PIN 0
|
||||
/* P4.5 - Output: VREG_EN to CC2420 */
|
||||
@ -198,7 +195,6 @@ typedef unsigned long off_t;
|
||||
#define CC2420_RESET_PORT(type) P4##type
|
||||
#define CC2420_RESET_PIN 6
|
||||
|
||||
|
||||
#define CC2420_IRQ_VECTOR PORT1_VECTOR
|
||||
|
||||
/* Pin status. */
|
||||
@ -208,33 +204,69 @@ typedef unsigned long off_t;
|
||||
#define CC2420_SFD_IS_1 (!!(CC2420_SFD_PORT(IN) & BV(CC2420_SFD_PIN)))
|
||||
|
||||
/* The CC2420 reset pin. */
|
||||
#define SET_RESET_INACTIVE() (CC2420_RESET_PORT(OUT) |= BV(CC2420_RESET_PIN))
|
||||
#define SET_RESET_INACTIVE() (CC2420_RESET_PORT(OUT) |= BV(CC2420_RESET_PIN))
|
||||
#define SET_RESET_ACTIVE() (CC2420_RESET_PORT(OUT) &= ~BV(CC2420_RESET_PIN))
|
||||
|
||||
/* CC2420 voltage regulator enable pin. */
|
||||
#define SET_VREG_ACTIVE() (CC2420_VREG_PORT(OUT) |= BV(CC2420_VREG_PIN))
|
||||
#define SET_VREG_ACTIVE() (CC2420_VREG_PORT(OUT) |= BV(CC2420_VREG_PIN))
|
||||
#define SET_VREG_INACTIVE() (CC2420_VREG_PORT(OUT) &= ~BV(CC2420_VREG_PIN))
|
||||
|
||||
/* CC2420 rising edge trigger for external interrupt 0 (FIFOP). */
|
||||
#define CC2420_FIFOP_INT_INIT() do { \
|
||||
CC2420_FIFOP_PORT(IES) &= ~BV(CC2420_FIFOP_PIN); \
|
||||
CC2420_CLEAR_FIFOP_INT(); \
|
||||
} while(0)
|
||||
#define CC2420_FIFOP_INT_INIT() do { \
|
||||
CC2420_FIFOP_PORT(IES) &= ~BV(CC2420_FIFOP_PIN); \
|
||||
CC2420_CLEAR_FIFOP_INT(); \
|
||||
} while(0)
|
||||
|
||||
/* FIFOP on external interrupt 0. */
|
||||
#define CC2420_ENABLE_FIFOP_INT() do {CC2420_FIFOP_PORT(IE) |= BV(CC2420_FIFOP_PIN);} while(0)
|
||||
#define CC2420_DISABLE_FIFOP_INT() do {CC2420_FIFOP_PORT(IE) &= ~BV(CC2420_FIFOP_PIN);} while(0)
|
||||
#define CC2420_CLEAR_FIFOP_INT() do {CC2420_FIFOP_PORT(IFG) &= ~BV(CC2420_FIFOP_PIN);} while(0)
|
||||
#define CC2420_ENABLE_FIFOP_INT() do { CC2420_FIFOP_PORT(IE) |= BV(CC2420_FIFOP_PIN); } while(0)
|
||||
#define CC2420_DISABLE_FIFOP_INT() do { CC2420_FIFOP_PORT(IE) &= ~BV(CC2420_FIFOP_PIN); } while(0)
|
||||
#define CC2420_CLEAR_FIFOP_INT() do { CC2420_FIFOP_PORT(IFG) &= ~BV(CC2420_FIFOP_PIN); } while(0)
|
||||
|
||||
/*
|
||||
* Enables/disables CC2420 access to the SPI bus (not the bus).
|
||||
* (Chip Select)
|
||||
*/
|
||||
|
||||
/* ENABLE CSn (active low) */
|
||||
/* ENABLE CSn (active low) */
|
||||
#define CC2420_SPI_ENABLE() (CC2420_CSN_PORT(OUT) &= ~BV(CC2420_CSN_PIN))
|
||||
/* DISABLE CSn (active low) */
|
||||
#define CC2420_SPI_DISABLE() (CC2420_CSN_PORT(OUT) |= BV(CC2420_CSN_PIN))
|
||||
/* DISABLE CSn (active low) */
|
||||
#define CC2420_SPI_DISABLE() (CC2420_CSN_PORT(OUT) |= BV(CC2420_CSN_PIN))
|
||||
#define CC2420_SPI_IS_ENABLED() ((CC2420_CSN_PORT(OUT) & BV(CC2420_CSN_PIN)) != BV(CC2420_CSN_PIN))
|
||||
|
||||
/*
|
||||
* I2C configuration
|
||||
*/
|
||||
|
||||
#define I2C_PxDIR P5DIR
|
||||
#define I2C_PxIN P5IN
|
||||
#define I2C_PxOUT P5OUT
|
||||
#define I2C_PxSEL P5SEL
|
||||
#define I2C_PxSEL2 P5SEL2
|
||||
#define I2C_PxREN P5REN
|
||||
|
||||
#define I2C_SDA (1 << 1) /* SDA == P5.1 */
|
||||
#define I2C_SCL (1 << 2) /* SCL == P5.2 */
|
||||
#define I2C_PRESC_1KHZ_LSB 0x00
|
||||
#define I2C_PRESC_1KHZ_MSB 0x20
|
||||
#define I2C_PRESC_100KHZ_LSB 0x50
|
||||
#define I2C_PRESC_100KHZ_MSB 0x00
|
||||
#define I2C_PRESC_400KHZ_LSB 0x14
|
||||
#define I2C_PRESC_400KHZ_MSB 0x00
|
||||
|
||||
/* Set rate as high as possible by default */
|
||||
#ifndef I2C_PRESC_Z1_LSB
|
||||
#define I2C_PRESC_Z1_LSB I2C_PRESC_400KHZ_LSB
|
||||
#endif
|
||||
|
||||
#ifndef I2C_PRESC_Z1_MSB
|
||||
#define I2C_PRESC_Z1_MSB I2C_PRESC_400KHZ_MSB
|
||||
#endif
|
||||
|
||||
/* I2C configuration with RX interrupts */
|
||||
#ifdef I2C_CONF_RX_WITH_INTERRUPT
|
||||
#define I2C_RX_WITH_INTERRUPT I2C_CONF_RX_WITH_INTERRUPT
|
||||
#else /* I2C_CONF_RX_WITH_INTERRUPT */
|
||||
#define I2C_RX_WITH_INTERRUPT 1
|
||||
#endif /* I2C_CONF_RX_WITH_INTERRUPT */
|
||||
|
||||
#endif /* PLATFORM_CONF_H_ */
|
||||
|
||||
Loading…
Reference in New Issue
Block a user