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https://github.com/oliverschmidt/contiki.git
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Zolertia Z1: Direct memory access using UART.
This commit is contained in:
suman_panchal
parent
6ac939bc58
commit
35cc40563e
@ -32,8 +32,12 @@
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#include "contiki.h"
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#include "dev/watchdog.h"
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/* dco_required set to 1 will cause the CPU not to go into
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* sleep modes where the DCO clock stopped */
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int msp430_dco_required;
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#if defined(__MSP430__) && defined(__GNUC__)
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#define asmv(arg) __asm__ __volatile__(arg)
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#define asmv(arg) __asm__ __volatile__ (arg)
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#endif
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/*---------------------------------------------------------------------------*/
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@ -42,8 +46,8 @@ void *
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w_memcpy(void *out, const void *in, size_t n)
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{
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uint8_t *src, *dest;
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src = (uint8_t *) in;
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dest = (uint8_t *) out;
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src = (uint8_t *)in;
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dest = (uint8_t *)out;
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while(n-- > 0) {
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*dest++ = *src++;
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}
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@ -56,7 +60,7 @@ void *
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w_memset(void *out, int value, size_t n)
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{
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uint8_t *dest;
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dest = (uint8_t *) out;
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dest = (uint8_t *)out;
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while(n-- > 0) {
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*dest++ = value & 0xff;
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}
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@ -152,10 +156,30 @@ init_ports(void)
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/*---------------------------------------------------------------------------*/
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/* msp430-ld may align _end incorrectly. Workaround in cpu_init. */
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#if defined(__MSP430__) && defined(__GNUC__)
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extern int _end; /* Not in sys/unistd.h */
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extern int _end; /* Not in sys/unistd.h */
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static char *cur_break = (char *)&_end;
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#endif
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/*---------------------------------------------------------------------------*/
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/* add/remove_lpm_req - for requiring a specific LPM mode. currently Contiki */
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/* jumps to LPM3 to save power, but DMA will not work if DCO is not clocked */
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/* so some modules might need to enter their LPM requirements */
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/* NOTE: currently only works with LPM1 (e.g. DCO) requirements. */
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/*---------------------------------------------------------------------------*/
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void
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msp430_add_lpm_req(int req)
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{
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if(req <= MSP430_REQUIRE_LPM1) {
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msp430_dco_required++;
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}
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}
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void
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msp430_remove_lpm_req(int req)
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{
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if(req <= MSP430_REQUIRE_LPM1) {
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msp430_dco_required--;
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}
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}
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void
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msp430_cpu_init(void)
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{
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@ -164,7 +188,7 @@ msp430_cpu_init(void)
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init_ports();
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/* set DCO to a reasonable default value (8MHz) */
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msp430_init_dco();
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/* calibrate the DCO step-by-step */
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/* calibrate the DCO step-by-step */
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msp430_sync_dco();
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eint();
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#if defined(__MSP430__) && defined(__GNUC__)
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@ -172,6 +196,7 @@ msp430_cpu_init(void)
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cur_break++;
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}
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#endif
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msp430_dco_required = 0;
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}
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/*---------------------------------------------------------------------------*/
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@ -191,7 +216,7 @@ splhigh_(void)
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asmv("mov r2, %0" : "=r" (sr));
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asmv("bic %0, r2" : : "i" (GIE));
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#endif
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return sr & GIE; /* Ignore other sr bits. */
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return sr & GIE; /* Ignore other sr bits. */
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}
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/*---------------------------------------------------------------------------*/
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/*
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@ -209,7 +234,8 @@ splhigh_(void)
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/* } */
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/*---------------------------------------------------------------------------*/
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#ifdef __IAR_SYSTEMS_ICC__
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int __low_level_init(void)
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int
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__low_level_init(void)
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{
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/* turn off watchdog so that C-init will run */
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WDTCTL = WDTPW + WDTHOLD;
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@ -224,7 +250,8 @@ int __low_level_init(void)
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#endif
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/*---------------------------------------------------------------------------*/
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void
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msp430_sync_dco(void) {
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msp430_sync_dco(void)
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{
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uint16_t oldcapture;
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int16_t diff;
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/* DELTA_2 assumes an ACLK of 32768 Hz */
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@ -260,7 +287,7 @@ msp430_sync_dco(void) {
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if(DCOCTL == 0x00) { /* Did DCO roll over? */
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BCSCTL1++;
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}
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/* -> Select next higher RSEL */
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/* -> Select next higher RSEL */
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}
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}
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@ -51,6 +51,11 @@ static volatile uint8_t transmitting;
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#define TX_WITH_INTERRUPT 1
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#endif /* UART0_CONF_TX_WITH_INTERRUPT */
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#ifdef UART0_CONF_RX_WITH_DMA
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#define RX_WITH_DMA UART0_CONF_RX_WITH_DMA
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#else /* UART0_CONF_RX_WITH_DMA */
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#define RX_WITH_DMA 1
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#endif /* UART0_CONF_RX_WITH_DMA */
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#if TX_WITH_INTERRUPT
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#define TXBUFSIZE 64
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@ -59,6 +64,30 @@ static struct ringbuf txbuf;
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static uint8_t txbuf_data[TXBUFSIZE];
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#endif /* TX_WITH_INTERRUPT */
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#if RX_WITH_DMA
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#define RXBUFSIZE 128
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static uint8_t rxbuf[RXBUFSIZE];
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static uint16_t last_size;
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static struct ctimer rxdma_timer;
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static void
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handle_rxdma_timer(void *ptr)
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{
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uint16_t size;
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size = DMA0SZ; /* Note: loop requires that size is less or eq to RXBUFSIZE */
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while(last_size != size) {
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uart0_input_handler((unsigned char)rxbuf[RXBUFSIZE - last_size]);
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last_size--;
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if(last_size == 0) {
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last_size = RXBUFSIZE;
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}
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}
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ctimer_reset(&rxdma_timer);
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}
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#endif /* RX_WITH_DMA */
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/*---------------------------------------------------------------------------*/
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uint8_t
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uart0_active(void)
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@ -69,6 +98,9 @@ uart0_active(void)
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void
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uart0_set_input(int (*input)(unsigned char c))
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{
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#if RX_WITH_DMA /* This needs to be called after ctimer process is started */
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ctimer_set(&rxdma_timer, CLOCK_SECOND / 64, handle_rxdma_timer, NULL);
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#endif
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uart0_input_handler = input;
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}
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/*---------------------------------------------------------------------------*/
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@ -100,7 +132,7 @@ uart0_writeb(unsigned char c)
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#endif /* TX_WITH_INTERRUPT */
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}
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/*---------------------------------------------------------------------------*/
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#if ! NETSTACK_CONF_WITH_IPV4 /* If NETSTACK_CONF_WITH_IPV4 is defined, putchar() is defined by the SLIP driver */
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#if !NETSTACK_CONF_WITH_IPV4 /* If NETSTACK_CONF_WITH_IPV4 is defined, putchar() is defined by the SLIP driver */
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#endif /* ! NETSTACK_CONF_WITH_IPV4 */
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/*---------------------------------------------------------------------------*/
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/**
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@ -135,8 +167,24 @@ uart0_init(unsigned long ubr)
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ringbuf_init(&txbuf, txbuf_data, sizeof(txbuf_data));
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IE2 |= UCA0TXIE; /* Enable UCA0 TX interrupt */
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#endif /* TX_WITH_INTERRUPT */
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#if RX_WITH_DMA
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IE2 &= ~UCA0RXIE; /* disable USART0 RX interrupt */
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/* UART0_RX trigger */
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DMACTL0 = DMA0TSEL_3;
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/* source address = UCA0RXBUF */
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DMA0SA = (unsigned int)&UCA0RXBUF;
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DMA0DA = (unsigned int)&rxbuf;
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DMA0SZ = RXBUFSIZE;
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last_size = RXBUFSIZE;
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DMA0CTL = DMADT_4 + DMASBDB + DMADSTINCR_3 + DMAEN + DMAREQ;
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msp430_add_lpm_req(MSP430_REQUIRE_LPM1);
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#endif /* RX_WITH_DMA */
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}
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/*---------------------------------------------------------------------------*/
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#if !RX_WITH_DMA
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ISR(USCIAB0RX, uart0_rx_interrupt)
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{
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uint8_t c;
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@ -148,18 +196,19 @@ ISR(USCIAB0RX, uart0_rx_interrupt)
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c = UCA0RXBUF;
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if(uart0_input_handler != NULL) {
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if(uart0_input_handler(c)) {
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LPM4_EXIT;
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LPM4_EXIT;
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}
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}
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}
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ENERGEST_OFF(ENERGEST_TYPE_IRQ);
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}
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#endif /* !RX_WITH_DMA */
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/*---------------------------------------------------------------------------*/
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#if TX_WITH_INTERRUPT
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ISR(USCIAB0TX, uart0_tx_interrupt)
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{
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ENERGEST_ON(ENERGEST_TYPE_IRQ);
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if((IFG2 & UCA0TXIFG)){
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if((IFG2 & UCA0TXIFG)) {
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if(ringbuf_elements(&txbuf) == 0) {
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transmitting = 0;
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@ -31,7 +31,6 @@
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#ifndef CONTIKI_CONF_H
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#define CONTIKI_CONF_H
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#include "platform-conf.h"
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#define XMAC_CONF_COMPOWER 1
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@ -58,8 +57,7 @@
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#define CXMAC_CONF_ANNOUNCEMENTS 0
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#define XMAC_CONF_ANNOUNCEMENTS 0
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#define QUEUEBUF_CONF_NUM 4
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#define QUEUEBUF_CONF_NUM 4
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#else /* NETSTACK_CONF_WITH_IPV6 */
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@ -108,8 +106,7 @@
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#define SHELL_VARS_CONF_RAM_BEGIN 0x1100
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#define SHELL_VARS_CONF_RAM_END 0x2000
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#define CFS_CONF_OFFSET_TYPE long
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#define CFS_CONF_OFFSET_TYPE long
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#define PROFILE_CONF_ON 0
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#define ENERGEST_CONF_ON 1
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@ -127,8 +124,9 @@
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#define PROCESS_CONF_STATS 1
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/*#define PROCESS_CONF_FASTPOLL 4*/
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#define UART0_CONF_TX_WITH_INTERRUPT 0 /* So far, printfs without interrupt. */
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#define UART0_CONF_TX_WITH_INTERRUPT 0 // So far, printfs without interrupt.
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#define UART0_CONF_RX_WITH_DMA 0
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#ifdef NETSTACK_CONF_WITH_IPV6
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@ -144,7 +142,7 @@
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/* Handle 10 routes */
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#define UIP_CONF_MAX_ROUTES 15
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#define UIP_CONF_ND6_SEND_RA 0
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#define UIP_CONF_ND6_SEND_RA 0
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#define UIP_CONF_ND6_REACHABLE_TIME 600000
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#define UIP_CONF_ND6_RETRANS_TIMER 10000
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@ -154,7 +152,7 @@
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#define UIP_CONF_IPV6_REASSEMBLY 0
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#define UIP_CONF_NETIF_MAX_ADDRESSES 3
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#define UIP_CONF_IP_FORWARD 0
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#define UIP_CONF_BUFFER_SIZE 140
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#define UIP_CONF_BUFFER_SIZE 140
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#define SICSLOWPAN_CONF_COMPRESSION SICSLOWPAN_COMPRESSION_HC06
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#ifndef SICSLOWPAN_CONF_FRAG
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@ -186,11 +184,8 @@
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#define UIP_CONF_TCP_SPLIT 0
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#ifdef PROJECT_CONF_H
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#include PROJECT_CONF_H
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#endif /* PROJECT_CONF_H */
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#endif /* CONTIKI_CONF_H */
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