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Always prod the watchdog on output to avoid spurious resets during long serial outputs

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This commit is contained in:
adamdunkels 2009-03-02 22:01:26 +00:00
parent 9816f49fe6
commit 62ef4002a5
1 changed files with 4 additions and 5 deletions
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9
cpu/msp430/dev/uart1.c
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@ -26,7 +26,7 @@
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE. * SUCH DAMAGE.
* *
* @(#)$Id: uart1.c,v 1.10 2009/03/01 20:40:30 adamdunkels Exp $ * @(#)$Id: uart1.c,v 1.11 2009/03/02 22:01:26 adamdunkels Exp $
*/ */
/* /*
@ -74,14 +74,13 @@ uart1_set_input(int (*input)(unsigned char c))
void void
uart1_writeb(unsigned char c) uart1_writeb(unsigned char c)
{ {
watchdog_periodic();
#if TX_WITH_INTERRUPT #if TX_WITH_INTERRUPT
/* Put the outgoing byte on the transmission buffer. If the buffer /* Put the outgoing byte on the transmission buffer. If the buffer
is full, we just keep on trying to put the byte into the buffer is full, we just keep on trying to put the byte into the buffer
until it is possible to put it there. */ until it is possible to put it there. */
while(ringbuf_put(&txbuf, c) == 0) { while(ringbuf_put(&txbuf, c) == 0);
watchdog_periodic();
}
/* If there is no transmission going, we need to start it by putting /* If there is no transmission going, we need to start it by putting
the first byte into the UART. */ the first byte into the UART. */
@ -91,7 +90,7 @@ uart1_writeb(unsigned char c)
} }
#else /* TX_WITH_INTERRUPT */ #else /* TX_WITH_INTERRUPT */
watchdog_periodic();
/* Loop until the transmission buffer is available. */ /* Loop until the transmission buffer is available. */
while((IFG2 & UTXIFG1) == 0); while((IFG2 & UTXIFG1) == 0);