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Merge pull request #1009 from bthebaudeau/use-additive-offsets

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Use additive offsets
This commit is contained in:
George Oikonomou 2015-03-28 19:55:45 +00:00
commit a9f499e528
7 changed files with 65 additions and 65 deletions
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14
cpu/cc2538/clock.c
View File

@ -96,17 +96,17 @@ clock_init(void)
REG(SYS_CTRL_RCGCGPT) |= SYS_CTRL_RCGCGPT_GPT0;
/* Make sure GPT0 is off */
REG(GPT_0_BASE | GPTIMER_CTL) = 0;
REG(GPT_0_BASE + GPTIMER_CTL) = 0;
/* 16-bit */
REG(GPT_0_BASE | GPTIMER_CFG) = 0x04;
REG(GPT_0_BASE + GPTIMER_CFG) = 0x04;
/* One-Shot, Count Down, No Interrupts */
REG(GPT_0_BASE | GPTIMER_TAMR) = GPTIMER_TAMR_TAMR_ONE_SHOT;
REG(GPT_0_BASE + GPTIMER_TAMR) = GPTIMER_TAMR_TAMR_ONE_SHOT;
/* Prescale by 16 (thus, value 15 in TAPR) */
REG(GPT_0_BASE | GPTIMER_TAPR) = 0x0F;
REG(GPT_0_BASE + GPTIMER_TAPR) = 0x0F;
}
/*---------------------------------------------------------------------------*/
CCIF clock_time_t
@ -144,11 +144,11 @@ clock_wait(clock_time_t i)
void
clock_delay_usec(uint16_t dt)
{
REG(GPT_0_BASE | GPTIMER_TAILR) = dt;
REG(GPT_0_BASE | GPTIMER_CTL) |= GPTIMER_CTL_TAEN;
REG(GPT_0_BASE + GPTIMER_TAILR) = dt;
REG(GPT_0_BASE + GPTIMER_CTL) |= GPTIMER_CTL_TAEN;
/* One-Shot mode: TAEN will be cleared when the timer reaches 0 */
while(REG(GPT_0_BASE | GPTIMER_CTL) & GPTIMER_CTL_TAEN);
while(REG(GPT_0_BASE + GPTIMER_CTL) & GPTIMER_CTL_TAEN);
}
/*---------------------------------------------------------------------------*/
/**

8
cpu/cc2538/dev/gpio.c
View File

@ -87,7 +87,7 @@ gpio_port_a_isr()
ENERGEST_ON(ENERGEST_TYPE_IRQ);
notify(REG(GPIO_A_BASE | GPIO_MIS), GPIO_A_NUM);
notify(REG(GPIO_A_BASE + GPIO_MIS), GPIO_A_NUM);
GPIO_CLEAR_INTERRUPT(GPIO_A_BASE, 0xFF);
GPIO_CLEAR_POWER_UP_INTERRUPT(GPIO_A_NUM, 0xFF);
@ -103,7 +103,7 @@ gpio_port_b_isr()
ENERGEST_ON(ENERGEST_TYPE_IRQ);
notify(REG(GPIO_B_BASE | GPIO_MIS), GPIO_B_NUM);
notify(REG(GPIO_B_BASE + GPIO_MIS), GPIO_B_NUM);
GPIO_CLEAR_INTERRUPT(GPIO_B_BASE, 0xFF);
GPIO_CLEAR_POWER_UP_INTERRUPT(GPIO_B_NUM, 0xFF);
@ -119,7 +119,7 @@ gpio_port_c_isr()
ENERGEST_ON(ENERGEST_TYPE_IRQ);
notify(REG(GPIO_C_BASE | GPIO_MIS), GPIO_C_NUM);
notify(REG(GPIO_C_BASE + GPIO_MIS), GPIO_C_NUM);
GPIO_CLEAR_INTERRUPT(GPIO_C_BASE, 0xFF);
GPIO_CLEAR_POWER_UP_INTERRUPT(GPIO_C_NUM, 0xFF);
@ -135,7 +135,7 @@ gpio_port_d_isr()
ENERGEST_ON(ENERGEST_TYPE_IRQ);
notify(REG(GPIO_D_BASE | GPIO_MIS), GPIO_D_NUM);
notify(REG(GPIO_D_BASE + GPIO_MIS), GPIO_D_NUM);
GPIO_CLEAR_INTERRUPT(GPIO_D_BASE, 0xFF);
GPIO_CLEAR_POWER_UP_INTERRUPT(GPIO_D_NUM, 0xFF);

44
cpu/cc2538/dev/gpio.h
View File

@ -91,28 +91,28 @@ typedef void (* gpio_callback_t)(uint8_t port, uint8_t pin);
* \param PIN_MASK Pin number mask. Pin 0: 0x01, Pin 1: 0x02 ... Pin 7: 0x80
*/
#define GPIO_SET_INPUT(PORT_BASE, PIN_MASK) \
do { REG((PORT_BASE) | GPIO_DIR) &= ~(PIN_MASK); } while(0)
do { REG((PORT_BASE) + GPIO_DIR) &= ~(PIN_MASK); } while(0)
/** \brief Set pins with PIN_MASK of port with PORT_BASE to output.
* \param PORT_BASE GPIO Port register offset
* \param PIN_MASK Pin number mask. Pin 0: 0x01, Pin 1: 0x02 ... Pin 7: 0x80
*/
#define GPIO_SET_OUTPUT(PORT_BASE, PIN_MASK) \
do { REG((PORT_BASE) | GPIO_DIR) |= (PIN_MASK); } while(0)
do { REG((PORT_BASE) + GPIO_DIR) |= (PIN_MASK); } while(0)
/** \brief Set pins with PIN_MASK of port with PORT_BASE high.
* \param PORT_BASE GPIO Port register offset
* \param PIN_MASK Pin number mask. Pin 0: 0x01, Pin 1: 0x02 ... Pin 7: 0x80
*/
#define GPIO_SET_PIN(PORT_BASE, PIN_MASK) \
do { REG(((PORT_BASE) | GPIO_DATA) + ((PIN_MASK) << 2)) = 0xFF; } while(0)
do { REG((PORT_BASE) + GPIO_DATA + ((PIN_MASK) << 2)) = 0xFF; } while(0)
/** \brief Set pins with PIN_MASK of port with PORT_BASE low.
* \param PORT_BASE GPIO Port register offset
* \param PIN_MASK Pin number mask. Pin 0: 0x01, Pin 1: 0x02 ... Pin 7: 0x80
*/
#define GPIO_CLR_PIN(PORT_BASE, PIN_MASK) \
do { REG(((PORT_BASE) | GPIO_DATA) + ((PIN_MASK) << 2)) = 0x00; } while(0)
do { REG((PORT_BASE) + GPIO_DATA + ((PIN_MASK) << 2)) = 0x00; } while(0)
/** \brief Set pins with PIN_MASK of port with PORT_BASE to value.
* \param PORT_BASE GPIO Port register offset
@ -133,7 +133,7 @@ typedef void (* gpio_callback_t)(uint8_t port, uint8_t pin);
* and then use 0x0A as the value ((1 << 3) | (1 << 1) for pins 3 and 1)
*/
#define GPIO_WRITE_PIN(PORT_BASE, PIN_MASK, value) \
do { REG(((PORT_BASE) | GPIO_DATA) + ((PIN_MASK) << 2)) = (value); } while(0)
do { REG((PORT_BASE) + GPIO_DATA + ((PIN_MASK) << 2)) = (value); } while(0)
/** \brief Read pins with PIN_MASK of port with PORT_BASE.
* \param PORT_BASE GPIO Port register offset
@ -146,21 +146,21 @@ typedef void (* gpio_callback_t)(uint8_t port, uint8_t pin);
* the macro will return 0x81.
*/
#define GPIO_READ_PIN(PORT_BASE, PIN_MASK) \
REG(((PORT_BASE) | GPIO_DATA) + ((PIN_MASK) << 2))
REG((PORT_BASE) + GPIO_DATA + ((PIN_MASK) << 2))
/** \brief Set pins with PIN_MASK of port with PORT_BASE to detect edge.
* \param PORT_BASE GPIO Port register offset
* \param PIN_MASK Pin number mask. Pin 0: 0x01, Pin 1: 0x02 ... Pin 7: 0x80
*/
#define GPIO_DETECT_EDGE(PORT_BASE, PIN_MASK) \
do { REG((PORT_BASE) | GPIO_IS) &= ~(PIN_MASK); } while(0)
do { REG((PORT_BASE) + GPIO_IS) &= ~(PIN_MASK); } while(0)
/** \brief Set pins with PIN_MASK of port with PORT_BASE to detect level.
* \param PORT_BASE GPIO Port register offset
* \param PIN_MASK Pin number mask. Pin 0: 0x01, Pin 1: 0x02 ... Pin 7: 0x80
*/
#define GPIO_DETECT_LEVEL(PORT_BASE, PIN_MASK) \
do { REG((PORT_BASE) | GPIO_IS) |= (PIN_MASK); } while(0)
do { REG((PORT_BASE) + GPIO_IS) |= (PIN_MASK); } while(0)
/** \brief Set pins with PIN_MASK of port with PORT_BASE to trigger an
* interrupt on both edges.
@ -168,7 +168,7 @@ typedef void (* gpio_callback_t)(uint8_t port, uint8_t pin);
* \param PIN_MASK Pin number mask. Pin 0: 0x01, Pin 1: 0x02 ... Pin 7: 0x80
*/
#define GPIO_TRIGGER_BOTH_EDGES(PORT_BASE, PIN_MASK) \
do { REG((PORT_BASE) | GPIO_IBE) |= (PIN_MASK); } while(0)
do { REG((PORT_BASE) + GPIO_IBE) |= (PIN_MASK); } while(0)
/** \brief Set pins with PIN_MASK of port with PORT_BASE to trigger an
* interrupt on single edge (controlled by GPIO_IEV).
@ -176,7 +176,7 @@ typedef void (* gpio_callback_t)(uint8_t port, uint8_t pin);
* \param PIN_MASK Pin number mask. Pin 0: 0x01, Pin 1: 0x02 ... Pin 7: 0x80
*/
#define GPIO_TRIGGER_SINGLE_EDGE(PORT_BASE, PIN_MASK) \
do { REG((PORT_BASE) | GPIO_IBE) &= ~(PIN_MASK); } while(0)
do { REG((PORT_BASE) + GPIO_IBE) &= ~(PIN_MASK); } while(0)
/** \brief Set pins with PIN_MASK of port with PORT_BASE to trigger an
* interrupt on rising edge.
@ -184,7 +184,7 @@ typedef void (* gpio_callback_t)(uint8_t port, uint8_t pin);
* \param PIN_MASK Pin number mask. Pin 0: 0x01, Pin 1: 0x02 ... Pin 7: 0x80
*/
#define GPIO_DETECT_RISING(PORT_BASE, PIN_MASK) \
do { REG((PORT_BASE) | GPIO_IEV) |= (PIN_MASK); } while(0)
do { REG((PORT_BASE) + GPIO_IEV) |= (PIN_MASK); } while(0)
/** \brief Set pins with PIN_MASK of port with PORT_BASE to trigger an
* interrupt on falling edge.
@ -192,7 +192,7 @@ typedef void (* gpio_callback_t)(uint8_t port, uint8_t pin);
* \param PIN_MASK Pin number mask. Pin 0: 0x01, Pin 1: 0x02 ... Pin 7: 0x80
*/
#define GPIO_DETECT_FALLING(PORT_BASE, PIN_MASK) \
do { REG((PORT_BASE) | GPIO_IEV) &= ~(PIN_MASK); } while(0)
do { REG((PORT_BASE) + GPIO_IEV) &= ~(PIN_MASK); } while(0)
/** \brief Enable interrupt triggering for pins with PIN_MASK of port with
* PORT_BASE.
@ -200,7 +200,7 @@ typedef void (* gpio_callback_t)(uint8_t port, uint8_t pin);
* \param PIN_MASK Pin number mask. Pin 0: 0x01, Pin 1: 0x02 ... Pin 7: 0x80
*/
#define GPIO_ENABLE_INTERRUPT(PORT_BASE, PIN_MASK) \
do { REG((PORT_BASE) | GPIO_IE) |= (PIN_MASK); } while(0)
do { REG((PORT_BASE) + GPIO_IE) |= (PIN_MASK); } while(0)
/** \brief Disable interrupt triggering for pins with PIN_MASK of port with
* PORT_BASE.
@ -208,7 +208,7 @@ typedef void (* gpio_callback_t)(uint8_t port, uint8_t pin);
* \param PIN_MASK Pin number mask. Pin 0: 0x01, Pin 1: 0x02 ... Pin 7: 0x80
*/
#define GPIO_DISABLE_INTERRUPT(PORT_BASE, PIN_MASK) \
do { REG((PORT_BASE) | GPIO_IE) &= ~(PIN_MASK); } while(0)
do { REG((PORT_BASE) + GPIO_IE) &= ~(PIN_MASK); } while(0)
/** \brief Clear interrupt triggering for pins with PIN_MASK of port with
* PORT_BASE.
@ -216,7 +216,7 @@ typedef void (* gpio_callback_t)(uint8_t port, uint8_t pin);
* \param PIN_MASK Pin number mask. Pin 0: 0x01, Pin 1: 0x02 ... Pin 7: 0x80
*/
#define GPIO_CLEAR_INTERRUPT(PORT_BASE, PIN_MASK) \
do { REG((PORT_BASE) | GPIO_IC) = (PIN_MASK); } while(0)
do { REG((PORT_BASE) + GPIO_IC) = (PIN_MASK); } while(0)
/** \brief Configure the pin to be under peripheral control with PIN_MASK of
* port with PORT_BASE.
@ -224,7 +224,7 @@ typedef void (* gpio_callback_t)(uint8_t port, uint8_t pin);
* \param PIN_MASK Pin number mask. Pin 0: 0x01, Pin 1: 0x02 ... Pin 7: 0x80
*/
#define GPIO_PERIPHERAL_CONTROL(PORT_BASE, PIN_MASK) \
do { REG((PORT_BASE) | GPIO_AFSEL) |= (PIN_MASK); } while(0)
do { REG((PORT_BASE) + GPIO_AFSEL) |= (PIN_MASK); } while(0)
/** \brief Configure the pin to be software controlled with PIN_MASK of port
* with PORT_BASE.
@ -232,7 +232,7 @@ typedef void (* gpio_callback_t)(uint8_t port, uint8_t pin);
* \param PIN_MASK Pin number mask. Pin 0: 0x01, Pin 1: 0x02 ... Pin 7: 0x80
*/
#define GPIO_SOFTWARE_CONTROL(PORT_BASE, PIN_MASK) \
do { REG((PORT_BASE) | GPIO_AFSEL) &= ~(PIN_MASK); } while(0)
do { REG((PORT_BASE) + GPIO_AFSEL) &= ~(PIN_MASK); } while(0)
/** \brief Set pins with PIN_MASK of port PORT to trigger a power-up interrupt
* on rising edge.
@ -240,7 +240,7 @@ typedef void (* gpio_callback_t)(uint8_t port, uint8_t pin);
* \param PIN_MASK Pin number mask. Pin 0: 0x01, Pin 1: 0x02 ... Pin 7: 0x80
*/
#define GPIO_POWER_UP_ON_RISING(PORT, PIN_MASK) \
do { REG(GPIO_PORT_TO_BASE(PORT) | GPIO_P_EDGE_CTRL) &= \
do { REG(GPIO_PORT_TO_BASE(PORT) + GPIO_P_EDGE_CTRL) &= \
~((PIN_MASK) << ((PORT) << 3)); } while(0)
/** \brief Set pins with PIN_MASK of port PORT to trigger a power-up interrupt
@ -249,7 +249,7 @@ typedef void (* gpio_callback_t)(uint8_t port, uint8_t pin);
* \param PIN_MASK Pin number mask. Pin 0: 0x01, Pin 1: 0x02 ... Pin 7: 0x80
*/
#define GPIO_POWER_UP_ON_FALLING(PORT, PIN_MASK) \
do { REG(GPIO_PORT_TO_BASE(PORT) | GPIO_P_EDGE_CTRL) |= \
do { REG(GPIO_PORT_TO_BASE(PORT) + GPIO_P_EDGE_CTRL) |= \
(PIN_MASK) << ((PORT) << 3); } while(0)
/** \brief Enable power-up interrupt triggering for pins with PIN_MASK of port
@ -258,7 +258,7 @@ typedef void (* gpio_callback_t)(uint8_t port, uint8_t pin);
* \param PIN_MASK Pin number mask. Pin 0: 0x01, Pin 1: 0x02 ... Pin 7: 0x80
*/
#define GPIO_ENABLE_POWER_UP_INTERRUPT(PORT, PIN_MASK) \
do { REG(GPIO_PORT_TO_BASE(PORT) | GPIO_PI_IEN) |= \
do { REG(GPIO_PORT_TO_BASE(PORT) + GPIO_PI_IEN) |= \
(PIN_MASK) << ((PORT) << 3); } while(0)
/** \brief Disable power-up interrupt triggering for pins with PIN_MASK of port
@ -267,7 +267,7 @@ typedef void (* gpio_callback_t)(uint8_t port, uint8_t pin);
* \param PIN_MASK Pin number mask. Pin 0: 0x01, Pin 1: 0x02 ... Pin 7: 0x80
*/
#define GPIO_DISABLE_POWER_UP_INTERRUPT(PORT, PIN_MASK) \
do { REG(GPIO_PORT_TO_BASE(PORT) | GPIO_PI_IEN) &= \
do { REG(GPIO_PORT_TO_BASE(PORT) + GPIO_PI_IEN) &= \
~((PIN_MASK) << ((PORT) << 3)); } while(0)
/** \brief Clear power-up interrupt triggering for pins with PIN_MASK of port
@ -276,7 +276,7 @@ typedef void (* gpio_callback_t)(uint8_t port, uint8_t pin);
* \param PIN_MASK Pin number mask. Pin 0: 0x01, Pin 1: 0x02 ... Pin 7: 0x80
*/
#define GPIO_CLEAR_POWER_UP_INTERRUPT(PORT, PIN_MASK) \
do { REG(GPIO_PORT_TO_BASE(PORT) | GPIO_IRQ_DETECT_ACK) = \
do { REG(GPIO_PORT_TO_BASE(PORT) + GPIO_IRQ_DETECT_ACK) = \
(PIN_MASK) << ((PORT) << 3); } while(0)
/**

2
cpu/cc2538/dev/nvic.c
View File

@ -57,7 +57,7 @@ nvic_init()
interrupt_unpend = (uint32_t *)NVIC_UNPEND0;
/* Provide our interrupt table to the NVIC */
REG(SCB_VTABLE) = (NVIC_CONF_VTABLE_BASE | NVIC_CONF_VTABLE_OFFSET);
REG(SCB_VTABLE) = (NVIC_CONF_VTABLE_BASE + NVIC_CONF_VTABLE_OFFSET);
}
/*---------------------------------------------------------------------------*/
void

50
cpu/cc2538/dev/uart.c
View File

@ -206,22 +206,22 @@ reset(uint32_t uart_base)
uint32_t lchr;
/* Make sure the UART is disabled before trying to configure it */
REG(uart_base | UART_CTL) = UART_CTL_VALUE;
REG(uart_base + UART_CTL) = UART_CTL_VALUE;
/* Clear error status */
REG(uart_base | UART_ECR) = 0xFF;
REG(uart_base + UART_ECR) = 0xFF;
/* Store LCHR configuration */
lchr = REG(uart_base | UART_LCRH);
lchr = REG(uart_base + UART_LCRH);
/* Flush FIFOs by clearing LCHR.FEN */
REG(uart_base | UART_LCRH) = 0;
REG(uart_base + UART_LCRH) = 0;
/* Restore LCHR configuration */
REG(uart_base | UART_LCRH) = lchr;
REG(uart_base + UART_LCRH) = lchr;
/* UART Enable */
REG(uart_base | UART_CTL) |= UART_CTL_UARTEN;
REG(uart_base + UART_CTL) |= UART_CTL_UARTEN;
}
/*---------------------------------------------------------------------------*/
static bool
@ -232,7 +232,7 @@ permit_pm1(void)
for(regs = &uart_regs[0]; regs < &uart_regs[UART_INSTANCE_COUNT]; regs++) {
/* Note: UART_FR.TXFE reads 0 if the UART clock is gated. */
if((REG(SYS_CTRL_RCGCUART) & regs->sys_ctrl_rcgcuart_uart) != 0 &&
(REG(regs->base | UART_FR) & UART_FR_TXFE) == 0) {
(REG(regs->base + UART_FR) & UART_FR_TXFE) == 0) {
return false;
}
}
@ -261,7 +261,7 @@ uart_init(uint8_t uart)
REG(SYS_CTRL_DCGCUART) |= regs->sys_ctrl_dcgcuart_uart;
/* Run on SYS_DIV */
REG(regs->base | UART_CC) = 0;
REG(regs->base + UART_CC) = 0;
/*
* Select the UARTx RX pin by writing to the IOC_UARTRXD_UARTn register
@ -292,21 +292,21 @@ uart_init(uint8_t uart)
* Acknowledge RX and RX Timeout
* Acknowledge Framing, Overrun and Break Errors
*/
REG(regs->base | UART_IM) = UART_IM_RXIM | UART_IM_RTIM;
REG(regs->base | UART_IM) |= UART_IM_OEIM | UART_IM_BEIM | UART_IM_FEIM;
REG(regs->base + UART_IM) = UART_IM_RXIM | UART_IM_RTIM;
REG(regs->base + UART_IM) |= UART_IM_OEIM | UART_IM_BEIM | UART_IM_FEIM;
REG(regs->base | UART_IFLS) =
REG(regs->base + UART_IFLS) =
UART_IFLS_RXIFLSEL_1_8 | UART_IFLS_TXIFLSEL_1_2;
/* Make sure the UART is disabled before trying to configure it */
REG(regs->base | UART_CTL) = UART_CTL_VALUE;
REG(regs->base + UART_CTL) = UART_CTL_VALUE;
/* Baud Rate Generation */
REG(regs->base | UART_IBRD) = regs->ibrd;
REG(regs->base | UART_FBRD) = regs->fbrd;
REG(regs->base + UART_IBRD) = regs->ibrd;
REG(regs->base + UART_FBRD) = regs->fbrd;
/* UART Control: 8N1 with FIFOs */
REG(regs->base | UART_LCRH) = UART_LCRH_WLEN_8 | UART_LCRH_FEN;
REG(regs->base + UART_LCRH) = UART_LCRH_WLEN_8 | UART_LCRH_FEN;
/*
* Enable hardware flow control (RTS/CTS) if requested.
@ -316,18 +316,18 @@ uart_init(uint8_t uart)
REG(IOC_UARTCTS_UART1) = ioc_input_sel(regs->cts.port, regs->cts.pin);
GPIO_PERIPHERAL_CONTROL(GPIO_PORT_TO_BASE(regs->cts.port), GPIO_PIN_MASK(regs->cts.pin));
ioc_set_over(regs->cts.port, regs->cts.pin, IOC_OVERRIDE_DIS);
REG(UART_1_BASE | UART_CTL) |= UART_CTL_CTSEN;
REG(UART_1_BASE + UART_CTL) |= UART_CTL_CTSEN;
}
if(regs->rts.port >= 0) {
ioc_set_sel(regs->rts.port, regs->rts.pin, IOC_PXX_SEL_UART1_RTS);
GPIO_PERIPHERAL_CONTROL(GPIO_PORT_TO_BASE(regs->rts.port), GPIO_PIN_MASK(regs->rts.pin));
ioc_set_over(regs->rts.port, regs->rts.pin, IOC_OVERRIDE_OE);
REG(UART_1_BASE | UART_CTL) |= UART_CTL_RTSEN;
REG(UART_1_BASE + UART_CTL) |= UART_CTL_RTSEN;
}
/* UART Enable */
REG(regs->base | UART_CTL) |= UART_CTL_UARTEN;
REG(regs->base + UART_CTL) |= UART_CTL_UARTEN;
/* Enable UART0 Interrupts */
nvic_interrupt_enable(regs->nvic_int);
@ -354,9 +354,9 @@ uart_write_byte(uint8_t uart, uint8_t b)
uart_base = uart_regs[uart].base;
/* Block if the TX FIFO is full */
while(REG(uart_base | UART_FR) & UART_FR_TXFF);
while(REG(uart_base + UART_FR) & UART_FR_TXFF);
REG(uart_base | UART_DR) = b;
REG(uart_base + UART_DR) = b;
}
/*---------------------------------------------------------------------------*/
void
@ -371,18 +371,18 @@ uart_isr(uint8_t uart)
/* Store the current MIS and clear all flags early, except the RTM flag.
* This will clear itself when we read out the entire FIFO contents */
mis = REG(uart_base | UART_MIS) & 0x0000FFFF;
mis = REG(uart_base + UART_MIS) & 0x0000FFFF;
REG(uart_base | UART_ICR) = 0x0000FFBF;
REG(uart_base + UART_ICR) = 0x0000FFBF;
if(mis & (UART_MIS_RXMIS | UART_MIS_RTMIS)) {
while(!(REG(uart_base | UART_FR) & UART_FR_RXFE)) {
while(!(REG(uart_base + UART_FR) & UART_FR_RXFE)) {
if(input_handler[uart] != NULL) {
input_handler[uart]((unsigned char)(REG(uart_base | UART_DR) & 0xFF));
input_handler[uart]((unsigned char)(REG(uart_base + UART_DR) & 0xFF));
} else {
/* To prevent an Overrun Error, we need to flush the FIFO even if we
* don't have an input_handler. Use mis as a data trash can */
mis = REG(uart_base | UART_DR);
mis = REG(uart_base + UART_DR);
}
}
} else if(mis & (UART_MIS_OEMIS | UART_MIS_BEMIS | UART_MIS_FEMIS)) {

2
cpu/cc26xx/clock.c
View File

@ -167,7 +167,7 @@ clock_delay_usec(uint16_t len)
* Wait for TBEN to clear. CC26xxware does not provide us with a convenient
* function, hence the direct register access here
*/
while(HWREG(GPT0_BASE | GPT_O_CTL) & GPT_CTL_TBEN);
while(HWREG(GPT0_BASE + GPT_O_CTL) & GPT_CTL_TBEN);
}
/*---------------------------------------------------------------------------*/
/**

10
cpu/stm32w108/hal/micro/cortexm3/mfg-token.c
View File

@ -50,10 +50,10 @@ void halInternalGetMfgTokenData(void *data, uint16_t ID, uint8_t index, uint8_t
MEMCOPY(ram, eui64, 8 /*EUI64_SIZE*/);
} else {
//read from the Information Blocks. The token ID is only the
//bottom 16bits of the token's actual address. Since the info blocks
//exist in the range DATA_BIG_INFO_BASE-DATA_BIG_INFO_END, we need
//to OR the ID with DATA_BIG_INFO_BASE to get the real address.
uint32_t realAddress = (DATA_BIG_INFO_BASE|ID) + (len*index);
//DATA_BIG_INFO_BASE-relative 16-bit offset of the token. Since the
//info blocks exist in the range DATA_BIG_INFO_BASE-DATA_BIG_INFO_END,
//we need to add the ID to DATA_BIG_INFO_BASE to get the real address.
uint32_t realAddress = (DATA_BIG_INFO_BASE+ID) + (len*index);
uint8_t *flash = (uint8_t *)realAddress;
@ -77,7 +77,7 @@ void halInternalGetMfgTokenData(void *data, uint16_t ID, uint8_t index, uint8_t
void halInternalSetMfgTokenData(uint16_t token, void *data, uint8_t len)
{
StStatus flashStatus;
uint32_t realAddress = (DATA_BIG_INFO_BASE|token);
uint32_t realAddress = (DATA_BIG_INFO_BASE+token);
uint8_t * flash = (uint8_t *)realAddress;
uint32_t i;