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https://github.com/oliverschmidt/contiki.git
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flash init --- makes them work much better.
resumeMACAsync on each received packet --- no more lockups.
This commit is contained in:
Mariano Alvira
parent
424761f23d
commit
b508d138a8
@ -400,6 +400,7 @@ typedef union maca_maskirq_reg_tag
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#define _is_action_complete_interrupt(x) (0 != (maca_irq_acpl & x))
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#define _is_filter_failed_interrupt(x) (0 != (maca_irq_flt & x))
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#define _is_checksum_failed_interrupt(x) (0 != (maca_irq_crc & x))
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#define SMAC_MACA_CNTL_INIT_STATE ( control_prm | control_nofc | control_mode_non_slotted )
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@ -411,6 +412,7 @@ void init_phy(void);
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void vreg_init(void);
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void ResumeMACASync(void);
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void radio_init(void);
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uint32_t init_from_flash(uint32_t addr);
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void set_power(uint8_t power);
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void set_channel(uint8_t chan);
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75
src/maca.c
75
src/maca.c
@ -28,7 +28,7 @@ void init_phy(void)
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maca_framesync = 0x000000A7;
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maca_clk = 0x00000008;
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// maca_maskirq = 0; //(maca_irq_cm | maca_irq_acpl | maca_irq_rst | maca_irq_di | maca_irq_crc | maca_irq_flt );
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maca_maskirq = (maca_irq_rst | maca_irq_acpl | maca_irq_cm | maca_irq_flt);
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maca_maskirq = (maca_irq_rst | maca_irq_acpl | maca_irq_cm | maca_irq_flt | maca_irq_crc);
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maca_slotoffset = 0x00350000;
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}
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@ -149,7 +149,7 @@ void vreg_init(void) {
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/* radio_init has been tested to be good */
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void radio_init(void) {
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uint32_t i;
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volatile uint32_t i;
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/* sequence 1 */
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for(i=0; i<MAX_SEQ1; i++) {
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*(volatile uint32_t *)(addr_seq1[i]) = data_seq1[i];
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@ -186,6 +186,24 @@ void radio_init(void) {
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for(i=0; i<MAX_DATA; i++) {
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*(volatile uint32_t *)(addr_reg_rep[i]) = data_reg_rep[i];
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}
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puts("initfromflash\n\r");
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*(volatile uint32_t *)(0x80003048) = 0x00000f04; /* bypass the buck */
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for(i=0; i<0x161a8; i++) { continue; } /* wait for the bypass to take */
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// while((((*(volatile uint32_t *)(0x80003018))>>17) & 1) !=1) { continue; } /* wait for the bypass to take */
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*(volatile uint32_t *)(0x80003048) = 0x00000fa4; /* start the regulators */
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for(i=0; i<0x161a8; i++) { continue; } /* wait for the bypass to take */
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init_from_flash(0x1F000);
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puts("ram_values:\n\r");
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for(i=0; i<4; i++) {
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puts(" 0x");
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put_hex(ram_values[i]);
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puts("\n\r");
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}
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}
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const uint32_t PSMVAL[19] = {
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@ -354,32 +372,55 @@ void set_channel(uint8_t chan) {
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#define ENTRY_EOF 0x00000e0f
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/* processes up to 4 words of initialization entries */
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/* returns the number of words processed */
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uint8_t exec_init_entry(uint32_t *entries, uint8_t *valbuf)
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uint32_t exec_init_entry(uint32_t *entries, uint8_t *valbuf)
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{
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volatile uint32_t i;
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if(entries[0] <= ROM_END) {
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if (entries[0] == 0) {
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/* do delay command*/
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puts("init_entry: delay ");
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put_hex32(entries[1]);
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puts("\n\r");
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for(i=0; i<entries[1]; i++) { continue; }
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return 2;
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} else if (entries[0] == 1) {
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/* do bit set/clear command*/
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puts("init_entry: bit set clear ");
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put_hex32(entries[1]);
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putc(' ');
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put_hex32(entries[2]);
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putc(' ');
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put_hex32(entries[3]);
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puts("\n\r");
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reg(entries[2]) = (reg(entries[2]) & ~entries[1]) | (entries[3] & entries[1]);
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return 4;
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} else if ((entries[0] >= 16) &&
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(entries[0] < 0xfff1)) {
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/* store bytes in valbuf */
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puts("init_entry: store in valbuf ");
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put_hex(entries[1]);
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puts(" position ");
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put_hex((entries[0]>>4)-1);
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puts("\n\r");
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valbuf[(entries[0]>>4)-1] = entries[1];
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return 2;
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} else if (entries[0] == ENTRY_EOF) {
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puts("init_entry: eof ");
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return 0;
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} else {
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/* invalid command code */
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puts("init_entry: invaild code ");
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put_hex32(entries[0]);
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puts("\n\r");
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return 0;
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}
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} else { /* address isn't in ROM space */
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/* do store value in address command */
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puts("init_entry: address value pair - *0x");
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put_hex32(entries[0]);
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puts(" = ");
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put_hex32(entries[1]);
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puts("\n\r");
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reg(entries[0]) = entries[1];
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return 2;
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}
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@ -390,18 +431,34 @@ uint8_t exec_init_entry(uint32_t *entries, uint8_t *valbuf)
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uint32_t init_from_flash(uint32_t addr) {
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nvmType_t type=0;
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nvmErr_t err;
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uint32_t buf[4];
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uint16_t len;
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uint32_t i=0;
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volatile uint32_t buf[8];
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volatile uint16_t len;
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volatile uint32_t i=0,j;
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err = nvm_detect(gNvmInternalInterface_c, &type);
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puts("nvm_detect returned type ");
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put_hex32(type);
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puts(" err ");
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put_hex(err);
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puts("\n\r");
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nvm_setsvar(0);
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err = nvm_read(gNvmInternalInterface_c, type, (uint8_t *)buf, addr, 8);
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i+=8;
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puts("nvm_read returned: 0x");
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put_hex(err);
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puts("\n\r");
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for(j=0; j<4; j++) {
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put_hex32(buf[j]);
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puts("\n\r");
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}
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if(buf[0] == FLASH_INIT_MAGIC) {
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len = buf[1] & 0x0000ffff;
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while(i<len) {
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while(i<len-4) {
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volatile uint32_t ret;
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err = nvm_read(gNvmInternalInterface_c, type, (uint8_t *)buf, addr+i, 32);
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i += exec_init_entry(buf, ram_values);
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i += 4*exec_init_entry(buf, ram_values);
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}
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return i;
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} else {
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@ -31,22 +31,6 @@ void put_hex32(uint32_t x);
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const uint8_t hex[16]={'0','1','2','3','4','5','6','7',
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'8','9','a','b','c','d','e','f'};
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void magic(void) {
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#define X 0x80009a000
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#define Y 0x80009a008
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#define VAL 0x0000f7df
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volatile uint32_t x,y;
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x = reg(X); /* get X */
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x &= 0xfffeffff; /* clear bit 16 */
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reg(X) = x; /* put it back */
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y = reg(Y); /* get Y */
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y |= VAL; /* or with the VAL */
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x = reg(X); /* get X again */
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x |= 16; /* or with 16 */
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reg(X) = x; /* put X back */
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reg(Y) = y; /* put Y back */
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}
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uint32_t ackBox[10];
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#define MAX_PAYLOAD 128
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@ -221,6 +205,8 @@ void main(void) {
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toggle_led();
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ResumeMACASync();
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command_xcvr_rx();
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break;
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@ -239,72 +225,12 @@ void main(void) {
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puts("filter failed\n\r");
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ResumeMACASync();
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command_xcvr_rx();
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} else if (_is_checksum_failed_interrupt(maca_irq)) {
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puts("crc failed\n\r");
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ResumeMACASync();
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command_xcvr_rx();
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}
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/* puts(NL); */
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/* puts("Maca_base"); */
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/* puts(NL); */
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/* dump_regs(MACA_BASE,96); */
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/* puts("0x80009000"); */
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/* puts(NL); */
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/* dump_regs(0x80009000,192); */
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/* /\* start rx sequence *\/ */
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/* reg(MACA_CONTROL) = 0x00031a01; /\* abort *\/ */
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/* while (((tmp = reg(MACA_STATUS)) & 15) == 14) */
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/* puts("."); */
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/* puts("abort status is "); put_hex32(tmp); puts(NL); */
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/* puts("1 status is "); put_hex32(reg(MACA_STATUS)); puts(NL); */
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/* puts("2 status is "); put_hex32(reg(MACA_STATUS)); puts(NL); */
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/* puts("3 status is "); put_hex32(reg(MACA_STATUS)); puts(NL); */
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/* read TSM_RX_STEPS */
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/* TsmRxSteps = (*((volatile uint32_t *)(0x80009204))); */
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/* puts("TsmRxSteps: "); */
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/* put_hex32(TsmRxSteps); */
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/* puts(NL); */
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/* /\* isolate the RX_WU_STEPS *\/ */
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/* /\* shift left to align with 32-bit addressing *\/ */
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/* LastWarmupStep = (TsmRxSteps & 0x1f) << 2; */
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/* /\* Read "current" TSM step and save this value for later *\/ */
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/* LastWarmupData = (*((volatile uint32_t *)(0x80009300 + LastWarmupStep))); */
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/* puts("LastWarmupData: "); */
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/* put_hex32(LastWarmupData); */
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/* puts(NL); */
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/* /\* isolate the RX_WD_STEPS *\/ */
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/* /\* right-shift bits down to bit 0 position *\/ */
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/* /\* left-shift to align with 32-bit addressing *\/ */
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/* LastWarmdownStep = ((TsmRxSteps & 0x1f00) >> 8) << 2; */
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/* /\* write "last warmdown data" to current TSM step to shutdown rx *\/ */
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/* LastWarmdownData = (*((volatile uint32_t *)(0x80009300 + LastWarmdownStep))); */
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/* puts("LastWarmdownData: "); */
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/* put_hex32(LastWarmdownData); */
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/* puts(NL); */
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/* reg(MACA_CONTROL) = 0x00031a04; /\* receive *\/ */
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/* while (((tmp = reg(MACA_STATUS)) & 15) == 14) */
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/* puts("."); */
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/* puts("complete status is "); put_hex32(tmp); puts(NL); */
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/* puts("1 status is "); put_hex32(reg(MACA_STATUS)); puts(NL); */
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/* puts("2 status is "); put_hex32(reg(MACA_STATUS)); puts(NL); */
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/* puts("3 status is "); put_hex32(reg(MACA_STATUS)); puts(NL); */
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/* puts(NL); */
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/* for(i=0; i<DELAY; i++) { continue; } */
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/* for(i=0; i<DELAY; i++) { continue; } */
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/* for(i=0; i<DELAY; i++) { continue; } */
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/* for(i=0; i<DELAY; i++) { continue; } */
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/* for(i=0; i<DELAY; i++) { continue; } */
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};
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}
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@ -17,7 +17,7 @@
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#define reg(x) (*(volatile uint32_t *)(x))
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#define DELAY 400000
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#define DELAY 100000
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#define DATA 0x00401000;
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#define NL "\033[K\r\n"
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@ -58,7 +58,7 @@ uint32_t ackBox[10];
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maca_control = (control_prm | control_asap | control_seq_rx); \
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}while(FALSE)
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#define PAYLOAD_LEN 16 /* not including the extra 4 bytes for len+fcs+somethingelse */
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#define PAYLOAD_LEN 8 /* not including the extra 4 bytes for len+fcs+somethingelse */
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/* maca dmatx needs extra 4 bytes for checksum */
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/* needs + 4 bytes for len(1 byte) + fcs(2 bytes) + somethingelse */
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#define command_xcvr_tx() \
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@ -139,10 +139,11 @@ void main(void) {
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reg(UART1_CON) = 0x00000003; /* enable receive and transmit */
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reg(GPIO_FUNC_SEL0) = ( (0x01 << (14*2)) | (0x01 << (15*2)) ); /* set GPIO15-14 to UART (UART1 TX and RX)*/
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reset_maca();
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radio_init();
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flyback_init();
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vreg_init();
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flyback_init();
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init_phy();
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set_power(0x0f); /* 0dbm */
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