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Renamed SPI_WAITFOREOTxBUF to SPI_WAITFORTxREADY for clarity and generalized SPI transmission status checks to work with both AVR and MSP430
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nifi
parent
9d7bdad864
commit
d4b619bcc5
@ -1,9 +1,22 @@
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/* -*- C -*- */
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/* @(#)$Id: spi.h,v 1.5 2009/08/31 12:06:34 nifi Exp $ */
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/* @(#)$Id: spi.h,v 1.6 2009/09/07 11:31:26 nifi Exp $ */
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#ifndef SPI_H
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#define SPI_H
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/* Define macros to use for checking SPI transmission status depending
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on if it is possible to wait for TX buffer ready. This is possible
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on for example MSP430 but not on AVR. */
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#ifdef SPI_WAITFORTxREADY
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#define SPI_WAITFORTx_BEFORE() SPI_WAITFORTxREADY()
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#define SPI_WAITFORTx_AFTER()
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#define SPI_WAITFORTx_ENDED() SPI_WAITFOREOTx()
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#else /* SPI_WAITFORTxREADY */
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#define SPI_WAITFORTx_BEFORE()
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#define SPI_WAITFORTx_AFTER() SPI_WAITFOREOTx()
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#define SPI_WAITFORTx_ENDED()
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#endif /* SPI_WAITFORTxREADY */
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extern unsigned char spi_busy;
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void spi_init(void);
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@ -20,8 +33,9 @@ void spi_init(void);
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#define FASTSPI_TX(x)\
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do {\
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SPI_WAITFOREOTxBUF();\
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SPI_WAITFORTx_BEFORE();\
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SPI_TXBUF = x;\
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SPI_WAITFORTx_AFTER();\
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} while(0)
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#define FASTSPI_RX(x)\
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@ -46,7 +60,7 @@ void spi_init(void);
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for (spiCnt = 0; spiCnt < (c); spiCnt++) {\
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FASTSPI_TX(((u8_t*)(p))[spiCnt]);\
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}\
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SPI_WAITFOREOTx();\
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SPI_WAITFORTx_ENDED();\
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} while(0)
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@ -94,7 +108,7 @@ void spi_init(void);
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FASTSPI_TX_ADDR(a);\
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FASTSPI_TX((u8_t) ((v) >> 8));\
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FASTSPI_TX((u8_t) (v));\
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SPI_WAITFOREOTx();\
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SPI_WAITFORTx_ENDED();\
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SPI_DISABLE();\
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} while (0)
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@ -135,7 +149,7 @@ void spi_init(void);
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for (i = 0; i < (c); i++) {\
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FASTSPI_TX(((u8_t*)(p))[i]);\
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}\
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SPI_WAITFOREOTx();\
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SPI_WAITFORTx_ENDED();\
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SPI_DISABLE();\
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} while (0)
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@ -145,7 +159,7 @@ void spi_init(void);
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for (u8_t spiCnt = 0; spiCnt < (c); spiCnt++) {\
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FASTSPI_TX(((u8_t*)(p))[spiCnt]);\
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}\
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SPI_WAITFOREOTx();\
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SPI_WAITFORTx_ENDED();\
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} while (0)
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#define FASTSPI_READ_FIFO_BYTE(b)\
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@ -212,7 +226,7 @@ void spi_init(void);
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for (n = 0; n < (c); n++) {\
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FASTSPI_TX(((u8_t*)(p))[n]);\
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}\
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SPI_WAITFOREOTx();\
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SPI_WAITFORTx_ENDED();\
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SPI_DISABLE();\
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} while (0)
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@ -1,5 +1,5 @@
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/* -*- C -*- */
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/* @(#)$Id: contiki-conf.h,v 1.5 2009/09/01 09:29:40 nifi Exp $ */
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/* @(#)$Id: contiki-conf.h,v 1.6 2009/09/07 11:31:26 nifi Exp $ */
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#ifndef CONTIKI_CONF_H
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#define CONTIKI_CONF_H
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@ -108,10 +108,10 @@ typedef unsigned long off_t;
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/* USART0 Tx ready? */
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#define SPI_WAITFOREOTx() while ((U0TCTL & TXEPT) == 0)
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/* USART0 Rx buffer ready? */
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/* USART0 Rx ready? */
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#define SPI_WAITFOREORx() while ((IFG1 & URXIFG0) == 0)
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/* USART0 Tx buffer ready? */
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#define SPI_WAITFOREOTxBUF() while ((IFG1 & UTXIFG0) == 0)
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#define SPI_WAITFORTxREADY() while ((IFG1 & UTXIFG0) == 0)
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#define SCK 1 /* P3.1 - Output: SPI Serial Clock (SCLK) */
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#define MOSI 2 /* P3.2 - Output: SPI Master out - slave in (MOSI) */
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@ -1,5 +1,5 @@
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/* -*- C -*- */
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/* @(#)$Id: contiki-conf.h,v 1.58 2009/08/31 12:06:35 nifi Exp $ */
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/* @(#)$Id: contiki-conf.h,v 1.59 2009/09/07 11:31:26 nifi Exp $ */
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#ifndef CONTIKI_CONF_H
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#define CONTIKI_CONF_H
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@ -172,10 +172,10 @@ typedef unsigned long off_t;
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/* USART0 Tx ready? */
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#define SPI_WAITFOREOTx() while ((U0TCTL & TXEPT) == 0)
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/* USART0 Rx buffer ready? */
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/* USART0 Rx ready? */
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#define SPI_WAITFOREORx() while ((IFG1 & URXIFG0) == 0)
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/* USART0 Tx buffer ready? */
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#define SPI_WAITFOREOTxBUF() while ((IFG1 & UTXIFG0) == 0)
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#define SPI_WAITFORTxREADY() while ((IFG1 & UTXIFG0) == 0)
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#define SCK 1 /* P3.1 - Output: SPI Serial Clock (SCLK) */
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#define MOSI 2 /* P3.2 - Output: SPI Master out - slave in (MOSI) */
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@ -26,7 +26,7 @@
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* @(#)$Id: xmem.c,v 1.9 2009/08/31 12:06:35 nifi Exp $
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* @(#)$Id: xmem.c,v 1.10 2009/09/07 11:31:26 nifi Exp $
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*/
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/**
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@ -78,7 +78,7 @@ write_enable(void)
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SPI_FLASH_ENABLE();
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FASTSPI_TX(SPI_FLASH_INS_WREN);
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SPI_WAITFOREOTx();
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SPI_WAITFORTx_ENDED();
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SPI_FLASH_DISABLE();
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splx(s);
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@ -95,7 +95,7 @@ read_status_register(void)
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SPI_FLASH_ENABLE();
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FASTSPI_TX(SPI_FLASH_INS_RDSR);
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SPI_WAITFOREOTx();
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SPI_WAITFORTx_ENDED();
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FASTSPI_CLEAR_RX();
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FASTSPI_RX(u);
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@ -137,7 +137,7 @@ erase_sector(unsigned long offset)
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FASTSPI_TX(offset >> 16); /* MSB */
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FASTSPI_TX(offset >> 8);
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FASTSPI_TX(offset >> 0); /* LSB */
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SPI_WAITFOREOTx();
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SPI_WAITFORTx_ENDED();
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SPI_FLASH_DISABLE();
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splx(s);
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@ -175,7 +175,7 @@ xmem_pread(void *_p, int size, unsigned long offset)
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FASTSPI_TX(offset >> 16); /* MSB */
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FASTSPI_TX(offset >> 8);
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FASTSPI_TX(offset >> 0); /* LSB */
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SPI_WAITFOREOTx();
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SPI_WAITFORTx_ENDED();
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FASTSPI_CLEAR_RX();
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for(; p < end; p++) {
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@ -213,7 +213,7 @@ program_page(unsigned long offset, const unsigned char *p, int nbytes)
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for(; p < end; p++) {
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FASTSPI_TX(~*p);
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}
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SPI_WAITFOREOTx();
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SPI_WAITFORTx_ENDED();
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SPI_FLASH_DISABLE();
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splx(s);
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