removed old include directory.

This commit is contained in:
Mariano Alvira 2010-03-02 17:53:09 -05:00
parent 1b4dd3b4dc
commit e9d8dbe5c5
6 changed files with 0 additions and 576 deletions

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#ifndef CRM_H
#define CRM_H
#define CRM_BASE (0x80003000)
#define CRM_SYS_CNTL (CRM_BASE+0x00)
#define CRM_WU_CNTL (CRM_BASE+0x04)
#define CRM_SLEEP_CNTL (CRM_BASE+0x08)
#define CRM_BS_CNTL (CRM_BASE+0x0c)
#define CRM_COP_CNTL (CRM_BASE+0x10)
#define CRM_COP_SERVICE (CRM_BASE+0x14)
#define CRM_STATUS (CRM_BASE+0x18)
#define CRM_MOD_STATUS (CRM_BASE+0x1c)
#define CRM_WU_COUNT (CRM_BASE+0x20)
#define CRM_WU_TIMEOUT (CRM_BASE+0x24)
#define CRM_RTC_COUNT (CRM_BASE+0x28)
#define CRM_RTC_TIMEOUT (CRM_BASE+0x2c)
#define CRM_CAL_CNTL (CRM_BASE+0x34)
#define CRM_CAL_COUNT (CRM_BASE+0x38)
#define CRM_RINGOSC_CNTL (CRM_BASE+0x3c)
#define CRM_XTAL_CNTL (CRM_BASE+0x40)
#define CRM_XTAL32_CNTL (CRM_BASE+0x44)
#define CRM_VREG_CNTL (CRM_BASE+0x48)
#define CRM_SW_RST (CRM_BASE+0x50)
/* wu_cntl bit locations */
#define EXT_WU_IEN 20 /* 4 bits */
#define EXT_WU_EN 4 /* 4 bits */
#define EXT_WU_EDGE 8 /* 4 bits */
#define EXT_WU_POL 12 /* 4 bits */
/* status bit locations */
#define EXT_WU_EVT 4 /* 4 bits */
#define enable_wu_en(k) (set_bit(reg32(CRM_WU_CNTL),(EXT_WU_EN+k-4)))
#endif

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/************************************************************************************
* This file holds type definitions that maps the standard c-types into types
* with guaranteed sizes. The types are target/platform specific and must be edited
* for each new target/platform.
*
* The header file also provides definitions for TRUE, FALSE and NULL.
*
* (c) Copyright 2006, Freescale Semiconductor, Inc. All rights reserved.
*
*
* No part of this document must be reproduced in any form - including copied,
* transcribed, printed or by any electronic means - without specific written
* permission from Freescale Semiconductor.
*************************************************************************************/
#ifndef _EMBEDDEDTYPES_H_
#define _EMBEDDEDTYPES_H_
/************************************************************************************
*
* TYPE DEFINITIONS
*
************************************************************************************/
typedef signed char int8_t;
typedef unsigned char uint8_t;
typedef signed short int16_t;
typedef unsigned short uint16_t;
typedef signed long int32_t;
typedef unsigned long uint32_t;
typedef signed long long int64_t;
typedef unsigned long long uint64_t;
typedef signed char intn8_t;
typedef unsigned char uintn8_t;
typedef signed short intn16_t;
typedef unsigned short uintn16_t;
typedef signed long intn32_t;
typedef unsigned long uintn32_t;
typedef signed long long intn64_t;
typedef unsigned long long uintn64_t;
/* boolean types */
typedef uint8_t bool_t;
typedef uintn8_t booln_t;
/* used for indexing into an array in the most efficient manner for the platform */
typedef uint8_t index_t;
#define BIT0 0x00000001UL
#define BIT1 0x00000002UL
#define BIT2 0x00000004UL
#define BIT3 0x00000008UL
#define BIT4 0x00000010UL
#define BIT5 0x00000020UL
#define BIT6 0x00000040UL
#define BIT7 0x00000080UL
#define BIT8 0x00000100UL
#define BIT9 0x00000200UL
#define BIT10 0x00000400UL
#define BIT11 0x00000800UL
#define BIT12 0x00001000UL
#define BIT13 0x00002000UL
#define BIT14 0x00004000UL
#define BIT15 0x00008000UL
#define BIT16 0x00010000UL
#define BIT17 0x00020000UL
#define BIT18 0x00040000UL
#define BIT19 0x00080000UL
#define BIT20 0x00100000UL
#define BIT21 0x00200000UL
#define BIT22 0x00400000UL
#define BIT23 0x00800000UL
#define BIT24 0x01000000UL
#define BIT25 0x02000000UL
#define BIT26 0x04000000UL
#define BIT27 0x08000000UL
#define BIT28 0x10000000UL
#define BIT29 0x20000000UL
#define BIT30 0x40000000UL
#define BIT31 0x80000000UL
#define TRUE 1
#define FALSE 0
#ifndef NULL
#define NULL (( void * )( 0 ))
#endif
/* indicate endian-ness of this MCU */
#define gBigEndian_c FALSE
typedef uint32_t zbClock32_t;
typedef uint32_t zbClock24_t;
typedef uint16_t zbClock16_t;
/* common macros to reduce code size in S08 */
#if (gBigEndian_c)
#define IsEqual2Bytes(aVal1, aVal2) (*((uint16_t *)(aVal1)) == *((uint16_t *)(aVal2)))
#define Copy2Bytes(aVal1, aVal2) (*((uint16_t *)(aVal1)) = *((uint16_t *)(aVal2)))
#define Set2Bytes(aVal1, iVal2) (*((uint16_t *)(aVal1)) = (iVal2))
#define IsEqual2BytesInt(aVal1, iVal2) (*((uint16_t *)(aVal1)) == (iVal2))
#define TwoBytesToUint16(aVal) ( *((uint16_t *)(aVal)) )
#define FourBytesToUint32(aVal) ( *((uint32_t *)(aVal)) )
#define TwoBytes2Byte(aVal) ( (uint8_t)( *( ( uint16_t * )(aVal) ) ) )
#define Cmp2BytesToZero(aVal) (!( TwoBytesToUint16(aVal) ))
#define Inc4Bytes(aVal1, iVal2) ( *((uint32_t *)(aVal1)) += (iVal2))
#else
#define Copy2Bytes(aVal1, aVal2) (FLib_MemCpy((void *)aVal1,(void *) aVal2, 2))
void Set2Bytes(void *ptr, uint16_t val);
bool_t IsEqual2BytesInt(void *ptr, uint16_t val);
//#define Set2Bytes(aVal1, iVal2) (*((uint16_t *)(aVal1)) = (iVal2))
//#define IsEqual2BytesInt(aVal1, iVal2) (*((uint16_t *)(aVal1)) == (iVal2))
#define TwoBytesToUint16(aVal) ( ((uint16_t)(*((uint8_t *)(aVal))))|(((uint16_t)(*(((uint8_t *)(aVal))+1)))<<8) )
#define FourBytesToUint32(aVal) ( ((uint32_t)TwoBytesToUint16(aVal))|(((uint32_t)TwoBytesToUint16(((uint8_t*)aVal)+2))<<16) )
#define TwoBytes2Byte(aVal) ( (uint8_t)( *( ( uint8_t * )(aVal) ) ) )
#define Cmp2BytesToZero(aVal) (!( TwoBytesToUint16(aVal) ))
void Inc4Bytes(uint8_t* aVal1, uint32_t Val2);
#define IsEqual2Bytes(aVal1, aVal2) (TwoBytesToUint16(aVal1) == TwoBytesToUint16(aVal2))
#endif /* #if (gBigEndian_c) */
/* allow for routines/variables to be static or not at compile-time. */
#define STATIC
/* add assert codes if needed. Calls assert function. */
typedef uint8_t assertCode_t;
void BeeAppAssert(assertCode_t code);
#define gAssertCode_NoTasks_c 0x01 /* not enough tasks. Increase gTsMaxTasks_c */
#define gAssertCode_NoTimers_c 0x02 /* not enough timers. Increase gTmrApplicationTimers_c */
#define gAssertCode_PageTooBig_c 0x04 /* An NVM page is to big to be stored. */
#define gMaxIndex_c 0xfe
#endif /* _EMBEDDEDTYPES_H_ */

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/*
* Defines and Macros for Interrupt-Service-Routines
* collected and partly created by
* Martin Thomas <mthomas@rhrk.uni-kl.de>
*
* Copyright 2005 M. Thomas
* No guarantees, warrantees, or promises, implied or otherwise.
* May be used for hobby or commercial purposes provided copyright
* notice remains intact.
*/
#ifndef interrupt_utils_
#define interrupt_utils_
/*
The following defines are usefull for
interrupt service routine declarations.
*/
/*
RAMFUNC
Attribute which defines a function to be located
in memory section .fastrun and called via "long calls".
See linker-skript and startup-code to see how the
.fastrun-section is handled.
The definition is not only useful for ISRs but since
ISRs should be executed fast the macro is defined in
this header.
*/
#define RAMFUNC __attribute__ ((long_call, section (".fastrun")))
/*
INTFUNC
standard attribute for arm-elf-gcc which marks
a function as ISR (for the VIC). Since gcc seems
to produce wrong code if this attribute is used in
thumb/thumb-interwork the attribute should only be
used for "pure ARM-mode" binaries.
*/
#define INTFUNC __attribute__ ((interrupt("IRQ")))
/*
NACKEDFUNC
gcc will not add any code to a function declared
"nacked". The user has to take care to save registers
and add the needed code for ISR functions. Some
macros for this tasks are provided below.
*/
#define NACKEDFUNC __attribute__((naked))
/******************************************************************************
*
* MACRO Name: ISR_STORE()
*
* Description:
* This MACRO is used upon entry to an ISR with interrupt nesting.
* Should be used together with ISR_ENABLE_NEST(). The MACRO
* performs the following steps:
*
* 1 - Save the non-banked registers r0-r12 and lr onto the IRQ stack.
*
*****************************************************************************/
#define ISR_STORE() asm volatile( \
"STMDB SP!,{R0-R12,LR}\n" )
/******************************************************************************
*
* MACRO Name: ISR_RESTORE()
*
* Description:
* This MACRO is used upon exit from an ISR with interrupt nesting.
* Should be used together with ISR_DISABLE_NEST(). The MACRO
* performs the following steps:
*
* 1 - Load the non-banked registers r0-r12 and lr from the IRQ stack.
* 2 - Adjusts resume adress
*
*****************************************************************************/
#define ISR_RESTORE() asm volatile( \
"LDMIA SP!,{R0-R12,LR}\n" \
"SUBS R15,R14,#0x0004\n" )
/******************************************************************************
*
* MACRO Name: ISR_ENABLE_NEST()
*
* Description:
* This MACRO is used upon entry from an ISR with interrupt nesting.
* Should be used after ISR_STORE.
*
*****************************************************************************/
#define ISR_ENABLE_NEST() asm volatile( \
"MRS LR, SPSR \n" \
"STMFD SP!, {LR} \n" \
"MSR CPSR_c, #0x1f \n" \
"STMFD SP!, {LR} " )
/******************************************************************************
*
* MACRO Name: ISR_DISABLE_NEST()
*
* Description:
* This MACRO is used upon entry from an ISR with interrupt nesting.
* Should be used before ISR_RESTORE.
*
*****************************************************************************/
#define ISR_DISABLE_NEST() asm volatile( \
"LDMFD SP!, {LR} \n" \
"MSR CPSR_c, #0x92 \n" \
"LDMFD SP!, {LR} \n" \
"MSR SPSR_cxsf, LR \n" )
/*
* The following marcos are from the file "armVIC.h" by:
*
* Copyright 2004, R O SoftWare
* No guarantees, warrantees, or promises, implied or otherwise.
* May be used for hobby or commercial purposes provided copyright
* notice remains intact.
*
*/
/******************************************************************************
*
* MACRO Name: ISR_ENTRY()
*
* Description:
* This MACRO is used upon entry to an ISR. The current version of
* the gcc compiler for ARM does not produce correct code for
* interrupt routines to operate properly with THUMB code. The MACRO
* performs the following steps:
*
* 1 - Adjust address at which execution should resume after servicing
* ISR to compensate for IRQ entry
* 2 - Save the non-banked registers r0-r12 and lr onto the IRQ stack.
* 3 - Get the status of the interrupted program is in SPSR.
* 4 - Push it onto the IRQ stack as well.
*
*****************************************************************************/
#define ISR_ENTRY() asm volatile(" sub lr, lr,#4\n" \
" stmfd sp!,{r0-r12,lr}\n" \
" mrs r1, spsr\n" \
" stmfd sp!,{r1}")
/******************************************************************************
*
* MACRO Name: ISR_EXIT()
*
* Description:
* This MACRO is used to exit an ISR. The current version of the gcc
* compiler for ARM does not produce correct code for interrupt
* routines to operate properly with THUMB code. The MACRO performs
* the following steps:
*
* 1 - Recover SPSR value from stack
* 2 - and restore its value
* 3 - Pop the return address & the saved general registers from
* the IRQ stack & return
*
*****************************************************************************/
#define ISR_EXIT() asm volatile(" ldmfd sp!,{r1}\n" \
" msr spsr_c,r1\n" \
" ldmfd sp!,{r0-r12,pc}^")
/******************************************************************************
*
* Function Name: disableIRQ()
*
* Description:
* This function sets the IRQ disable bit in the status register
*
* Calling Sequence:
* void
*
* Returns:
* previous value of CPSR
*
*****************************************************************************/
unsigned disableIRQ(void);
/******************************************************************************
*
* Function Name: enableIRQ()
*
* Description:
* This function clears the IRQ disable bit in the status register
*
* Calling Sequence:
* void
*
* Returns:
* previous value of CPSR
*
*****************************************************************************/
unsigned enableIRQ(void);
/******************************************************************************
*
* Function Name: restoreIRQ()
*
* Description:
* This function restores the IRQ disable bit in the status register
* to the value contained within passed oldCPSR
*
* Calling Sequence:
* void
*
* Returns:
* previous value of CPSR
*
*****************************************************************************/
unsigned restoreIRQ(unsigned oldCPSR);
/******************************************************************************
*
* Function Name: disableFIQ()
*
* Description:
* This function sets the FIQ disable bit in the status register
*
* Calling Sequence:
* void
*
* Returns:
* previous value of CPSR
*
*****************************************************************************/
unsigned disableFIQ(void);
/******************************************************************************
*
* Function Name: enableFIQ()
*
* Description:
* This function clears the FIQ disable bit in the status register
*
* Calling Sequence:
* void
*
* Returns:
* previous value of CPSR
*
*****************************************************************************/
unsigned enableFIQ(void);
/******************************************************************************
*
* Function Name: restoreFIQ()
*
* Description:
* This function restores the FIQ disable bit in the status register
* to the value contained within passed oldCPSR
*
* Calling Sequence:
* void
*
* Returns:
* previous value of CPSR
*
*****************************************************************************/
unsigned restoreFIQ(unsigned oldCPSR);
#endif

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#ifndef __SYS_INTERRUPT_H
#define __SYS_INTERRUPT_H
/* Returns true if it handled an active interrupt */
typedef int (*SystemInterruptFunc)();
typedef struct _SystemInterruptHandler SystemInterruptHandler;
struct _SystemInterruptHandler
{
SystemInterruptHandler *next;
SystemInterruptFunc handler;
};
void
sys_interrupt_enable();
void
sys_interrupt_disable();
void
sys_interrupt_append_handler(SystemInterruptHandler *handler);
void
sys_interrupt_prepend_handler(SystemInterruptHandler *handler);
void
sys_interrupt_remove_handler(SystemInterruptHandler *handler);
#endif /* __SYS_INTERRUPT_H */

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/* Timer registers are all 16-bit wide with 16-bit access only */
#define TMR_OFFSET (0x20)
#define TMR_BASE (0x80007000)
#define TMR0_BASE (TMR_BASE)
#define TMR1_BASE (TMR_BASE + TMR_OFFSET*1)
#define TMR2_BASE (TMR_BASE + TMR_OFFSET*2)
#define TMR3_BASE (TMR_BASE + TMR_OFFSET*3)
#define TMR_REGOFF_COMP1 (0x0)
#define TMR_REGOFF_COMP2 (0x2)
#define TMR_REGOFF_CAPT (0x4)
#define TMR_REGOFF_LOAD (0x6)
#define TMR_REGOFF_HOLD (0x8)
#define TMR_REGOFF_CNTR (0xa)
#define TMR_REGOFF_CTRL (0xc)
#define TMR_REGOFF_SCTRL (0xe)
#define TMR_REGOFF_CMPLD1 (0x10)
#define TMR_REGOFF_CMPLD2 (0x12)
#define TMR_REGOFF_CSCTRL (0x14)
#define TMR_REGOFF_ENBL (0x1e)
/* one enable register to rule them all */
#define TMR_ENBL TMR0_BASE + TMR_REGOFF_ENBL
/* Timer 0 registers */
#define TMR0_COMP1 (TMR0_BASE + TMR_REGOFF_COMP1)
#define TMR0_COMP_UP TMR0_COMP1
#define TMR0_COMP2 (TMR0_BASE + TMR_REGOFF_COMP2)
#define TMR0_COMP_DOWN TMR0_COMP2
#define TMR0_CAPT (TMR0_BASE + TMR_REGOFF_CAPT)
#define TMR0_LOAD (TMR0_BASE + TMR_REGOFF_LOAD)
#define TMR0_HOLD (TMR0_BASE + TMR_REGOFF_HOLD)
#define TMR0_CNTR (TMR0_BASE + TMR_REGOFF_CTRL)
#define TMR0_CTRL (TMR0_BASE + TMR_REGOFF_CTRL)
#define TMR0_SCTRL (TMR0_BASE + TMR_REGOFF_SCTRL)
#define TMR0_CMPLD1 (TMR0_BASE + TMR_REGOFF_CMPLD1)
#define TMR0_CMPLD2 (TMR0_BASE + TMR_REGOFF_CMPLD2)
#define TMR0_CSCTRL (TMR0_BASE + TMR_REGOFF_CSCTRL)
/* Timer 1 registers */
#define TMR1_COMP1 (TMR1_BASE + TMR_REGOFF_COMP1)
#define TMR1_COMP_UP TMR1_COMP1
#define TMR1_COMP2 (TMR1_BASE + TMR_REGOFF_COMP2)
#define TMR1_COMP_DOWN TMR1_COMP2
#define TMR1_CAPT (TMR1_BASE + TMR_REGOFF_CAPT)
#define TMR1_LOAD (TMR1_BASE + TMR_REGOFF_LOAD)
#define TMR1_HOLD (TMR1_BASE + TMR_REGOFF_HOLD)
#define TMR1_CNTR (TMR1_BASE + TMR_REGOFF_CTRL)
#define TMR1_CTRL (TMR1_BASE + TMR_REGOFF_CTRL)
#define TMR1_SCTRL (TMR1_BASE + TMR_REGOFF_SCTRL)
#define TMR1_CMPLD1 (TMR1_BASE + TMR_REGOFF_CMPLD1)
#define TMR1_CMPLD2 (TMR1_BASE + TMR_REGOFF_CMPLD2)
#define TMR1_CSCTRL (TMR1_BASE + TMR_REGOFF_CSCTRL)
/* Timer 2 registers */
#define TMR2_COMP1 (TMR2_BASE + TMR_REGOFF_COMP1)
#define TMR2_COMP_UP TMR2_COMP1
#define TMR2_COMP2 (TMR2_BASE + TMR_REGOFF_COMP2)
#define TMR2_COMP_DOWN TMR2_COMP2
#define TMR2_CAPT (TMR2_BASE + TMR_REGOFF_CAPT)
#define TMR2_LOAD (TMR2_BASE + TMR_REGOFF_LOAD)
#define TMR2_HOLD (TMR2_BASE + TMR_REGOFF_HOLD)
#define TMR2_CNTR (TMR2_BASE + TMR_REGOFF_CTRL)
#define TMR2_CTRL (TMR2_BASE + TMR_REGOFF_CTRL)
#define TMR2_SCTRL (TMR2_BASE + TMR_REGOFF_SCTRL)
#define TMR2_CMPLD1 (TMR2_BASE + TMR_REGOFF_CMPLD1)
#define TMR2_CMPLD2 (TMR2_BASE + TMR_REGOFF_CMPLD2)
#define TMR2_CSCTRL (TMR2_BASE + TMR_REGOFF_CSCTRL)
/* Timer 3 registers */
#define TMR3_COMP1 (TMR3_BASE + TMR_REGOFF_COMP1)
#define TMR3_COMP_UP TMR3_COMP1
#define TMR3_COMP2 (TMR3_BASE + TMR_REGOFF_COMP2)
#define TMR3_COMP_DOWN TMR3_COMP2
#define TMR3_CAPT (TMR3_BASE + TMR_REGOFF_CAPT)
#define TMR3_LOAD (TMR3_BASE + TMR_REGOFF_LOAD)
#define TMR3_HOLD (TMR3_BASE + TMR_REGOFF_HOLD)
#define TMR3_CNTR (TMR3_BASE + TMR_REGOFF_CTRL)
#define TMR3_CTRL (TMR3_BASE + TMR_REGOFF_CTRL)
#define TMR3_SCTRL (TMR3_BASE + TMR_REGOFF_SCTRL)
#define TMR3_CMPLD1 (TMR3_BASE + TMR_REGOFF_CMPLD1)
#define TMR3_CMPLD2 (TMR3_BASE + TMR_REGOFF_CMPLD2)
#define TMR3_CSCTRL (TMR3_BASE + TMR_REGOFF_CSCTRL)

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#ifndef UTILS_H
#define UTILS_H
#define reg32(x) (*(volatile uint32_t *)(x))
#define reg16(x) (*(volatile uint16_t *)(x))
#define bit(bit) (1<<bit)
#define bit_is_set(val,bit) (((val & (1<<bit)) >> bit) == 1)
#define clear_bit(val,bit) (val=(val & ~(1<<bit)))
#define set_bit(val,bit) (val=(val | (1<<bit)))
#endif