Commit Graph

1518 Commits

Author SHA1 Message Date
Jens Dede
119291d083 Fix putchar include when using IPv4 2016-05-02 19:13:26 +02:00
George Oikonomou
00d5645d16 Merge pull request #1601 from philrhinehart/bugfix-cc26xx-ble-events
cc26xx-cc13xx BLE beacon event issue
2016-04-18 20:06:33 +01:00
Phil Rhinehart
5d5544151f Fixed bug in cc26xx-cc13xx rf-core. When running BLE in conjunction with ContikiMAC, oscillators were modified from an interrupt state causing occasional bus faults and infinite loops. We now check if BLE is active prior to modifiying the oscillators to avoid these conditions. 2016-04-18 17:17:07 +08:00
Phil Rhinehart
2a07dc0e0a This fixes an event handling issue in the cc26xx BLE driver. Currently, the rf_ble_beacon_process triggers the BLE beacon upon receiving any event, rather than verifying that the event timer has expired. This means that any PROCESS_BROADCAST (e.g. any sensor event) will fire the beacon. This commit adds logic to prevent this. 2016-04-18 17:14:37 +08:00
Oliver Schmidt
2c48f3b232 Added compatibility with W5100 shared access.
If the setup of socket 0 to 3 with 4+2+1+1KB is detected then the W5100 is _not_ initialized, otherwise it does set up socket 0 and 1 with 4KB each. Either way socket 0 is used - now with 4KB instead of 8KB as before.
2016-04-05 21:11:19 +02:00
Oliver Schmidt
4f28289df2 Added a pfs_remove() function and a pfs_seek() stub to the Commodore platforms.
- "Normalized" some Assembly code.
- Implemented CFS_APPEND in pfs_open().
- Made CFS_WRITE work in VICE's virtual disk/file system.
2016-03-28 14:07:35 +02:00
Michael LeMay
93126b57bb x86, galileo: Use IMRs to restrict DMA
This patch configures Isolated Memory Regions (IMRs) to block DMA to
code and data regions that do not contain any data that needs to be
DMA-accessible.
2016-03-17 08:35:49 -07:00
Michael LeMay
58a00b7c23 x86, galileo: Add driver for Isolated Memory Regions (IMRs)
The Intel Quark X1000 SoC includes support for Isolated Memory Regions
(IMRs), which are specified using range registers and associated
control registers that are accessible via the message bus.  This patch
adds a driver for accessing those registers.
2016-03-17 08:35:49 -07:00
Michael LeMay
25c07613c2 x86: Add driver for message bus
The Intel Quark X1000 SoC includes a message bus that is accessible
via PCI configuration registers.  It communicates to various SoC
components such as the Isolated Memory Region (IMR) registers and the
Remote Management Unit.  This patch adds a driver for accessing the
message bus.
2016-03-17 08:35:48 -07:00
Nicolas Tsiftes
9ab327090c Merge pull request #1444 from mdlemay/galileo-always-init-gpio
galileo: Enable I2C and GPIO interrupt sharing and centralize their initialization
2016-03-14 20:09:40 +01:00
Simon Duquennoy
dea04c67d7 Change the default IPv6 prefix from aaaa::/64 to fd00::/64 2016-03-07 17:47:44 +01:00
Michael LeMay
58874ea25d x86, galileo: Refactor I2C and GPIO initialization
This patch revises the I2C and GPIO initialization code to always be
run during platform boot rather than within each process that requires
it.

This patch also revises the gpio-output example to use a pin that is
set as an output by the default pinmux configuration.  Previously, it
used a pin that was set as an output by the pinmux configuration that
is in effect when the OS does not change the pinmux configuration.
2016-02-16 21:19:44 -08:00
Michael LeMay
c815fa4511 x86: Use shared ISR for I2C and GPIO
This patch permits interrupts to be generated by both the I2C and GPIO
controllers for simultaneously-executing applications. The controllers
share a single interrupt pin, INTC. Prior to this patch,
quarkX1000_gpio_init() routed INTA to PIRQC and IRQ 10 (due to an
incorrect assumption that INTA is connected to the GPIO controller),
and quarkX1000_i2c_init() routed INTC to PIRQC and IRQ 9. The I2C
controller initialization is a prerequisite for GPIO initialization,
so the final configuration was that INTA and INTC were both routed to
PIRQC and IRQ 10. Thus, only the GPIO ISR was being invoked, even if
the I2C controller was actually responsible for the interrupt.

This patch refactors the I2C and GPIO ISR setup and handler code so
that the shared portions are combined in
cpu/x86/drivers/legacy_pc/shared-isr.[ch].  The I2C and GPIO drivers
communicate their interrupt information to the shared component by
placing structures in a specific section of the binary.
2016-02-16 21:19:44 -08:00
George Oikonomou
d42b1b50e5 Allow the caller to access the entire content of CMDSTA
When sending a command to the CC13xx/CC25xx RF core, we wait for command completion by checking the LSB of CMDSTA (correctly so). However, in doing so we also zero out the 3 CMDSTA return bytes. For some commands, those bytes contain useful information (e.g. an RSSI value) and are required by the caller.

This problem manifests itself e.g. in PROP mode `channel_clear()`, whereby the caller will always see an RSSI value of 0.

This pull therefore fixes the logic in `rf_core_send_cmd()` to check for command completion by blocking on the CMDSTA result byte without zeroing out the 3 return bytes.

Fixes #1465
2016-01-24 13:39:14 +00:00
George Oikonomou
707353f71b Remove Sensinode platform, cpu, example and tools files
This is part of a set of commits that will obsolete the Sensinode platform
2016-01-10 15:01:58 +00:00
George Oikonomou
ab59a387b3 Merge pull request #1371 from g-oikonomou/bugfix/cc26xx/lpm-operation
Improve the stability of CC13xx/CC26xx low-power operation
2016-01-09 18:07:47 +00:00
George Oikonomou
b97a3d1049 Merge pull request #1242 from g-oikonomou/contrib/cc26xx-ieee-volatile-cmd-ieee-tx
Use volatile access for CMD_IEEE_TX
2016-01-09 18:01:40 +00:00
George Oikonomou
3a831cbebf Merge pull request #1322 from g-oikonomou/bugfix/cc26xx/interrupt-flag-management
Clear CC26xx/CC13xx interrupt flags selectively
2016-01-09 18:01:15 +00:00
George Oikonomou
109696174f Merge pull request #1350 from g-oikonomou/bugfix/cc26xx/tx-power
Correctly set new CC26xx TX power when the RFC is powered off
2016-01-09 17:59:24 +00:00
George Oikonomou
fa002c2d73 Merge pull request #1321 from g-oikonomou/bugfix/cc26xx/remove-redundant-reads
Remove redundant function calls in CC13xx/CC26xx RFC code
2016-01-09 17:52:15 +00:00
Benoît Thébaudeau
92d8f95cba cc2538: Fix GCC 5 warning
Fix the following warning issued by GCC ARM Embedded 5-2015-q4-major:

  ../../cpu/cc2538/dev/udma.c: In function 'udma_init':
  ../../cpu/cc2538/dev/udma.c:59:10: warning: passing argument 1 of 'memset' discards 'volatile' qualifier from pointer target type [-Wdiscarded-array-qualifiers]
     memset(&channel_config, 0, sizeof(channel_config));
            ^
  In file included from <toolchain-path>/arm-none-eabi/include/string.h:10:0,
                   from ../../platform/cc2538dk/./contiki-conf.h:12,
                   from ../../cpu/cc2538/dev/udma.c:38:
  <toolchain-path>/arm-none-eabi/include/string.h:25:7: note: expected 'void *' but argument is of type 'volatile struct channel_ctrl (*)[4]'
   _PTR  _EXFUN(memset,(_PTR, int, size_t));
         ^

Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau.dev@gmail.com>
2016-01-09 15:43:20 +01:00
Benoît Thébaudeau
f78a132395 cc2538: pka: Fix include paths breakage
The PKA drivers and examples were full of include paths missing the
appropriate prefix, or using angle brackets instead of double quotes or
the other way around.

Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau.dev@gmail.com>
2016-01-09 15:43:13 +01:00
Benoît Thébaudeau
ccceb63e88 cc2538: Add crypto driver and example for AES-GCM
Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau.dev@gmail.com>
2016-01-06 23:22:54 +01:00
Benoît Thébaudeau
e77e9861fe cc2538: Add crypto driver and example for AES-CBC-MAC
Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau.dev@gmail.com>
2016-01-06 23:22:53 +01:00
Benoît Thébaudeau
47c24cab11 cc2538: Add crypto driver and example for AES-CTR
Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau.dev@gmail.com>
2016-01-06 23:22:53 +01:00
Benoît Thébaudeau
cf5e9557f8 cc2538: Add crypto driver and example for AES-CBC
Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau.dev@gmail.com>
2016-01-06 22:01:41 +01:00
Benoît Thébaudeau
69eacbddbe cc2538: Add AES-CCM* driver
Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau.dev@gmail.com>
2016-01-04 00:28:27 +01:00
kkrentz
24cb05059a CC2538: Add AES-128 driver 2016-01-04 00:28:27 +01:00
Benoît Thébaudeau
3dbe4c9403 cc2538: Add crypto driver and example for AES-ECB
Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau.dev@gmail.com>
2016-01-04 00:28:26 +01:00
Benoît Thébaudeau
04890b1899 cc2538: ccm: Allow separate input/output buffers
This is supported by the hardware, so give access to this feature in the
API.

Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau.dev@gmail.com>
2016-01-04 00:28:26 +01:00
Benoît Thébaudeau
baef75752e cc2538: aes: Add support for generic operations
Add generic AES functions that should be able to support all the modes
of operation of the hardware AES crypto engine, i.e. ECB, CBC, CTR,
CBC-MAC, GCM, and CCM.

This makes it possible to easily implement these modes of operation
without duplicating code.

Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau.dev@gmail.com>
2016-01-04 00:26:32 +01:00
Michael LeMay
52d75dce0d x86: Remove spurious UEFI-related info message
This patch removes a spurious info message in a UEFI-related portion
of a Makefile.
2015-12-21 08:06:14 -02:00
Michael LeMay
0e99ebbded x86: Add support for 32-bit build hosts in build_uefi.sh
This patch adds support for building the UEFI EDK2 tools on 32-bit
hosts.  It also revises the script to support rebuilding the tools
when the script is re-invoked after the EDK2 repository has previously
been downloaded.
2015-12-21 08:06:14 -02:00
Michael LeMay
e297177a69 x86: Streamline MMIO accesses in GPIO and I2C drivers
This patch refactors the MMIO routines in the GPIO and I2C drivers to
eliminate the base_addr parameter that specifies the MMIO base
address.  Instead, just the MMIO routines themselves retrieve the base
address from the driver structure.
2015-12-21 08:06:14 -02:00
Michael LeMay
f85654a82f x86, galileo: Add UEFI support
This patch adds support for optionally building EFI binaries in
addition to Multiboot ELF binaries.  It includes a script,
build_uefi.sh, that downloads tool and library sources from the EDK II
project, builds the GenFw tool that is used to create UEFI binaries,
and creates a makefile that is included from the main x86 common
makefile and enables UEFI support in the Contiki build system.  If the
script is not run prior to building Contiki, then an informational
message will be displayed with instructions for running build_uefi.sh
if UEFI support is desired.  This patch also adds the path to the
auto-generated makefile to .gitignore.

This patch modifies the linker script for the Intel Quark X1000 to
account for the output file section offsets and alignment expectations
of the EDK II GenFw project.

This patch also adds a newlib patch to remove the weak symbol
attribute from floating point stdio support routines.  See
<newlib>/newlib/README for an explanation of how the newlib developers
intended for _printf_float and _scanf_float to be linked.  Newlib
declares them as weak symbols with the intention that developers would
force them to be linked only when needed using a linker command line
option.  However, some but not all Contiki programs require them, so
we cannot simply always include or exclude them.  Instead, we remove
the weak symbol attributes and rely on the linker to automatically
determine whether or not they should be linked.  This avoids an issue
in which weak symbols were undefined in the intermediate DLL generated
as part of the UEFI build process.  That resulted in the GenFw program
emitting "ERROR 3000" messages when it encountered relocations
referencing such an undefined symbol.

Finally, this patch updates README.md to both make some revisions to
account for the UART support introduced in previous patches as well as
to provide instructions for using the UEFI support.
2015-12-21 08:06:14 -02:00
Michael LeMay
b915e7d5e3 galileo: Omit exception handling unwind tables
This patch modifies the newlib and Contiki C and C++ compiler flags to
omit exception handling unwind tables (see
http://wiki.dwarfstd.org/index.php?title=Exception_Handling).
Removing these tables saves space in debug builds and has not caused
any readily-apparent functional changes.

Here is the size listing for an example program built without this
patch:
   text	   data	    bss	    dec	    hex	filename
  76002	   1508	  21224	  98734	  181ae	all-timers.galileo

Here is the size listing for the same program with this patch:
   text	   data	    bss	    dec	    hex	filename
  72918	   1508	  21224	  95650	  175a2	all-timers.galileo

The primary motivation for this patch is to help enable UEFI support.
The .eh_frame and .eh_frame_hdr sections that are otherwise generated
are treated as code sections by the EDK2 GenFw program, since they are
read-only alloc sections.  They get grouped with the actual code
sections, ahead of the data sections.  This perturbs symbols and
complicates debugging.
2015-12-21 08:06:14 -02:00
Michael LeMay
abeed93da5 x86: Add driver for Intel Quark X1000 built-in Ethernet
This patch adds a simple, space-efficient driver for the Ethernet
interface built into the Intel Quark X1000.  It only allocates a
single packet descriptor for each of the transmit and receive
directions, computes checksums on the CPU, and enables
store-and-forward mode for both transmit and receive directions.
2015-12-21 08:06:14 -02:00
Ricardo de Almeida Gonzaga
4726bc3313 x86: Add Intel Quark X1000 GPIO Controller (non-legacy) interrupt support
Since Galileo pinmux is available, this patch adds interrupt support
for GPIO Controller (non-legacy).
2015-12-21 08:06:14 -02:00
Ricardo de Almeida Gonzaga
495dcd659a x86: Add PCAL9535A support
This patch adds gpio-pcal9535a.c and gpio-pcal9535a.h files,
which support access to I2C-based PCAL9535A GPIO controller
configuration register through a function interface.

The PCAL9535A is a low-voltage 16-bit GPIO expander with interrupt
and reset for I2C-bus/SMBus applications. It contains the PCA9535
register set of four pairs of 8-bit Configuration, Input, Output,
and Polarity Inversion registers, and additionally, the PCAL9535A has
Agile I/O, which are additional features specifically designed to
enhance the I/O. More about PCAL9535A can be found in its datasheet[1].

This driver is needed in order to configure Galileo pinmux.

[1] - http://www.nxp.com/documents/data_sheet/PCAL9535A.pdf
2015-12-21 08:06:14 -02:00
Ricardo de Almeida Gonzaga
a27af5b395 x86: Add Intel Quark X1000 I2C support
This patch adds the i2c.c, i2c.h and i2c-registers.h files,
which support access to I2C controller configuration register
through a function interface.
2015-12-21 08:06:14 -02:00
Ricardo de Almeida Gonzaga
2d552285cd x86: Add Intel Quark X1000 GPIO Controller (non-legacy) support
This patch adds the gpio.c and gpio.h files, which support
access to GPIO Controller (non-legacy) configuration register
through a function interface.

It doesn't add interrupt support due to pinmux reasons. On
Galileo Gen 2 we need to configure a pin as input/interrupt
using pinmux and this can only be achieved through I2C. There's
one pin exported by default as GPIO output and we used this one
to test this driver.

In the future, we plan to add an I2C driver and a pinmux configuration
driver in order to solve this kind of problems.
2015-12-21 08:06:14 -02:00
Ricardo de Almeida Gonzaga
60f6edef80 x86: Add support for PCI BAR1
This patch adds support for PCI BAR1 and also changes
the pci_init(), instead of having one function for each `bar`
we now set the `bar` to pci_config_addr_t parameter before calling
the pci_init() function..
2015-12-21 08:06:14 -02:00
Michael LeMay
6dc27579bc x86: Extend PCI driver module with support for metadata and configuration writes
This patch adds the 'meta' field to the generic driver structure to
point to optional driver-defined metadata.  It also modifies the
associated initialization routine to populate it and updates the 16X50
UART driver to use the new initialization routine signature.  This
patch also adds a function to perform PCI configuration register
writes, definitions for the PCI Command configuration register address
and some of the bits in that register, and a function to set
additional bits in that register.  Finally, it adds macros to help
with performing MMIO to and from PCI devices.
2015-12-21 08:06:14 -02:00
Andre Guedes
c6ef8454a1 x86: Use -O0 instead of -Og for debug build
This patch replaces the gcc option '-Og' by '-O0' which is used when
building debugging binaries. The motivation for this change comes
from the fact that we have found at least one optimization done by
'-Og' that interfered with one of our debugging sessions.
2015-12-21 08:06:14 -02:00
Andre Guedes
6b433aede1 x86: Improve release binary size
This patch adds -ffunction-sections and -fdata-sections to the
'release' CFLAGS so each function and data is place into its
own section in the output file. It also adds --gc-section to
the 'release' LDFLAGS so the linker removes the sections which
are not referenced.

This patch also adds -ffunction-sections and -fdata-sections
options to CFLAGS from build_newlib.sh. This increases newlib
static libraries size, however, the Contiki image shrinks even
more since --gc-section removes "dead code" from newlib.

As a practical effect, all unused function and data (as well as
sections such as .eh_frame) are striped out from the final elf
binary. This shrinks our release binary drastically.

Finally, to prevent --gc-section from removing .multiboot section,
this patch adds KEEP(*(.multiboot)) to quarkX1000.ld.
2015-12-21 08:06:14 -02:00
Ricardo de Almeida Gonzaga
c796e270bf x86: Add Intel Quark X1000 PCI Interrupt Routing support
PCI Interrupt Routing is mapped using Interrupt Queue Agents
IRQAGENT[0:3] and aggregating the INT[A:D] interrupts for each
PCI-mapped device in the SoC.

PCI based interrupts PIRQ[A:H] are then available for consumption
by either the 8259 PICs or the IO-APIC, depending on the configuration
of the 8 PIRQx Routing Control Registers PIRQ[A:H].

More information about can be find in Intel Quark X1000 datasheet[1]
section 21.11.

[1] - http://www.intel.com/content/www/us/en/embedded/products/quark/quark-x1000-datasheet.html
2015-12-21 08:06:14 -02:00
Jesus Sanchez-Palencia
8ae392e66f x86: Reduce .eh_frame section size
When generating binaries, gcc will always add information of what it
calls "the exception handler framework" into its own section: .eh_frame.
This section is based on the DWARF format's call frame information (CFI) [1]
and holds information that can be useful for debuggers but also for language
constructs that relies on always having stack unwinding information (i.e. exceptions).
Such constructs, however, are pretty much useless for the C language and are
mainly just used on C++. Furthermore, this section is one of the loadable sections
of a binary, meaning it will take extra space on flash.

When .eh_frame is not present, debuggers can still get the exact same information
they need for unwinding a stack frame and for restoring registers thanks to yet
another section: .debug_frame. This section is generated by '-g' gcc option and
friends. It is actually defined by DWARF and, as opposed to .eh_frame, is not a
loadable section. In other words, it is 'strippable' while .eh_frame is not.

Since all we need is the debug information we can get from .debug_frame, we can
disable the generation of these large and unused information tables by using gcc's
'-fno-asynchronous-unwind-tables'. The .eh_frame section stays around but the code
size issue is heavily tackled. This is the same approach taken on other projects
that target small code size generation [2] [3].

Pratically speaking, on a DEBUG build of the all-timers appplication, before this
patch we had:
   text    data     bss     dec     hex filename
  21319    1188   12952   35459    8a83 all-timers.galileo

And now, after this patch:
   text    data     bss     dec     hex filename
  16347    1188   12952   30487    7717 all-timers.galileo

This means a ~5Kb reduction on the loadable text segment (.text + .rodata + .eh_frame).

The flag is applied regardless of build type, DEBUG or RELEASE, since it benefits both.
Note that when release builds apply --gc-sections, they will remove .eh_frame section entirely.

[1] http://comments.gmane.org/gmane.comp.standards.dwarf/222
[2] 0d74ad383b
[3] http://git.musl-libc.org/cgit/musl/commit/?id=b439c051c7eee4eb4b93fc382f993aa6305ce530
[4] https://refspecs.linuxfoundation.org/LSB_3.0.0/LSB-Core-generic/LSB-Core-generic/ehframechpt.html

Signed-off-by: Jesus Sanchez-Palencia <jesus.sanchez-palencia@intel.com>
2015-12-21 08:06:14 -02:00
Michael LeMay
0dcd5e9b5a x86: Revise CFLAGS and LDFLAGS for LLVM Clang compatibility
This patch slightly revises CFLAGS and LDFLAGS to specify the
optimization and debugging options and linker script in a way that is
compatible with using Clang as the C compiler and to invoke the linker
(i.e. CC = clang and LD = clang).
2015-12-21 08:06:14 -02:00
Michael LeMay
128d9f3566 x86: Revise SET_INTERRUPT_HANDLER to avoid using inline assembly feature that does not work with LLVM Clang
The SET_INTERRUPT_HANDLER macro in interrupt.h used an inline assembly
feature to cause GCC to generate a unique number for a trampoline
label.  Clang compiled the code using that feature without generating
any compile-time errors, but it always generated the number 0,
resulting in all interrupt trampolines having the same label names.
This patch replaces the usage of that feature with local labels, which
are supported by both GCC and Clang.  See
https://sourceware.org/binutils/docs/as/Symbol-Names.html for an
explanation of local labels.
2015-12-21 08:06:14 -02:00
Michael LeMay
f9072c166b x86: Add missing clobber list in interrupt.h
The SET_INTERRUPT_HANDLER macro defines and registers an interrupt
handler.  It outputs a trampoline for the interrupt handler using a
block of inline assembly, and the address of that trampoline is what
is actually placed in the IDT.  That trampoline invokes the main body
of the interrupt handler.

This patch adds a missing clobber list to the inline assembly block.
It simply lists the caller-saved registers defined by the cdecl
calling convention: EAX, ECX, and EDX.  This is necessary, because the
inline assembly block invokes idt_set_intr_gate_desc using a call
instruction at the time the function containing the
SET_INTERRUPT_HANDLER instance is executed.  The
idt_set_intr_gate_desc function is free to clobber EAX, ECX, and EDX
according to cdecl.  A Clang-generated implementation of
idt_set_intr_gate_desc did in fact clobber those registers, resulting
in incorrect operation of the code following an instance of
SET_INTERRUPT_HANDLER.  The change in this patch informs the compiler
that those registers may be clobbered so that it can adjust the code
that it outputs around the inline assembly block accordingly.
2015-12-21 08:06:14 -02:00