This patch adds a simple non-driver protection domain sample to serve
as an example for defining other non-driver protection domains. It
simply performs a ping-pong test of protection domain switching
latency during boot, including optional accesses to a private metadata
region, and prints out the results.
This patch extends the protection domain framework with a third plugin
that is a hybrid of the previous two. The hardware task switching
mechanism has a strictly-defined format for TSS data structures that
causes more space to be consumed than would otherwise be required.
This patch defines a smaller data structure that is allocated for each
protection domain, only requiring 32 bytes instead of 128 bytes. It
uses the same multi-segment memory layout as the TSS-based plugin and
leaves paging disabled. However, it uses a similar mechanism as the
paging plugin to perform system call dispatches and returns.
For additional information, please refer to cpu/x86/mm/README.md.
This patch extends the protection domain framework with an additional
plugin to use Task-State Segment (TSS) structures to offload much of
the work of switching protection domains to the CPU. This can save
space compared to paging, since paging requires two 4KiB page tables
and one 32-byte page table plus one whole-system TSS and an additional
32-byte data structure for each protection domain, whereas the
approach implemented by this patch just requires a 128-byte data
structure for each protection domain. Only a small number of
protection domains will typically be used, so
n * 128 < 8328 + (n * 32).
For additional information, please refer to cpu/x86/mm/README.md.
GCC 6 is introducing named address spaces for the FS and GS segments
[1]. LLVM Clang also provides address spaces for the FS and GS
segments [2]. This patch also adds support to the multi-segment X86
memory management subsystem for using these features instead of inline
assembly blocks, which enables type checking to detect some address
space mismatches.
[1] https://gcc.gnu.org/onlinedocs/gcc/Named-Address-Spaces.html
[2] http://llvm.org/releases/3.3/tools/clang/docs/LanguageExtensions.html#target-specific-extensions
This patch implements a simple, lightweight form of protection domains
using a pluggable framework. Currently, the following plugin is
available:
- Flat memory model with paging.
The overall goal of a protection domain implementation within this
framework is to define a set of resources that should be accessible to
each protection domain and to prevent that protection domain from
accessing other resources. The details of each implementation of
protection domains may differ substantially, but they should all be
guided by the principle of least privilege. However, that idealized
principle is balanced against the practical objectives of limiting the
number of relatively time-consuming context switches and minimizing
changes to existing code.
For additional information, please refer to cpu/x86/mm/README.md.
This patch also causes the C compiler to be used as the default linker
and assembler.
The UEFI GenFw program inserts headers ahead of the code in the UEFI
binary. The linker script adjusts the starting address of the .text
section to account for that. This prevents the symbols from being
perturbed. This patch accounts for a recent change in the size of the
headers added by the GenFw program.
This patch configures Isolated Memory Regions (IMRs) to block DMA to
code and data regions that do not contain any data that needs to be
DMA-accessible.
The Intel Quark X1000 SoC includes support for Isolated Memory Regions
(IMRs), which are specified using range registers and associated
control registers that are accessible via the message bus. This patch
adds a driver for accessing those registers.
The Intel Quark X1000 SoC includes a message bus that is accessible
via PCI configuration registers. It communicates to various SoC
components such as the Isolated Memory Region (IMR) registers and the
Remote Management Unit. This patch adds a driver for accessing the
message bus.
This patch revises the I2C and GPIO initialization code to always be
run during platform boot rather than within each process that requires
it.
This patch also revises the gpio-output example to use a pin that is
set as an output by the default pinmux configuration. Previously, it
used a pin that was set as an output by the pinmux configuration that
is in effect when the OS does not change the pinmux configuration.
This patch permits interrupts to be generated by both the I2C and GPIO
controllers for simultaneously-executing applications. The controllers
share a single interrupt pin, INTC. Prior to this patch,
quarkX1000_gpio_init() routed INTA to PIRQC and IRQ 10 (due to an
incorrect assumption that INTA is connected to the GPIO controller),
and quarkX1000_i2c_init() routed INTC to PIRQC and IRQ 9. The I2C
controller initialization is a prerequisite for GPIO initialization,
so the final configuration was that INTA and INTC were both routed to
PIRQC and IRQ 10. Thus, only the GPIO ISR was being invoked, even if
the I2C controller was actually responsible for the interrupt.
This patch refactors the I2C and GPIO ISR setup and handler code so
that the shared portions are combined in
cpu/x86/drivers/legacy_pc/shared-isr.[ch]. The I2C and GPIO drivers
communicate their interrupt information to the shared component by
placing structures in a specific section of the binary.
When sending a command to the CC13xx/CC25xx RF core, we wait for command completion by checking the LSB of CMDSTA (correctly so). However, in doing so we also zero out the 3 CMDSTA return bytes. For some commands, those bytes contain useful information (e.g. an RSSI value) and are required by the caller.
This problem manifests itself e.g. in PROP mode `channel_clear()`, whereby the caller will always see an RSSI value of 0.
This pull therefore fixes the logic in `rf_core_send_cmd()` to check for command completion by blocking on the CMDSTA result byte without zeroing out the 3 return bytes.
Fixes#1465
Fix the following warning issued by GCC ARM Embedded 5-2015-q4-major:
../../cpu/cc2538/dev/udma.c: In function 'udma_init':
../../cpu/cc2538/dev/udma.c:59:10: warning: passing argument 1 of 'memset' discards 'volatile' qualifier from pointer target type [-Wdiscarded-array-qualifiers]
memset(&channel_config, 0, sizeof(channel_config));
^
In file included from <toolchain-path>/arm-none-eabi/include/string.h:10:0,
from ../../platform/cc2538dk/./contiki-conf.h:12,
from ../../cpu/cc2538/dev/udma.c:38:
<toolchain-path>/arm-none-eabi/include/string.h:25:7: note: expected 'void *' but argument is of type 'volatile struct channel_ctrl (*)[4]'
_PTR _EXFUN(memset,(_PTR, int, size_t));
^
Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau.dev@gmail.com>
The PKA drivers and examples were full of include paths missing the
appropriate prefix, or using angle brackets instead of double quotes or
the other way around.
Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau.dev@gmail.com>
Add generic AES functions that should be able to support all the modes
of operation of the hardware AES crypto engine, i.e. ECB, CBC, CTR,
CBC-MAC, GCM, and CCM.
This makes it possible to easily implement these modes of operation
without duplicating code.
Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau.dev@gmail.com>
This patch adds support for building the UEFI EDK2 tools on 32-bit
hosts. It also revises the script to support rebuilding the tools
when the script is re-invoked after the EDK2 repository has previously
been downloaded.
This patch refactors the MMIO routines in the GPIO and I2C drivers to
eliminate the base_addr parameter that specifies the MMIO base
address. Instead, just the MMIO routines themselves retrieve the base
address from the driver structure.
This patch adds support for optionally building EFI binaries in
addition to Multiboot ELF binaries. It includes a script,
build_uefi.sh, that downloads tool and library sources from the EDK II
project, builds the GenFw tool that is used to create UEFI binaries,
and creates a makefile that is included from the main x86 common
makefile and enables UEFI support in the Contiki build system. If the
script is not run prior to building Contiki, then an informational
message will be displayed with instructions for running build_uefi.sh
if UEFI support is desired. This patch also adds the path to the
auto-generated makefile to .gitignore.
This patch modifies the linker script for the Intel Quark X1000 to
account for the output file section offsets and alignment expectations
of the EDK II GenFw project.
This patch also adds a newlib patch to remove the weak symbol
attribute from floating point stdio support routines. See
<newlib>/newlib/README for an explanation of how the newlib developers
intended for _printf_float and _scanf_float to be linked. Newlib
declares them as weak symbols with the intention that developers would
force them to be linked only when needed using a linker command line
option. However, some but not all Contiki programs require them, so
we cannot simply always include or exclude them. Instead, we remove
the weak symbol attributes and rely on the linker to automatically
determine whether or not they should be linked. This avoids an issue
in which weak symbols were undefined in the intermediate DLL generated
as part of the UEFI build process. That resulted in the GenFw program
emitting "ERROR 3000" messages when it encountered relocations
referencing such an undefined symbol.
Finally, this patch updates README.md to both make some revisions to
account for the UART support introduced in previous patches as well as
to provide instructions for using the UEFI support.
This patch modifies the newlib and Contiki C and C++ compiler flags to
omit exception handling unwind tables (see
http://wiki.dwarfstd.org/index.php?title=Exception_Handling).
Removing these tables saves space in debug builds and has not caused
any readily-apparent functional changes.
Here is the size listing for an example program built without this
patch:
text data bss dec hex filename
76002 1508 21224 98734 181ae all-timers.galileo
Here is the size listing for the same program with this patch:
text data bss dec hex filename
72918 1508 21224 95650 175a2 all-timers.galileo
The primary motivation for this patch is to help enable UEFI support.
The .eh_frame and .eh_frame_hdr sections that are otherwise generated
are treated as code sections by the EDK2 GenFw program, since they are
read-only alloc sections. They get grouped with the actual code
sections, ahead of the data sections. This perturbs symbols and
complicates debugging.
This patch adds a simple, space-efficient driver for the Ethernet
interface built into the Intel Quark X1000. It only allocates a
single packet descriptor for each of the transmit and receive
directions, computes checksums on the CPU, and enables
store-and-forward mode for both transmit and receive directions.
This patch adds gpio-pcal9535a.c and gpio-pcal9535a.h files,
which support access to I2C-based PCAL9535A GPIO controller
configuration register through a function interface.
The PCAL9535A is a low-voltage 16-bit GPIO expander with interrupt
and reset for I2C-bus/SMBus applications. It contains the PCA9535
register set of four pairs of 8-bit Configuration, Input, Output,
and Polarity Inversion registers, and additionally, the PCAL9535A has
Agile I/O, which are additional features specifically designed to
enhance the I/O. More about PCAL9535A can be found in its datasheet[1].
This driver is needed in order to configure Galileo pinmux.
[1] - http://www.nxp.com/documents/data_sheet/PCAL9535A.pdf
This patch adds the i2c.c, i2c.h and i2c-registers.h files,
which support access to I2C controller configuration register
through a function interface.
This patch adds the gpio.c and gpio.h files, which support
access to GPIO Controller (non-legacy) configuration register
through a function interface.
It doesn't add interrupt support due to pinmux reasons. On
Galileo Gen 2 we need to configure a pin as input/interrupt
using pinmux and this can only be achieved through I2C. There's
one pin exported by default as GPIO output and we used this one
to test this driver.
In the future, we plan to add an I2C driver and a pinmux configuration
driver in order to solve this kind of problems.
This patch adds support for PCI BAR1 and also changes
the pci_init(), instead of having one function for each `bar`
we now set the `bar` to pci_config_addr_t parameter before calling
the pci_init() function..
This patch adds the 'meta' field to the generic driver structure to
point to optional driver-defined metadata. It also modifies the
associated initialization routine to populate it and updates the 16X50
UART driver to use the new initialization routine signature. This
patch also adds a function to perform PCI configuration register
writes, definitions for the PCI Command configuration register address
and some of the bits in that register, and a function to set
additional bits in that register. Finally, it adds macros to help
with performing MMIO to and from PCI devices.
This patch replaces the gcc option '-Og' by '-O0' which is used when
building debugging binaries. The motivation for this change comes
from the fact that we have found at least one optimization done by
'-Og' that interfered with one of our debugging sessions.
This patch adds -ffunction-sections and -fdata-sections to the
'release' CFLAGS so each function and data is place into its
own section in the output file. It also adds --gc-section to
the 'release' LDFLAGS so the linker removes the sections which
are not referenced.
This patch also adds -ffunction-sections and -fdata-sections
options to CFLAGS from build_newlib.sh. This increases newlib
static libraries size, however, the Contiki image shrinks even
more since --gc-section removes "dead code" from newlib.
As a practical effect, all unused function and data (as well as
sections such as .eh_frame) are striped out from the final elf
binary. This shrinks our release binary drastically.
Finally, to prevent --gc-section from removing .multiboot section,
this patch adds KEEP(*(.multiboot)) to quarkX1000.ld.
PCI Interrupt Routing is mapped using Interrupt Queue Agents
IRQAGENT[0:3] and aggregating the INT[A:D] interrupts for each
PCI-mapped device in the SoC.
PCI based interrupts PIRQ[A:H] are then available for consumption
by either the 8259 PICs or the IO-APIC, depending on the configuration
of the 8 PIRQx Routing Control Registers PIRQ[A:H].
More information about can be find in Intel Quark X1000 datasheet[1]
section 21.11.
[1] - http://www.intel.com/content/www/us/en/embedded/products/quark/quark-x1000-datasheet.html
When generating binaries, gcc will always add information of what it
calls "the exception handler framework" into its own section: .eh_frame.
This section is based on the DWARF format's call frame information (CFI) [1]
and holds information that can be useful for debuggers but also for language
constructs that relies on always having stack unwinding information (i.e. exceptions).
Such constructs, however, are pretty much useless for the C language and are
mainly just used on C++. Furthermore, this section is one of the loadable sections
of a binary, meaning it will take extra space on flash.
When .eh_frame is not present, debuggers can still get the exact same information
they need for unwinding a stack frame and for restoring registers thanks to yet
another section: .debug_frame. This section is generated by '-g' gcc option and
friends. It is actually defined by DWARF and, as opposed to .eh_frame, is not a
loadable section. In other words, it is 'strippable' while .eh_frame is not.
Since all we need is the debug information we can get from .debug_frame, we can
disable the generation of these large and unused information tables by using gcc's
'-fno-asynchronous-unwind-tables'. The .eh_frame section stays around but the code
size issue is heavily tackled. This is the same approach taken on other projects
that target small code size generation [2] [3].
Pratically speaking, on a DEBUG build of the all-timers appplication, before this
patch we had:
text data bss dec hex filename
21319 1188 12952 35459 8a83 all-timers.galileo
And now, after this patch:
text data bss dec hex filename
16347 1188 12952 30487 7717 all-timers.galileo
This means a ~5Kb reduction on the loadable text segment (.text + .rodata + .eh_frame).
The flag is applied regardless of build type, DEBUG or RELEASE, since it benefits both.
Note that when release builds apply --gc-sections, they will remove .eh_frame section entirely.
[1] http://comments.gmane.org/gmane.comp.standards.dwarf/222
[2] 0d74ad383b
[3] http://git.musl-libc.org/cgit/musl/commit/?id=b439c051c7eee4eb4b93fc382f993aa6305ce530
[4] https://refspecs.linuxfoundation.org/LSB_3.0.0/LSB-Core-generic/LSB-Core-generic/ehframechpt.html
Signed-off-by: Jesus Sanchez-Palencia <jesus.sanchez-palencia@intel.com>
This patch slightly revises CFLAGS and LDFLAGS to specify the
optimization and debugging options and linker script in a way that is
compatible with using Clang as the C compiler and to invoke the linker
(i.e. CC = clang and LD = clang).
The SET_INTERRUPT_HANDLER macro in interrupt.h used an inline assembly
feature to cause GCC to generate a unique number for a trampoline
label. Clang compiled the code using that feature without generating
any compile-time errors, but it always generated the number 0,
resulting in all interrupt trampolines having the same label names.
This patch replaces the usage of that feature with local labels, which
are supported by both GCC and Clang. See
https://sourceware.org/binutils/docs/as/Symbol-Names.html for an
explanation of local labels.
The SET_INTERRUPT_HANDLER macro defines and registers an interrupt
handler. It outputs a trampoline for the interrupt handler using a
block of inline assembly, and the address of that trampoline is what
is actually placed in the IDT. That trampoline invokes the main body
of the interrupt handler.
This patch adds a missing clobber list to the inline assembly block.
It simply lists the caller-saved registers defined by the cdecl
calling convention: EAX, ECX, and EDX. This is necessary, because the
inline assembly block invokes idt_set_intr_gate_desc using a call
instruction at the time the function containing the
SET_INTERRUPT_HANDLER instance is executed. The
idt_set_intr_gate_desc function is free to clobber EAX, ECX, and EDX
according to cdecl. A Clang-generated implementation of
idt_set_intr_gate_desc did in fact clobber those registers, resulting
in incorrect operation of the code following an instance of
SET_INTERRUPT_HANDLER. The change in this patch informs the compiler
that those registers may be clobbered so that it can adjust the code
that it outputs around the inline assembly block accordingly.
Child sections can be created depending on the CFLAGS used when building Contiki.
For instance, if built with -ffunction-sections or -fdata-sections would create
one section per function/variable and -Os sometimes split part of .text into one
child section.
This can also be an issue if we start linking with external libraries that are
built in such a way. Since we can't foresee how the port is going to be used,
we should make sure it is ready for the cases above.
This patch fixes this by correctly grouping child sections into their parent
sections.
Patch developed while investigating a bug with José Souza (jose.souza@intel.com).
