mirror of
https://github.com/oliverschmidt/contiki.git
synced 2024-12-26 04:32:02 +00:00
570 lines
15 KiB
C
570 lines
15 KiB
C
#include <mc1322x.h>
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#define reg(x) (*(volatile uint32_t *)(x))
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static uint8_t ram_values[4];
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void init_phy(void)
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{
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volatile uint32_t cnt;
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maca_reset = maca_reset_rst;
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for(cnt=0; cnt < 100; cnt++);
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maca_reset = maca_reset_cln_on;
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maca_control = control_seq_nop;
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#define DELAY 400000
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for(cnt=0; cnt < DELAY; cnt++);
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maca_tmren = maca_start_clk | maca_cpl_clk;
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maca_divider = gMACA_Clock_DIV_c;
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maca_warmup = 0x00180012;
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maca_eofdelay = 0x00000004;
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maca_ccadelay = 0x001a0022;
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maca_txccadelay = 0x00000025;
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maca_framesync = 0x000000A7;
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maca_clk = 0x00000008;
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// maca_maskirq = 0; //(maca_irq_cm | maca_irq_acpl | maca_irq_rst | maca_irq_di | maca_irq_crc | maca_irq_flt );
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maca_maskirq = (maca_irq_rst | maca_irq_acpl | maca_irq_cm | maca_irq_flt | maca_irq_crc);
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maca_slotoffset = 0x00350000;
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}
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void reset_maca(void)
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{
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uint32_t tmp;
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MACA_WRITE(maca_control, control_seq_nop);
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do
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{
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tmp = MACA_READ(maca_status);
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}
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while ((tmp & maca_status_cc_mask) == cc_not_completed);
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/* Clear all interrupts. */
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MACA_WRITE(maca_clrirq, 0xFFFF);
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}
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/*
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004030c4 <SMAC_InitFlybackSettings>:
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4030c4: 4806 ldr r0, [pc, #24] (4030e0 <SMAC_InitFlybackSettings+0x1c>) // r0 gets base 0x80009a00
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4030c6: 6881 ldr r1, [r0, #8] // r1 gets *(0x80009a08)
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4030c8: 4806 ldr r0, [pc, #24] (4030e4 <SMAC_InitFlybackSettings+0x20>) // r0 gets 0x0000f7df
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4030ca: 4308 orrs r0, r1 // or them, r0 has it
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4030cc: 4904 ldr r1, [pc, #16] (4030e0 <SMAC_InitFlybackSettings+0x1c>) // r1 gets base 0x80009a00
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4030ce: 6088 str r0, [r1, #8] // put r0 into 0x80009a08
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4030d0: 0008 lsls r0, r1, #0 // r0 gets r1, r0 is the base now
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4030d2: 4905 ldr r1, [pc, #20] (4030e8 <SMAC_InitFlybackSettings+0x24>) // r1 gets 0x00ffffff
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4030d4: 60c1 str r1, [r0, #12] // put 0x00ffffff into base+12
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4030d6: 0b09 lsrs r1, r1, #12 // r1 = 0x00ffffff >> 12
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4030d8: 6101 str r1, [r0, #16] // put r1 base+16
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4030da: 2110 movs r1, #16 // r1 gets 16
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4030dc: 6001 str r1, [r0, #0] // put r1 in the base
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4030de: 4770 bx lr // return
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4030e0: 80009a00 .word 0x80009a00
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4030e4: 0000f7df .word 0x0000f7df
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4030e8: 00ffffff .word 0x00ffffff
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*/
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/* tested and is good */
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#define RF_BASE 0x80009a00
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void flyback_init(void) {
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uint32_t val8, or;
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val8 = *(volatile uint32_t *)(RF_BASE+8);
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or = val8 | 0x0000f7df;
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*(volatile uint32_t *)(RF_BASE+8) = or;
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*(volatile uint32_t *)(RF_BASE+12) = 0x00ffffff;
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*(volatile uint32_t *)(RF_BASE+16) = (((uint32_t)0x00ffffff)>>12);
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*(volatile uint32_t *)(RF_BASE) = 16;
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/* good luck and godspeed */
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}
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#define MAX_SEQ1 2
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const uint32_t addr_seq1[MAX_SEQ1] = {
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0x80003048,
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0x8000304c,
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};
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const uint32_t data_seq1[MAX_SEQ1] = {
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0x00000f78,
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0x00607707,
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};
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#define MAX_SEQ2 2
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const uint32_t addr_seq2[MAX_SEQ2] = {
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0x8000a050,
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0x8000a054,
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};
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const uint32_t data_seq2[MAX_SEQ2] = {
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0x0000047b,
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0x0000007b,
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};
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#define MAX_CAL3_SEQ1 3
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const uint32_t addr_cal3_seq1[MAX_CAL3_SEQ1] = { 0x80009400,0x80009a04,0x80009a00, };
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const uint32_t data_cal3_seq1[MAX_CAL3_SEQ1] = {0x00020017,0x8185a0a4,0x8c900025, };
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#define MAX_CAL3_SEQ2 2
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const uint32_t addr_cal3_seq2[MAX_CAL3_SEQ2] = { 0x80009a00,0x80009a00,};
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const uint32_t data_cal3_seq2[MAX_CAL3_SEQ2] = { 0x8c900021,0x8c900027,};
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#define MAX_CAL3_SEQ3 1
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const uint32_t addr_cal3_seq3[MAX_CAL3_SEQ3] = { 0x80009a00 };
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const uint32_t data_cal3_seq3[MAX_CAL3_SEQ3] = { 0x8c900000 };
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#define MAX_CAL5 4
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const uint32_t addr_cal5[MAX_CAL5] = {
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0x80009400,
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0x8000a050,
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0x8000a054,
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0x80003048,
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};
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const uint32_t data_cal5[MAX_CAL5] = {
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0x00000017,
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0x00000000,
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0x00000000,
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0x00000f00,
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};
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#define MAX_DATA 43
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const uint32_t addr_reg_rep[MAX_DATA] = { 0x80004118,0x80009204,0x80009208,0x8000920c,0x80009210,0x80009300,0x80009304,0x80009308,0x8000930c,0x80009310,0x80009314,0x80009318,0x80009380,0x80009384,0x80009388,0x8000938c,0x80009390,0x80009394,0x8000a008,0x8000a018,0x8000a01c,0x80009424,0x80009434,0x80009438,0x8000943c,0x80009440,0x80009444,0x80009448,0x8000944c,0x80009450,0x80009460,0x80009464,0x8000947c,0x800094e0,0x800094e4,0x800094e8,0x800094ec,0x800094f0,0x800094f4,0x800094f8,0x80009470,0x8000981c,0x80009828 };
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const uint32_t data_reg_rep[MAX_DATA] = { 0x00180012,0x00000605,0x00000504,0x00001111,0x0fc40000,0x20046000,0x4005580c,0x40075801,0x4005d801,0x5a45d800,0x4a45d800,0x40044000,0x00106000,0x00083806,0x00093807,0x0009b804,0x000db800,0x00093802,0x00000015,0x00000002,0x0000000f,0x0000aaa0,0x01002020,0x016800fe,0x8e578248,0x000000dd,0x00000946,0x0000035a,0x00100010,0x00000515,0x00397feb,0x00180358,0x00000455,0x00000001,0x00020003,0x00040014,0x00240034,0x00440144,0x02440344,0x04440544,0x0ee7fc00,0x00000082,0x0000002a };
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/* has been tested and it good */
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void vreg_init(void) {
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volatile uint32_t i;
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*(volatile uint32_t *)(0x80003000) = 0x00000018; /* set default state */
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*(volatile uint32_t *)(0x80003048) = 0x00000f04; /* bypass the buck */
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for(i=0; i<0x161a8; i++) { continue; } /* wait for the bypass to take */
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// while((((*(volatile uint32_t *)(0x80003018))>>17) & 1) !=1) { continue; } /* wait for the bypass to take */
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*(volatile uint32_t *)(0x80003048) = 0x00000ff8; /* start the regulators */
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}
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void radio_off(void) {
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/* turn off the radio regulators */
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reg(0x80003048) = 0x00000f00;
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/* hold the maca in reset */
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maca_reset = maca_reset_rst;
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}
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void radio_on(void) {
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/* turn the radio regulators back on */
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reg(0x80003048) = 0x00000f78;
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/* reinitialize the phy */
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init_phy();
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}
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/* initialized with 0x4c */
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uint8_t ctov[16] = {
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0x0b,
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0x0b,
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0x0b,
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0x0a,
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0x0d,
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0x0d,
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0x0c,
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0x0c,
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0x0f,
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0x0e,
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0x0e,
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0x0e,
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0x11,
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0x10,
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0x10,
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0x0f,
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};
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/* get_ctov thanks to Umberto */
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#define _INIT_CTOV_WORD_1 0x00dfbe77
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#define _INIT_CTOV_WORD_2 0x023126e9
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uint8_t get_ctov( uint32_t r0, uint32_t r1 )
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{
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r0 = r0 * _INIT_CTOV_WORD_1;
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r0 += ( r1 << 22 );
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r0 += _INIT_CTOV_WORD_2;
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r0 = (uint32_t)(((int32_t)r0) >> 25);
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return (uint8_t)r0;
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}
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/* radio_init has been tested to be good */
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void radio_init(void) {
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volatile uint32_t i;
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/* sequence 1 */
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for(i=0; i<MAX_SEQ1; i++) {
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*(volatile uint32_t *)(addr_seq1[i]) = data_seq1[i];
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}
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/* seq 1 delay */
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for(i=0; i<0x161a8; i++) { continue; }
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/* sequence 2 */
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for(i=0; i<MAX_SEQ2; i++) {
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*(volatile uint32_t *)(addr_seq2[i]) = data_seq2[i];
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}
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/* modem val */
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*(volatile uint32_t *)0x80009000 = 0x80050100;
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/* cal 3 seq 1*/
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for(i=0; i<MAX_CAL3_SEQ1; i++) {
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*(volatile uint32_t *)(addr_cal3_seq1[i]) = data_cal3_seq1[i];
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}
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/* cal 3 delay */
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for(i=0; i<0x11194; i++) { continue; }
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/* cal 3 seq 2*/
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for(i=0; i<MAX_CAL3_SEQ2; i++) {
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*(volatile uint32_t *)(addr_cal3_seq2[i]) = data_cal3_seq2[i];
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}
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/* cal 3 delay */
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for(i=0; i<0x11194; i++) { continue; }
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/* cal 3 seq 3*/
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for(i=0; i<MAX_CAL3_SEQ3; i++) {
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*(volatile uint32_t *)(addr_cal3_seq3[i]) = data_cal3_seq3[i];
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}
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/* cal 5 */
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for(i=0; i<MAX_CAL5; i++) {
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*(volatile uint32_t *)(addr_cal5[i]) = data_cal5[i];
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}
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/*reg replacment */
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for(i=0; i<MAX_DATA; i++) {
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*(volatile uint32_t *)(addr_reg_rep[i]) = data_reg_rep[i];
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}
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puts("initfromflash\n\r");
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*(volatile uint32_t *)(0x80003048) = 0x00000f04; /* bypass the buck */
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for(i=0; i<0x161a8; i++) { continue; } /* wait for the bypass to take */
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// while((((*(volatile uint32_t *)(0x80003018))>>17) & 1) !=1) { continue; } /* wait for the bypass to take */
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*(volatile uint32_t *)(0x80003048) = 0x00000fa4; /* start the regulators */
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for(i=0; i<0x161a8; i++) { continue; } /* wait for the bypass to take */
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init_from_flash(0x1F000);
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puts("ram_values:\n\r");
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for(i=0; i<4; i++) {
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puts(" 0x");
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put_hex(ram_values[i]);
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puts("\n\r");
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}
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puts("radio_init: ctov parameter 0x");
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put_hex(ram_values[3]);
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puts("\n\r");
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for(i=0; i<16; i++) {
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ctov[i] = get_ctov(i,ram_values[3]);
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puts("radio_init: ctov[");
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put_hex(i);
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puts("] = 0x");
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put_hex(ctov[i]);
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puts("\n\r");
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}
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}
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const uint32_t PSMVAL[19] = {
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0x0000080f,
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0x0000080f,
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0x0000080f,
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0x0000080f,
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0x0000081f,
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0x0000081f,
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0x0000081f,
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0x0000080f,
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0x0000080f,
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0x0000080f,
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0x0000001f,
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0x0000000f,
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0x0000000f,
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0x00000816,
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0x0000001b,
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0x0000000b,
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0x00000802,
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0x00000817,
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0x00000003,
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};
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const uint32_t PAVAL[19] = {
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0x000022c0,
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0x000022c0,
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0x000022c0,
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0x00002280,
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0x00002303,
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0x000023c0,
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0x00002880,
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0x000029f0,
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0x000029f0,
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0x000029f0,
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0x000029c0,
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0x00002bf0,
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0x000029f0,
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0x000028a0,
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0x00002800,
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0x00002ac0,
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0x00002880,
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0x00002a00,
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0x00002b00,
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};
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const uint32_t AIMVAL[19] = {
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0x000123a0,
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0x000163a0,
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0x0001a3a0,
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0x0001e3a0,
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0x000223a0,
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0x000263a0,
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0x0002a3a0,
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0x0002e3a0,
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0x000323a0,
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0x000363a0,
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0x0003a3a0,
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0x0003a3a0,
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0x0003e3a0,
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0x000423a0,
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0x000523a0,
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0x000423a0,
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0x0004e3a0,
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0x0004e3a0,
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0x0004e3a0,
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};
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/* tested and seems to be good */
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#define ADDR_POW1 0x8000a014
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#define ADDR_POW2 ADDR_POW1 + 12
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#define ADDR_POW3 ADDR_POW1 + 64
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void set_power(uint8_t power) {
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reg(ADDR_POW1) = PSMVAL[power];
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reg(ADDR_POW2) = (ADDR_POW1>>18) | PAVAL[power];
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reg(ADDR_POW3) = AIMVAL[power];
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}
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const uint8_t VCODivI[16] = {
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0x2f,
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0x2f,
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0x2f,
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0x2f,
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0x2f,
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0x2f,
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0x2f,
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0x2f,
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0x30,
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0x30,
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0x30,
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0x2f,
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0x30,
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0x30,
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0x30,
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0x30,
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};
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const uint32_t VCODivF[16] = {
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0x00355555,
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0x006aaaaa,
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0x00a00000,
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0x00d55555,
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0x010aaaaa,
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0x01400000,
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0x01755555,
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0x01aaaaaa,
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0x01e00000,
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0x00155555,
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0x004aaaaa,
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0x00800000,
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0x00b55555,
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0x00eaaaaa,
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0x01200000,
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0x01555555,
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};
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/* tested good */
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#define ADDR_CHAN1 0x80009800
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#define ADDR_CHAN2 (ADDR_CHAN1+12)
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#define ADDR_CHAN3 (ADDR_CHAN1+16)
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#define ADDR_CHAN4 (ADDR_CHAN1+48)
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void set_channel(uint8_t chan) {
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volatile uint32_t tmp;
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tmp = reg(ADDR_CHAN1);
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tmp = tmp & 0xbfffffff;
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reg(ADDR_CHAN1) = tmp;
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reg(ADDR_CHAN2) = VCODivI[chan];
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reg(ADDR_CHAN3) = VCODivF[chan];
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tmp = reg(ADDR_CHAN4);
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tmp = tmp | 2;
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reg(ADDR_CHAN4) = tmp;
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tmp = reg(ADDR_CHAN4);
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tmp = tmp | 4;
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reg(ADDR_CHAN4) = tmp;
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tmp = tmp & 0xffffe0ff;
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tmp = tmp | (((ctov[chan])<<8)&0x1F00);
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reg(ADDR_CHAN4) = tmp;
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/* duh! */
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}
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#define ROM_END 0x0013ffff
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#define ENTRY_EOF 0x00000e0f
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/* processes up to 4 words of initialization entries */
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/* returns the number of words processed */
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uint32_t exec_init_entry(volatile uint32_t *entries, uint8_t *valbuf)
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{
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volatile uint32_t i;
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if(entries[0] <= ROM_END) {
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if (entries[0] == 0) {
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/* do delay command*/
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puts("init_entry: delay ");
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put_hex32(entries[1]);
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puts("\n\r");
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for(i=0; i<entries[1]; i++) { continue; }
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return 2;
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} else if (entries[0] == 1) {
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/* do bit set/clear command*/
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puts("init_entry: bit set clear ");
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put_hex32(entries[1]);
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putc(' ');
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put_hex32(entries[2]);
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putc(' ');
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put_hex32(entries[3]);
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puts("\n\r");
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reg(entries[2]) = (reg(entries[2]) & ~entries[1]) | (entries[3] & entries[1]);
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return 4;
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} else if ((entries[0] >= 16) &&
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(entries[0] < 0xfff1)) {
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/* store bytes in valbuf */
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puts("init_entry: store in valbuf ");
|
|
put_hex(entries[1]);
|
|
puts(" position ");
|
|
put_hex((entries[0]>>4)-1);
|
|
puts("\n\r");
|
|
valbuf[(entries[0]>>4)-1] = entries[1];
|
|
return 2;
|
|
} else if (entries[0] == ENTRY_EOF) {
|
|
puts("init_entry: eof ");
|
|
return 0;
|
|
} else {
|
|
/* invalid command code */
|
|
puts("init_entry: invaild code ");
|
|
put_hex32(entries[0]);
|
|
puts("\n\r");
|
|
return 0;
|
|
}
|
|
} else { /* address isn't in ROM space */
|
|
/* do store value in address command */
|
|
puts("init_entry: address value pair - *0x");
|
|
put_hex32(entries[0]);
|
|
puts(" = ");
|
|
put_hex32(entries[1]);
|
|
puts("\n\r");
|
|
reg(entries[0]) = entries[1];
|
|
return 2;
|
|
}
|
|
}
|
|
|
|
|
|
#define FLASH_INIT_MAGIC 0x00000abc
|
|
uint32_t init_from_flash(uint32_t addr) {
|
|
nvmType_t type=0;
|
|
nvmErr_t err;
|
|
volatile uint32_t buf[8];
|
|
volatile uint32_t len;
|
|
volatile uint32_t i=0,j;
|
|
|
|
err = nvm_detect(gNvmInternalInterface_c, &type);
|
|
puts("nvm_detect returned type ");
|
|
put_hex32(type);
|
|
puts(" err ");
|
|
put_hex(err);
|
|
puts("\n\r");
|
|
|
|
nvm_setsvar(0);
|
|
err = nvm_read(gNvmInternalInterface_c, type, (uint8_t *)buf, addr, 8);
|
|
i+=8;
|
|
puts("nvm_read returned: 0x");
|
|
put_hex(err);
|
|
puts("\n\r");
|
|
|
|
for(j=0; j<4; j++) {
|
|
put_hex32(buf[j]);
|
|
puts("\n\r");
|
|
}
|
|
|
|
if(buf[0] == FLASH_INIT_MAGIC) {
|
|
len = buf[1] & 0x0000ffff;
|
|
while(i < (len-4)) {
|
|
err = nvm_read(gNvmInternalInterface_c, type, (uint8_t *)buf, addr+i, 32);
|
|
i += 4*exec_init_entry(buf, ram_values);
|
|
}
|
|
return i;
|
|
} else {
|
|
return 0;
|
|
}
|
|
|
|
}
|
|
|
|
/*
|
|
* Do the ABORT-Wait-NOP-Wait sequence in order to prevent MACA malfunctioning.
|
|
* This seqeunce is synchronous and no interrupts should be triggered when it is done.
|
|
*/
|
|
void ResumeMACASync(void)
|
|
{
|
|
uint32_t clk, TsmRxSteps, LastWarmupStep, LastWarmupData, LastWarmdownStep, LastWarmdownData;
|
|
// bool_t tmpIsrStatus;
|
|
volatile uint32_t i;
|
|
|
|
// ITC_DisableInterrupt(gMacaInt_c);
|
|
// AppInterrupts_ProtectFromMACAIrq(tmpIsrStatus); <- Original from MAC code, but not sure how is it implemented
|
|
|
|
/* Manual TSM modem shutdown */
|
|
|
|
/* read TSM_RX_STEPS */
|
|
TsmRxSteps = (*((volatile uint32_t *)(0x80009204)));
|
|
|
|
/* isolate the RX_WU_STEPS */
|
|
/* shift left to align with 32-bit addressing */
|
|
LastWarmupStep = (TsmRxSteps & 0x1f) << 2;
|
|
/* Read "current" TSM step and save this value for later */
|
|
LastWarmupData = (*((volatile uint32_t *)(0x80009300 + LastWarmupStep)));
|
|
|
|
/* isolate the RX_WD_STEPS */
|
|
/* right-shift bits down to bit 0 position */
|
|
/* left-shift to align with 32-bit addressing */
|
|
LastWarmdownStep = ((TsmRxSteps & 0x1f00) >> 8) << 2;
|
|
/* write "last warmdown data" to current TSM step to shutdown rx */
|
|
LastWarmdownData = (*((volatile uint32_t *)(0x80009300 + LastWarmdownStep)));
|
|
(*((volatile uint32_t *)(0x80009300 + LastWarmupStep))) = LastWarmdownData;
|
|
|
|
/* Abort */
|
|
MACA_WRITE(maca_control, 1);
|
|
|
|
/* Wait ~8us */
|
|
for (clk = maca_clk, i = 0; maca_clk - clk < 3 && i < 300; i++)
|
|
;
|
|
|
|
/* NOP */
|
|
MACA_WRITE(maca_control, 0);
|
|
|
|
/* Wait ~8us */
|
|
for (clk = maca_clk, i = 0; maca_clk - clk < 3 && i < 300; i++)
|
|
;
|
|
|
|
|
|
/* restore original "last warmup step" data to TSM (VERY IMPORTANT!!!) */
|
|
(*((volatile uint32_t *)(0x80009300 + LastWarmupStep))) = LastWarmupData;
|
|
|
|
|
|
|
|
/* Clear all MACA interrupts - we should have gotten the ABORT IRQ */
|
|
MACA_WRITE(maca_clrirq, 0xFFFF);
|
|
|
|
// AppInterrupts_UnprotectFromMACAIrq(tmpIsrStatus); <- Original from MAC code, but not sure how is it implemented
|
|
// ITC_EnableInterrupt(gMacaInt_c);
|
|
}
|