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This patch extends the protection domain framework with an additional plugin to use Task-State Segment (TSS) structures to offload much of the work of switching protection domains to the CPU. This can save space compared to paging, since paging requires two 4KiB page tables and one 32-byte page table plus one whole-system TSS and an additional 32-byte data structure for each protection domain, whereas the approach implemented by this patch just requires a 128-byte data structure for each protection domain. Only a small number of protection domains will typically be used, so n * 128 < 8328 + (n * 32). For additional information, please refer to cpu/x86/mm/README.md. GCC 6 is introducing named address spaces for the FS and GS segments [1]. LLVM Clang also provides address spaces for the FS and GS segments [2]. This patch also adds support to the multi-segment X86 memory management subsystem for using these features instead of inline assembly blocks, which enables type checking to detect some address space mismatches. [1] https://gcc.gnu.org/onlinedocs/gcc/Named-Address-Spaces.html [2] http://llvm.org/releases/3.3/tools/clang/docs/LanguageExtensions.html#target-specific-extensions
281 lines
8.6 KiB
C
281 lines
8.6 KiB
C
/*
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* Copyright (C) 2015, Intel Corporation. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* 3. Neither the name of the copyright holder nor the names of its
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* contributors may be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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* COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
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* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
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* OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <assert.h>
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#include "pci.h"
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#include "helpers.h"
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#include "syscalls.h"
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/* I/O port for PCI configuration address */
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#define PCI_CONFIG_ADDR_PORT 0xCF8
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/* I/O port for PCI configuration data */
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#define PCI_CONFIG_DATA_PORT 0xCFC
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PROT_DOMAINS_ALLOC(dom_client_data_t, root_complex_drv);
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/*---------------------------------------------------------------------------*/
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/* Initialize PCI configuration register address in preparation for accessing
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* the specified register.
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*/
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static void
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set_addr(pci_config_addr_t addr)
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{
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addr.en_mapping = 1;
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outl(PCI_CONFIG_ADDR_PORT, addr.raw);
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}
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/*---------------------------------------------------------------------------*/
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/**
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* \brief Read from the specified PCI configuration register.
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* \param addr Address of PCI configuration register.
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* \return Value read from PCI configuration register.
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*/
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uint32_t
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pci_config_read(pci_config_addr_t addr)
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{
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set_addr(addr);
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return inl(PCI_CONFIG_DATA_PORT);
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}
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/*---------------------------------------------------------------------------*/
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/**
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* \brief Write to the PCI configuration data port.
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* \param addr Address of PCI configuration register.
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* \param data Value to write.
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*/
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void
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pci_config_write(pci_config_addr_t addr, uint32_t data)
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{
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set_addr(addr);
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outl(PCI_CONFIG_DATA_PORT, data);
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}
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/*---------------------------------------------------------------------------*/
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/**
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* \brief Enable PCI command bits of the specified PCI configuration
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* register.
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* \param addr Address of PCI configuration register.
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* \param flags Flags used to enable PCI command bits.
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*/
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void
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pci_command_enable(pci_config_addr_t addr, uint32_t flags)
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{
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uint32_t data;
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addr.reg_off = 0x04; /* PCI COMMAND_REGISTER */
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data = pci_config_read(addr);
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pci_config_write(addr, data | flags);
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}
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/*---------------------------------------------------------------------------*/
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/**
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* \brief Set current PIRQ to interrupt queue agent. PCI based interrupts
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* PIRQ[A:H] are then available for consumption by either the 8259
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* PICs or the IO-APIC depending on configuration of the 8 PIRQx
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* Routing Control Registers PIRQ[A:H]. See also pci_pirq_set_irq().
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* \param agent Interrupt Queue Agent to be used, IRQAGENT[0:3].
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* \param pin Interrupt Pin Route to be used, INT[A:D].
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* \param pirq PIRQ to be used, PIRQ[A:H].
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*/
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SYSCALLS_DEFINE_SINGLETON(pci_irq_agent_set_pirq,
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root_complex_drv,
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IRQAGENT agent, INTR_PIN pin, PIRQ pirq)
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{
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uint16_t value;
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uint32_t rcba_addr, offset = 0;
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rcba_addr = PROT_DOMAINS_MMIO(root_complex_drv);
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assert(agent >= IRQAGENT0 && agent <= IRQAGENT3);
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assert(pin >= INTA && pin <= INTD);
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assert(pirq >= PIRQA && pirq <= PIRQH);
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switch(agent) {
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case IRQAGENT0:
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if(pin != INTA) {
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halt();
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}
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offset = 0x3140;
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break;
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case IRQAGENT1:
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offset = 0x3142;
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break;
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case IRQAGENT2:
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if(pin != INTA) {
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halt();
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}
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offset = 0x3144;
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break;
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case IRQAGENT3:
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offset = 0x3146;
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}
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prot_domains_enable_mmio();
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MMIO_READW(value, *(uint16_t ATTR_MMIO_ADDR_SPACE *)(rcba_addr + offset));
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/* clear interrupt pin route and set corresponding pirq. */
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switch(pin) {
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case INTA:
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value &= ~0xF;
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value |= pirq;
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break;
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case INTB:
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value &= ~0xF0;
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value |= (pirq << 4);
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break;
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case INTC:
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value &= ~0xF00;
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value |= (pirq << 8);
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break;
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case INTD:
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value &= ~0xF000;
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value |= (pirq << 12);
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}
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MMIO_WRITEW(*(uint16_t ATTR_MMIO_ADDR_SPACE *)(rcba_addr + offset), value);
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prot_domains_disable_mmio();
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}
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/*---------------------------------------------------------------------------*/
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/**
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* \brief Set current IRQ to PIRQ. The interrupt router can be
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* programmed to allow PIRQ[A:H] to be routed internally
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* to the 8259 as ISA compatible interrupts. See also
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* pci_irq_agent_set_pirq().
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* \param pirq PIRQ to be used, PIRQ[A:H].
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* \param pin IRQ to be used, IRQ[0:15].
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* \param route_to_legacy Whether or not the interrupt should be routed to PIC 8259.
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*/
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void
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pci_pirq_set_irq(PIRQ pirq, uint8_t irq, uint8_t route_to_legacy)
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{
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pci_config_addr_t pci;
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uint32_t value;
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assert(pirq >= PIRQA && pirq <= PIRQH);
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assert(irq >= 0 && irq <= 0xF);
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assert(route_to_legacy == 0 || route_to_legacy == 1);
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pci.raw = 0;
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pci.bus = 0;
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pci.dev = 31;
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pci.func = 0;
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pci.reg_off = (pirq <= PIRQD) ? 0x60 : 0x64; /* PABCDRC and PEFGHRC Registers */
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value = pci_config_read(pci);
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switch(pirq) {
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case PIRQA:
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case PIRQE:
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value &= ~0x8F;
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value |= irq;
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value |= (!route_to_legacy << 7);
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break;
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case PIRQB:
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case PIRQF:
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value &= ~0x8F00;
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value |= (irq << 8);
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value |= (!route_to_legacy << 15);
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break;
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case PIRQC:
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case PIRQG:
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value &= ~0x8F0000;
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value |= (irq << 16);
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value |= (!route_to_legacy << 23);
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break;
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case PIRQD:
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case PIRQH:
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value &= ~0x8F000000;
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value |= (irq << 24);
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value |= (!route_to_legacy << 31);
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}
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set_addr(pci);
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outl(PCI_CONFIG_DATA_PORT, value);
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}
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/*---------------------------------------------------------------------------*/
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/**
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* \brief Initialize a structure for a PCI device driver that performs
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* MMIO to address range 0. Assumes that device has already
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* been configured with an MMIO address range 0, e.g. by
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* firmware.
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* \param c_this Structure that will be initialized to represent the driver.
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* \param pci_addr PCI base address of device.
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* \param mmio_sz Size of MMIO region.
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* \param meta Base address of optional driver-defined metadata.
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* \param meta_sz Size of optional driver-defined metadata.
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*/
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void
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pci_init(pci_driver_t ATTR_KERN_ADDR_SPACE *c_this,
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pci_config_addr_t pci_addr,
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size_t mmio_sz,
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uintptr_t meta,
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size_t meta_sz)
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{
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uintptr_t mmio;
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/* The BAR value is masked to clear non-address bits. */
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mmio = pci_config_read(pci_addr) & ~0xFFF;
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prot_domains_reg(c_this, mmio, mmio_sz, meta, meta_sz, false);
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}
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/*---------------------------------------------------------------------------*/
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/**
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* \brief Initialize the PCI root complex driver.
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*/
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void
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pci_root_complex_init(void)
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{
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uint32_t rcba_addr;
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pci_config_addr_t pci = { .raw = 0 };
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pci.dev = 31;
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pci.reg_off = 0xF0; /* Root Complex Base Address Register */
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/* masked to clear non-address bits. */
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rcba_addr = pci_config_read(pci) & ~0x3FFF;
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PROT_DOMAINS_INIT_ID(root_complex_drv);
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prot_domains_reg(&root_complex_drv, rcba_addr, 0x4000, 0, 0, false);
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SYSCALLS_INIT(pci_irq_agent_set_pirq);
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SYSCALLS_AUTHZ(pci_irq_agent_set_pirq, root_complex_drv);
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}
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/*---------------------------------------------------------------------------*/
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/**
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* \brief Prevent further invocations of pci_irq_agent_set_pirq.
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*/
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void
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pci_root_complex_lock(void)
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{
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SYSCALLS_DEAUTHZ(pci_irq_agent_set_pirq, root_complex_drv);
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}
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/*---------------------------------------------------------------------------*/
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