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This patch adds the 'meta' field to the generic driver structure to point to optional driver-defined metadata. It also modifies the associated initialization routine to populate it and updates the 16X50 UART driver to use the new initialization routine signature. This patch also adds a function to perform PCI configuration register writes, definitions for the PCI Command configuration register address and some of the bits in that register, and a function to set additional bits in that register. Finally, it adds macros to help with performing MMIO to and from PCI devices.
121 lines
4.0 KiB
C
121 lines
4.0 KiB
C
/*
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* Copyright (C) 2015, Intel Corporation. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* 3. Neither the name of the copyright holder nor the names of its
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* contributors may be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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* COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
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* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
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* OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef CPU_X86_DRIVERS_LEGACY_PC_PCI_H_
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#define CPU_X86_DRIVERS_LEGACY_PC_PCI_H_
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#include <stdint.h>
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#include "helpers.h"
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/** PCI configuration register identifier for Base Address Register 0 (BAR0) */
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#define PCI_CONFIG_REG_BAR0 0x10
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/** PCI Interrupt Routing is mapped using Interrupt Queue Agents */
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typedef enum {
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IRQAGENT0,
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IRQAGENT1,
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IRQAGENT2,
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IRQAGENT3
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} IRQAGENT;
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/** PCI Interupt Pins */
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typedef enum {
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INTA,
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INTB,
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INTC,
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INTD
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} INTR_PIN;
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/**
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* PCI based interrupts PIRQ[A:H] are then available for consumption by either
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* the 8259 PICs or the IO-APIC.
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*/
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typedef enum {
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PIRQA,
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PIRQB,
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PIRQC,
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PIRQD,
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PIRQE,
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PIRQF,
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PIRQG,
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PIRQH,
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} PIRQ;
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/** PCI command register bit to enable bus mastering */
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#define PCI_CMD_2_BUS_MST_EN BIT(2)
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/** PCI command register bit to enable memory space */
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#define PCI_CMD_1_MEM_SPACE_EN BIT(1)
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/**
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* PCI configuration address
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*
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* Refer to Intel Quark SoC X1000 Datasheet, Section 5.5 for more details on
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* PCI configuration register access.
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*/
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typedef union pci_config_addr {
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struct {
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/** Register/offset number. Least-significant two bits should be zero. */
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uint32_t reg_off : 8;
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uint32_t func : 3; /**< Function number */
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uint32_t dev : 5; /**< Device number */
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uint32_t bus : 8; /**< Bus number */
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uint32_t : 7;
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/** Must be set to perform PCI configuration access. */
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uint32_t en_mapping : 1;
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};
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uint32_t raw;
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} pci_config_addr_t;
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uint32_t pci_config_read(pci_config_addr_t addr);
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void pci_config_write(pci_config_addr_t addr, uint32_t data);
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void pci_command_enable(pci_config_addr_t addr, uint32_t flags);
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/**
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* PCI device driver instance with an optional single MMIO range and optional
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* metadata.
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*/
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typedef struct pci_driver {
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uintptr_t mmio; /**< MMIO range base address */
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uintptr_t meta; /**< Driver-defined metadata base address */
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} pci_driver_t;
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void pci_init_bar0(pci_driver_t *c_this,
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pci_config_addr_t pci_addr,
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uintptr_t meta);
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int pci_irq_agent_set_pirq(IRQAGENT agent, INTR_PIN pin, PIRQ pirq);
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void pci_pirq_set_irq(PIRQ pirq, uint8_t irq, uint8_t route_to_legacy);
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#define PCI_MMIO_READL(c_this, dest, reg_addr) \
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dest = *((volatile uint32_t *)((c_this).mmio + (reg_addr)))
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#define PCI_MMIO_WRITEL(c_this, reg_addr, src) \
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*((volatile uint32_t *)((c_this).mmio + (reg_addr))) = (src)
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#endif /* CPU_X86_DRIVERS_LEGACY_PC_PCI_H_ */
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