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37e73894f1
Some SoC data requires huge alignments. E.g., the µDMA channel control table has to be 1024-byte aligned. This table was simply aligned to 1024 bytes in the C code, which had the following consequences, wasting a lot of RAM: - As this table could be placed anywhere in .bss, there could be an alignment gap of up to 1023 bytes between the preceding data and this table. - The size of this table was also aligned to 1024 bytes, regardless of UDMA_CONF_MAX_CHANNEL, making this configuration option supposed to save RAM just useless. - .bss was also aligned to at least 1024 bytes, creating a huge alignment gap between .data and .bss. Instead of relying on the compiler to force this alignment, and on the linker to automatically place data, this change places carefully such SoC data in RAM using the linker script. A dedicated section is created to place such SoC data requiring huge alignments, and it is put at the beginning of the SRAM in order to ensure a maximal alignment without any gap. In this way, the alignment of .bss also remains normal, and the size of this table is not constrained by its alignment, but only by its contents (i.e. by UDMA_CONF_MAX_CHANNEL). In the case of the µDMA channel control table, the data is still zeroed by udma_init() (instead of also being zeroed as part of .bss). Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
260 lines
7.2 KiB
C
260 lines
7.2 KiB
C
/*
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* Copyright (c) 2013, Texas Instruments Incorporated - http://www.ti.com/
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* 3. Neither the name of the copyright holder nor the names of its
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* contributors may be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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* COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
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* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
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* OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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/**
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* \addtogroup cc2538-udma
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* @{
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*
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* \file
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* Implementation of the cc2538 micro-DMA driver
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*/
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#include "contiki-conf.h"
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#include "dev/udma.h"
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#include "dev/nvic.h"
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#include "reg.h"
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#include <stdint.h>
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#include <string.h>
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/*---------------------------------------------------------------------------*/
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struct channel_ctrl {
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uint32_t src_end_ptr;
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uint32_t dst_end_ptr;
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uint32_t ctrl_word;
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uint32_t unused;
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};
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static volatile struct channel_ctrl channel_config[UDMA_CONF_MAX_CHANNEL + 1]
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__attribute__ ((section(".udma_channel_control_table")));
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/*---------------------------------------------------------------------------*/
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void
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udma_init()
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{
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memset(&channel_config, 0, sizeof(channel_config));
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REG(UDMA_CFG) = UDMA_CFG_MASTEN;
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REG(UDMA_CTLBASE) = (uint32_t)(&channel_config);
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nvic_interrupt_enable(NVIC_INT_UDMA);
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nvic_interrupt_enable(NVIC_INT_UDMA_ERR);
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}
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/*---------------------------------------------------------------------------*/
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void
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udma_set_channel_src(uint8_t channel, uint32_t src_end)
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{
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if(channel > UDMA_CONF_MAX_CHANNEL) {
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return;
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}
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channel_config[channel].src_end_ptr = src_end;
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}
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/*---------------------------------------------------------------------------*/
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void
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udma_set_channel_dst(uint8_t channel, uint32_t dst_end)
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{
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if(channel > UDMA_CONF_MAX_CHANNEL) {
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return;
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}
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channel_config[channel].dst_end_ptr = dst_end;
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}
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/*---------------------------------------------------------------------------*/
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void
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udma_set_channel_control_word(uint8_t channel, uint32_t ctrl)
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{
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if(channel > UDMA_CONF_MAX_CHANNEL) {
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return;
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}
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channel_config[channel].ctrl_word = ctrl;
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}
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/*---------------------------------------------------------------------------*/
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void
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udma_set_channel_assignment(uint8_t channel, uint8_t enc)
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{
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uint32_t base_chmap = UDMA_CHMAP0;
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uint8_t shift;
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if(channel > UDMA_CONF_MAX_CHANNEL) {
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return;
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}
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/* Calculate the address of the relevant CHMAP register */
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base_chmap += (channel >> 3) * 4;
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/* Calculate the shift value for the correct CHMAP register bits */
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shift = (channel & 0x07);
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/* Read CHMAPx value, zero out channel's bits and write the new value */
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REG(base_chmap) = (REG(base_chmap) & ~(0x0F << shift)) | (enc << shift);
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}
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/*---------------------------------------------------------------------------*/
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void
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udma_channel_enable(uint8_t channel)
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{
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if(channel > UDMA_CONF_MAX_CHANNEL) {
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return;
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}
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REG(UDMA_ENASET) |= 1 << channel;
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}
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/*---------------------------------------------------------------------------*/
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void
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udma_channel_disable(uint8_t channel)
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{
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if(channel > UDMA_CONF_MAX_CHANNEL) {
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return;
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}
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/* Writes of 0 have no effect, this no need for RMW */
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REG(UDMA_ENACLR) = 1 << channel;
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}
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/*---------------------------------------------------------------------------*/
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void
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udma_channel_use_alternate(uint8_t channel)
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{
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if(channel > UDMA_CONF_MAX_CHANNEL) {
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return;
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}
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REG(UDMA_ALTSET) |= 1 << channel;
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}
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/*---------------------------------------------------------------------------*/
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void
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udma_channel_use_primary(uint8_t channel)
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{
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if(channel > UDMA_CONF_MAX_CHANNEL) {
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return;
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}
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/* Writes of 0 have no effect, this no need for RMW */
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REG(UDMA_ALTCLR) = 1 << channel;
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}
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/*---------------------------------------------------------------------------*/
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void
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udma_channel_prio_set_high(uint8_t channel)
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{
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if(channel > UDMA_CONF_MAX_CHANNEL) {
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return;
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}
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REG(UDMA_PRIOSET) |= 1 << channel;
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}
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/*---------------------------------------------------------------------------*/
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void
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udma_channel_prio_set_default(uint8_t channel)
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{
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if(channel > UDMA_CONF_MAX_CHANNEL) {
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return;
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}
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/* Writes of 0 have no effect, this no need for RMW */
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REG(UDMA_PRIOCLR) = 1 << channel;
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}
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/*---------------------------------------------------------------------------*/
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void
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udma_channel_use_burst(uint8_t channel)
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{
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if(channel > UDMA_CONF_MAX_CHANNEL) {
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return;
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}
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REG(UDMA_USEBURSTSET) |= 1 << channel;
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}
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/*---------------------------------------------------------------------------*/
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void
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udma_channel_use_single(uint8_t channel)
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{
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if(channel > UDMA_CONF_MAX_CHANNEL) {
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return;
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}
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/* Writes of 0 have no effect, this no need for RMW */
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REG(UDMA_USEBURSTCLR) = 1 << channel;
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}
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/*---------------------------------------------------------------------------*/
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void
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udma_channel_mask_set(uint8_t channel)
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{
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if(channel > UDMA_CONF_MAX_CHANNEL) {
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return;
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}
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REG(UDMA_REQMASKSET) |= 1 << channel;
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}
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/*---------------------------------------------------------------------------*/
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void
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udma_channel_mask_clr(uint8_t channel)
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{
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if(channel > UDMA_CONF_MAX_CHANNEL) {
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return;
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}
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/* Writes of 0 have no effect, this no need for RMW */
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REG(UDMA_REQMASKCLR) = 1 << channel;
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}
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/*---------------------------------------------------------------------------*/
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void
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udma_channel_sw_request(uint8_t channel)
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{
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if(channel > UDMA_CONF_MAX_CHANNEL) {
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return;
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}
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REG(UDMA_SWREQ) |= 1 << channel;
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}
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/*---------------------------------------------------------------------------*/
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uint8_t
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udma_channel_get_mode(uint8_t channel)
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{
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if(channel > UDMA_CONF_MAX_CHANNEL) {
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return 0;
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}
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return (channel_config[channel].ctrl_word & 0x07);
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}
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/*---------------------------------------------------------------------------*/
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void
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udma_isr()
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{
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/* Simply clear Channel interrupt status for now */
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REG(UDMA_CHIS) = UDMA_CHIS_CHIS;
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}
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/*---------------------------------------------------------------------------*/
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void
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udma_err_isr()
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{
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/* Stub Implementation, just clear the error flag */
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REG(UDMA_ERRCLR) = 1;
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}
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/*---------------------------------------------------------------------------*/
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/** @} */
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