2020-09-17 05:12:40 +00:00
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; This plays KRG files, stripped down ym5 files
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; this is a limited format: the envelope values are ignored
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; the fields with don't-care values are packed together
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; they are played at 25Hz
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; FRAME0 = AFINE (r0)
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; FRAME1 = BFINE (r2)
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; FRAME2 = CFINE (r4)
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; FRAME3 = NOISE PERIOD (r6)
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; FRAME4 = ENABLE (r7)
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; FRAME5 = ACOARSE/BCOARSE (r1/r3)
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; FRAME6 = CCOARSE/AAMP (r5/r8)
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; FRAME7 = BAMP/CAMP (r9/r10)
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;================================
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;================================
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; mockingboard interrupt handler
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;================================
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;================================
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; On Apple II/6502 the interrupt handler jumps to address in 0xfffe
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; This is in the ROM, which saves the registers
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; on older IIe it saved A to $45 (which could mess with DISK II)
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; newer IIe doesn't do that.
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; It then calculates if it is a BRK or not (which trashes A)
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; Then it sets up the stack like an interrupt and calls 0x3fe
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CHUNKSIZE = 15 ; hardcoded, based on krg file
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interrupt_handler:
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php
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pha ; save A ; 3
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txa
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pha
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tya
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pha
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2020-09-17 14:23:31 +00:00
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; inc $0404 ; debug (flashes char onscreen)
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2020-09-17 05:12:40 +00:00
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bit $C404 ; clear 6522 interrupt by reading T1C-L ; 4
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lda DONE_PLAYING ; 3
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beq mb_play_music ; if song done, don't play music ; 3/2nt
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jmp done_interrupt ; 3
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;============
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; 13
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mb_play_music:
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;======================================
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; Write frames to Mockingboard
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;======================================
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; actually plays frame loaded at end of
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; last interrupt, so 20ms behind?
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mb_write_frame:
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;==================================
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; loop through the 11 registers
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; reading the value, then write out
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;==================================
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ldx #0 ; set up reg count ; 2
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mb_write_loop_left:
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lda REGISTER_DUMP,X ; load register value ; 4
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cmp REGISTER_OLD,X ; compare with old values ; 4
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beq mb_no_write_left ; 3/2nt
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;=============
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; typ 11
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; address
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stx MOCK_6522_ORA1 ; put address on PA1 ; 4
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lda #MOCK_AY_LATCH_ADDR ; latch_address for PB1 ; 2
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sta MOCK_6522_ORB1 ; latch_address on PB1 ; 4
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lda #MOCK_AY_INACTIVE ; go inactive ; 2
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sta MOCK_6522_ORB1 ; 4
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; value
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lda REGISTER_DUMP,X ; load register value ; 4
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sta MOCK_6522_ORA1 ; put value on PA1 ; 4
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lda #MOCK_AY_WRITE ; ; 2
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sta MOCK_6522_ORB1 ; write on PB1 ; 4
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lda #MOCK_AY_INACTIVE ; go inactive ; 2
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sta MOCK_6522_ORB1 ; 4
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;===========
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; 36
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mb_no_write_left:
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inx ; point to next register ; 2
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cpx #11 ; if 11 we're done ; 2
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bmi mb_write_loop_left ; otherwise, loop ; 3/2nt
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;============
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; 7
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ldx #0 ; set up reg count ; 2
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mb_write_loop_right:
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lda REGISTER_DUMP,X ; load register value ; 4
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cmp REGISTER_OLD,X ; compare with old values ; 4
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beq mb_no_write_right ; 3/2nt
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;=============
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; typ 11
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; address
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stx MOCK_6522_ORA2 ; put address on PA2 ; 4
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lda #MOCK_AY_LATCH_ADDR ; latch_address for PB1 ; 2
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sta MOCK_6522_ORB2 ; latch_address on PB2 ; 4
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lda #MOCK_AY_INACTIVE ; go inactive ; 2
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sta MOCK_6522_ORB2 ; 4
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; value
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lda REGISTER_DUMP,X ; load register value ; 4
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sta MOCK_6522_ORA2 ; put value on PA2 ; 4
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lda #MOCK_AY_WRITE ; ; 2
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sta MOCK_6522_ORB2 ; write on PB2 ; 4
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lda #MOCK_AY_INACTIVE ; go inactive ; 2
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sta MOCK_6522_ORB2 ; 4
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;===========
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; 36
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mb_no_write_right:
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inx ; point to next register ; 2
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cpx #11 ; if 11 we're done ; 2
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bmi mb_write_loop_right ; otherwise, loop ; 3/2nt
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;============
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; 7
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;=====================================
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; Copy registers to old
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;=====================================
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; 11 coming in
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ldx #10 ; 2
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mb_reg_copy:
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lda REGISTER_DUMP,X ; load register value ; 4
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sta REGISTER_OLD,X ; compare with old values ; 4
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dex ; 2
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bpl mb_reg_copy ; 2nt/3
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;=============
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; 171
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;===================================
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; Load all 11 registers in advance
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;===================================
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; note, assuming not cross page boundary, not any slower
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; then loading from zero page?
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mb_load_values:
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ldy MB_CHUNK_OFFSET ; get chunk offset ; 3
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; afine
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2020-10-20 23:09:36 +00:00
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lda (MB_ADDR_L),y ; load register value ; 5
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2020-09-17 05:12:40 +00:00
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sta A_FINE_TONE ; 3
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clc ; point to next interleaved ; 2
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2020-10-20 23:09:36 +00:00
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lda MB_ADDR_H ; page by adding CHUNKSIZE ; 3
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2020-09-17 05:12:40 +00:00
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adc #CHUNKSIZE ; 3
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2020-10-20 23:09:36 +00:00
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sta MB_ADDR_H ; 3
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2020-09-17 05:12:40 +00:00
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; bfine
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2020-10-20 23:09:36 +00:00
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lda (MB_ADDR_L),y ; load register value ; 5
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2020-09-17 05:12:40 +00:00
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sta B_FINE_TONE ; 3
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clc ; point to next interleaved ; 2
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2020-10-20 23:09:36 +00:00
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lda MB_ADDR_H ; page by adding CHUNKSIZE ; 3
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2020-09-17 05:12:40 +00:00
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adc #CHUNKSIZE ; 3
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2020-10-20 23:09:36 +00:00
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sta MB_ADDR_H ; 3
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2020-09-17 05:12:40 +00:00
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; cfine
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2020-10-20 23:09:36 +00:00
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lda (MB_ADDR_L),y ; load register value ; 5
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2020-09-17 05:12:40 +00:00
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sta C_FINE_TONE ; 3
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clc ; point to next interleaved ; 2
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2020-10-20 23:09:36 +00:00
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lda MB_ADDR_H ; page by adding CHUNKSIZE ; 3
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2020-09-17 05:12:40 +00:00
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adc #CHUNKSIZE ; 3
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2020-10-20 23:09:36 +00:00
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sta MB_ADDR_H ; 3
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2020-09-17 05:12:40 +00:00
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; noise
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2020-10-20 23:09:36 +00:00
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lda (MB_ADDR_L),y ; load register value ; 5
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2020-09-17 05:12:40 +00:00
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sta NOISE ; 3
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clc ; point to next interleaved ; 2
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2020-10-20 23:09:36 +00:00
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lda MB_ADDR_H ; page by adding CHUNKSIZE ; 3
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2020-09-17 05:12:40 +00:00
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adc #CHUNKSIZE ; 3
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2020-10-20 23:09:36 +00:00
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sta MB_ADDR_H ; 3
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2020-09-17 05:12:40 +00:00
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; enable
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2020-10-20 23:09:36 +00:00
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lda (MB_ADDR_L),y ; load register value ; 5
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2020-09-17 05:12:40 +00:00
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sta ENABLE ; 3
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clc ; point to next interleaved ; 2
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2020-10-20 23:09:36 +00:00
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lda MB_ADDR_H ; page by adding CHUNKSIZE ; 3
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2020-09-17 05:12:40 +00:00
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adc #CHUNKSIZE ; 3
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2020-10-20 23:09:36 +00:00
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sta MB_ADDR_H ; 3
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2020-09-17 05:12:40 +00:00
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; acoarse/bcoarse
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2020-10-20 23:09:36 +00:00
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lda (MB_ADDR_L),y ; load register value ; 5
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2020-09-17 05:12:40 +00:00
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and #$f ; 2
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sta B_COARSE_TONE ; 3
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2020-10-20 23:09:36 +00:00
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lda (MB_ADDR_L),y ; load register value ; 5
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2020-09-17 05:12:40 +00:00
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lsr ; 2
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lsr ; 2
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lsr ; 2
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lsr ; 2
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sta A_COARSE_TONE ; 3
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clc ; point to next interleaved ; 2
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2020-10-20 23:09:36 +00:00
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lda MB_ADDR_H ; page by adding CHUNKSIZE ; 3
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2020-09-17 05:12:40 +00:00
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adc #CHUNKSIZE ; 3
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2020-10-20 23:09:36 +00:00
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sta MB_ADDR_H ; 3
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2020-09-17 05:12:40 +00:00
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; CCOARSE/AAMP
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2020-10-20 23:09:36 +00:00
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lda (MB_ADDR_L),y ; load register value ; 5
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2020-09-17 05:12:40 +00:00
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and #$f ; 2
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sta A_VOLUME ; 3
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2020-10-20 23:09:36 +00:00
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lda (MB_ADDR_L),y ; load register value ; 5
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2020-09-17 05:12:40 +00:00
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lsr ; 2
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lsr ; 2
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lsr ; 2
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lsr ; 2
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sta C_COARSE_TONE ; 3
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clc ; point to next interleaved ; 2
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2020-10-20 23:09:36 +00:00
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lda MB_ADDR_H ; page by adding CHUNKSIZE ; 3
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2020-09-17 05:12:40 +00:00
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adc #CHUNKSIZE ; 3
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2020-10-20 23:09:36 +00:00
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sta MB_ADDR_H ; 3
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2020-09-17 05:12:40 +00:00
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inx ; point to next register ; 2
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; BAMP/CAMP
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2020-10-20 23:09:36 +00:00
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lda (MB_ADDR_L),y ; load register value ; 5
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2020-09-17 05:12:40 +00:00
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and #$f ; 2
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sta C_VOLUME ; 3
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2020-10-20 23:09:36 +00:00
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lda (MB_ADDR_L),y ; load register value ; 5
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2020-09-17 05:12:40 +00:00
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lsr ; 2
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lsr ; 2
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lsr ; 2
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lsr ; 2
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sta B_VOLUME ; 3
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;=========================================
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; if NOISE is $ff then we are done
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lda NOISE ; 3
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cmp #$ff
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bne mb_not_done
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; bpl mb_not_done ; 3/2nt
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; lda #1
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sta DONE_PLAYING
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jsr clear_ay_both
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jmp done_interrupt ; 3
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;===========
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; typ 6
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mb_not_done:
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;==============================================
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; incremement offset. If 0 move to next chunk
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;==============================================
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increment_offset:
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inc MB_CHUNK_OFFSET ; increment offset ; 5
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bne increment_done ; if not zero, done ; 3/2nt
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inc WHICH_CHUNK
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lda WHICH_CHUNK
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cmp #CHUNKSIZE
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bne increment_done
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lda #0
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sta WHICH_CHUNK
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increment_done:
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lda #>music_start
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clc
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adc WHICH_CHUNK
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2020-10-20 23:09:36 +00:00
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sta MB_ADDR_H
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2020-09-17 05:12:40 +00:00
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;=================================
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; Finally done with this interrupt
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;=================================
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done_interrupt:
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exit_interrupt:
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pla
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tay
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pla
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tax
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pla
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lda $45
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plp
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rti ; return from interrupt ; 6
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;============
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; typical
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; ???? cycles
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REGISTER_OLD:
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.byte 0,0,0,0,0,0,0,0,0,0,0,0,0,0
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