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doc: update the notes
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\begin{document}
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\begin{document}
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Sort of similar to how the Raspberry Pi started out as a GPU with a small
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\begin{center}
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RAM processor tacked to the side, the Apple II design is very much
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\begin{large}
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a TV-typewriter style video display that just happens to have a 6502
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{\bf Notes on the Apple II Lores Memory Map}
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\end{large}
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{\bf Or: Why is the memory map so weird}
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\end{center}
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The SoC in a Raspberry Pi is actually a large GPU with a small
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helper ARM processor tacked onto the side.
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In a similar fashion, the Apple II is very much
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a TV-typewriter video terminal that happens to have a 6502
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processor attached to give the display something to do.
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processor attached to give the display something to do.
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The video display is key to many things, in fact the CPU clock
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Wozniak has said in an interview in retrospect he could have
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usually runs at 978ns, but every 65th cycle
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gotten a lineary video memory map at the expense of two more chips.
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it is extended to 1117ns to keep the video output in sync with the colorburst.
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Apparently at design time he had thought most people would use BASIC
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This is why the 6502 runs at the odd average speed of 1.020484MHz.
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on the machine, and since BASIC already supported things did not realize
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what a hassle the map would be to assembly coders.
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Note any time use text or plot/line need a lookup table.
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My sprite code cheats and only supports drawing at an even rows because
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it makes the code smaller, fater, and simpler
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Page 1 of The Apple II low-resolution graphics and text display share
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Page 1 of The Apple II low-resolution graphics and text display share
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the same 1k region of memory, from addresses {\tt \$400} to {\tt \$800}.
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the same 1k region of memory, from addresses {\tt \$400} to {\tt \$800}.
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In an easy-to-use setup you would have a linear memory map where
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In an easy-to-use setup you would have a linear memory map where
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location (0,0) would map to address {\tt \$400}, location (39,0) would map
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location (0,0) would map to address {\tt \$400}, location (39,0) would map
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to {\tt \$427}, and location (1,0) would be at {\tt \$428}.
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to {\tt \$427}, and location (1,0) would be at {\tt \$428}.
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This is not how it works though.
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That would make too much sense.
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First, each memory location holds an 8-bit value.
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First, each memory location holds an 8-bit value.
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In text mode this is just the ASCII value you want to print
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In text mode this is just the ASCII value you want to print,
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(confusingly with the high bit set for plain text, the low-bit clear
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although confusingly with the high bit set for plain text.
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does weird things like enable inverse (black-on-white) or flashing
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Leaving the high bit clear does weird things like enable inverse
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modes).
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(black-on-white) or flashing characters.
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So setting address {\tt \$400} to {\tt \$C1}
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Setting address {\tt \$400} to {\tt \$C1}
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would put an 'A' (ASCII {\tt \$41})
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would put an 'A' (ASCII {\tt \$41})
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in the upper left corner of the screen.
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in the upper left corner of the screen.
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In low-res graphics mode the nibbles are used, so the {\tt \$C1} would
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In low-res graphics mode the nibbles are used, so the {\tt \$C1} would
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be intepreted as putting two blocks, one above each other, in the upper
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be interpreted as putting two blocks, one above each other, in the upper
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left.
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left.
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The top one would be color 1 (red) and the bottom color 12 (light green).
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The top block would be color 1 (red) and the bottom color 12 (light green).
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The colors are NTSC artifact colors, caused by outputting the raw bit
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The colors are NTSC artifact colors, caused by outputting the raw bit
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pattern out to the screen with the color burst enabled.
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pattern out to the screen with the color burst enabled.
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You can try this out yourself from BASIC by running
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You can try this out yourself from BASIC by running
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{\tt TEXT:HOME:POKE 1024,193} to see the text result, and
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{\tt TEXT:HOME:POKE 1024,193} to see the text result, and
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{\tt GR:POKE 1024,193} to see the graphcis result.
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{\tt GR:POKE 1024,193} to see the graphics result.
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The next part that complicates things is the weird interleavings of
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The next part that complicates things is the weird interleavings of
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the addresses.
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the addresses.
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Note that Line 2 starts at {\tt \$480}, not {\tt \$428} as expected.
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Note that Line 2 starts at {\tt \$480}, not {\tt \$428} as you might expect.
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{\tt \$428} actually corresponds to line 16.
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{\tt \$428} actually corresponds to line 16.
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The reason for this craziness turns out to Steve Wozniak being especially
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The reason for this craziness turns out to Steve Wozniak being especially
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clever, and finding a way to get DRAM refresh essentially for free.
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clever, and finding a way to get DRAM refresh essentially for free.
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Early home computers often used static RAM (SRAM).
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Early home computers often used static RAM (SRAM).
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SRAM is easy to use, you just hook up the address and read/write lines,
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SRAM is easy to use, you just hook up the CPU address and read/write lines
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then just read and write to memory.
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to the memory chips and read and write bytes as needed.
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It was very fast too.
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So why use dynamic RAM (DRAM)?
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Well SRAM uses 6 transistors per bit.
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DRAM only uses 1 transistor (plus a capacitor to store the value).
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So you can in theory fit 6 times the RAM in the same space, leading
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to much cheaper costs and much better density.
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What are the downsides of DRAM?
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Typically it was slower.
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Also that capacitor leaks away your memory.
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Given enough time (on the order of seconds or so) and all of your RAM
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will leak down to zero.
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To combat that, you have to refresh your memory.
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This essentially involves reading each memory value out faster
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than it leaks away (due to the design of DRAM, reads are destructive,
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so a read operation always reads out, recharges, then writes back
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the value).
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The act of refresh can be slow.
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The Apple II uses dynamic RAM (DRAM) where each bit is stored in a capacitor
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On many systems there was separate hardware to do the refresh, and
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whose value will leak away to zero unless you refresh it periodically.
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it often took over the memory bus to do this and your CPU would have
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Why would you use memory that did that?
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to pause while it was happening.
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Well SRAM uses 6 transistors to store a bit, a DRAM only 1.
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This is true of the original IBM PC.
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So in theory you can fit 6 times the RAM in the same space, leading
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If you ever look at cycle-level optimization on this platform you will
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to much cheaper costs and much better density.
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notice the coders have to take into account pauses caused by
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Refreshing the DRAM involves regularly reading each memory value out faster
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than it leaks away.
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Due to the design of DRAM, reads are destructive,
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so a read operation always reads out, recharges, then writes back
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the value.
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Refreshing can be slow.
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On many systems there was separate hardware to conduct the refresh, and
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often this hardware would take over the memory bus and halt the CPU
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while it was happening.
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This is true of the original IBM PC;
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if you ever look at cycle-level optimization on the PC
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you will notice the coders have to take into account pauses caused by
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memory refresh (the refresh tended to be conservative so some coders
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memory refresh (the refresh tended to be conservative so some coders
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would live dangerously and make refresh happen less often to increase
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chose to live dangerously and make refresh happen less often to increase
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performance).
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performance).
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% Wozniak's article in Byte magazine, May 1977 (Volume 2, Number 5)
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% Wozniak's article in Byte magazine, May 1977 (Volume 2, Number 5)
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% Gayler: The Apple II Circuit discription
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% Gayler: The Apple II Circuit description
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% 15-bit video address, 6 horiz 9 vert, increments, repeating 60Hz
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% 15-bit video address, 6 horiz 9 vert, increments, repeating 60Hz
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% vert has 262 values, horiz has 65 (40 chars+25 horiz blank)
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% vert has 262 values, horiz has 65 (40 chars+25 horiz blank)
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% value is loaded from proper place, and latched, 7 bits written out?
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% value is loaded from proper place, and latched, 7 bits written out?
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@ -117,63 +111,65 @@ performance).
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% it is extended to 1117ns to keep the video output in sync
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% it is extended to 1117ns to keep the video output in sync
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% Which is why the average CPU freq of apple II is 1.020484MHz
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% Which is why the average CPU freq of apple II is 1.020484MHz
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% 192 dots vertical. 70 blanking
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% 192 dots vertical. 70 blanking
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% Undstanding the Apple II by Sather
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% Understanding the Apple II by Sather
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% interleaving, but also to not leave execessive holes in map
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% interleaving, but also to not leave excessive holes in map
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% In interview in Sather book Woz says could have had contiguous
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% In interview in Sather book Woz says could have had contiguous
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% memory with 2 more chips.
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% memory with 2 more chips.
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Could have had contiguous memory with two more chips?
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Steve Wozniak realized that he could avoid stopping the CPU for refresh.
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The 6502 clock has two phases.
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1MHz 6502 cpu clock two phases. During first phase processor is busy
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During first phase processor is busy
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with internal work and the memory bus is idle. So during this
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with internal work and the memory bus is idle.
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time the video circuitry reads the memory and updates the display.
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On the Apple II during the idle time it steps through the video memory
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and updates the display.
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4116, refresh every two milliseconds. 2ms=500Hz
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To refresh the 16k (4116) DRAM chips you need to read each 128-wide
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row at least once every 2ms.
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each column has 128 bytes
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By carefully selecting the way that the CPU address lines map to
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the RAS/CAS lines into the DRAM you can have the video scanning
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RA0-RA2 are the only ones that matter for correctness
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circuitry walk through each row of the DRAMs fast enough to
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conduct the refresh for free, at the expense of having weird
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RA0 = V0
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interleaved video memory mappings.
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RA1 = H2
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RA2 = H0
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654 3210
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0x400 00 000 1000 000 0000
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0x480 00 000 1001 000 0000
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0x500 00 000 1010 000 0000
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0x580 00 000 1011 000 0000
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0x600 00 000 1100 000 0000
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0x680 00 000 1101 000 0000
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0x700 00 000 1110 000 0000
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0x780 00 000 1111 000 0000
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0x428 00 000 1000 010 1000
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0x4a8 00 000 1001 010 1000
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0x528 00 000 1010 010 1000
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0x5a8 00 000 1011 010 1000
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0x628 00 000 1100 010 1000
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0x6a8 00 000 1101 010 1000
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0x728 00 000 1110 010 1000
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0x7a8 00 000 1111 010 1000
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0x450,0x4d0,0x550,0x5d0,0x650,0x6d0,0x750,0x7d0,
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127 values needed
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0000 0000 0000 0000 = $0000
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...
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0011 1111 1000 0000 = $3f80
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%
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% 654 3210
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%0x400 00 000 1000 000 0000
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%0x480 00 000 1001 000 0000
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%0x500 00 000 1010 000 0000
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%0x580 00 000 1011 000 0000
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%0x600 00 000 1100 000 0000
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%0x680 00 000 1101 000 0000
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%0x700 00 000 1110 000 0000
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%0x780 00 000 1111 000 0000
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%0x428 00 000 1000 010 1000
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%0x4a8 00 000 1001 010 1000
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%0x528 00 000 1010 010 1000
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%0x5a8 00 000 1011 010 1000
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%0x628 00 000 1100 010 1000
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%0x6a8 00 000 1101 010 1000
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%0x728 00 000 1110 010 1000
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%0x7a8 00 000 1111 010 1000
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%0x450,0x4d0,0x550,0x5d0,0x650,0x6d0,0x750,0x7d0,
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%
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%127 values needed
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%
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%0000 0000 0000 0000 = $0000
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%...
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%0011 1111 1000 0000 = $3f80
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Wozniak said in a later interview that in retrospect he could have
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gotten a linear video memory map at the expense of two more chips
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on the circuit board.
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Apparently when designing the Apple II he thought most people would use BASIC
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which hid the memory map, and did not realize the interleaving would
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be such a pain for assembly coders.
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So this is the reason for the ugly memory map.
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It is also why Apple II graphics code often uses lookup tables and
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read/shift/mask operations just to do a simple plot operation.
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It is also why my demo code cheats and the sprite code only works
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at even row offsets.
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And it may seem hard to believe, but the hi-res code drawing routines
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are even more complicated.
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\input{table.tex}
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\input{table.tex}
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