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botdemo: try to fix glitchy audio
somehow the fix didn't make it into pt3_lib
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@ -109,36 +109,51 @@ reset_ay_smc4:
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; register in X
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; value in MB_VALUE
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; note the datasheet says 10,000ns (10 cycle) max hold
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; time on the write signals. So interleaving write/left
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; write might violate that
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write_ay_both:
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; address
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; write left
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lda #MOCK_AY_LATCH_ADDR ; latch_address on PB1 ; 2
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ldy #MOCK_AY_INACTIVE ; go inactive ; 2
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write_ay_smc1:
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stx MOCK_6522_ORA1 ; put address on PA1 ; 4
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stx MOCK_6522_ORA2 ; put address on PA2 ; 4
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lda #MOCK_AY_LATCH_ADDR ; latch_address on PB1 ; 2
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write_ay_smc2:
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sta MOCK_6522_ORB1 ; latch_address on PB1 ; 4
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sta MOCK_6522_ORB2 ; latch_address on PB2 ; 4
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ldy #MOCK_AY_INACTIVE ; go inactive ; 2
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write_ay_smc3:
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sty MOCK_6522_ORB1 ; 4
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sty MOCK_6522_ORB1 ; go inactive ; 4
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; write right
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stx MOCK_6522_ORA2 ; put address on PA2 ; 4
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sta MOCK_6522_ORB2 ; latch_address on PB2 ; 4
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sty MOCK_6522_ORB2 ; 4
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;===========
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; 28
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; value
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lda MB_VALUE ; 3
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; write left
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write_ay_smc4:
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sta MOCK_6522_ORA1 ; put value on PA1 ; 4
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sta MOCK_6522_ORA2 ; put value on PA2 ; 4
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lda #MOCK_AY_WRITE ; ; 2
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write_ay_smc5:
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sta MOCK_6522_ORB1 ; write on PB1 ; 4
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sta MOCK_6522_ORB2 ; write on PB2 ; 4
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write_ay_smc6:
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sty MOCK_6522_ORB1 ; 4
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lda MB_VALUE ; 3
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; write right
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sta MOCK_6522_ORA2 ; put value on PA2 ; 4
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lda #MOCK_AY_WRITE ; ; 2
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sta MOCK_6522_ORB2 ; write on PB2 ; 4
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sty MOCK_6522_ORB2 ; 4
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;===========
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; 29
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rts ; 6
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;===========
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