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https://github.com/deater/dos33fsprogs.git
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fire: shave off a byte thanks to qkumba
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@ -34,7 +34,8 @@
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; 106 bytes -- assume bit 8 is as random as bit 0
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; 106 bytes -- assume bit 8 is as random as bit 0
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; 82 bytes -- use VTAB in firmware to setup addresses
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; 82 bytes -- use VTAB in firmware to setup addresses
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; (Antoine Vignau on comp.sys.apple2 reminded me of this)
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; (Antoine Vignau on comp.sys.apple2 reminded me of this)
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; 81 bytes -- qkumba points out that GR leaves BASL:BASH pointing at line 23
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; so we can use Y-indirect of BASL to draw the bottom white line
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; Zero Page
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; Zero Page
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SEEDL = $4E
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SEEDL = $4E
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@ -82,16 +83,19 @@ fire_demo:
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; Setup white line on bottom
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; Setup white line on bottom
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; note: calling HLINE in firmware would take at least 13 bytes
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; note: calling HLINE in firmware would take at least 13 bytes
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; open coded is 10
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; below code is 9
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; we depend on the call to MON_SETGR leaving BASL:BASH set for line 39
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; (thanks to qkumba)
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lda #$ff ; 2
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lda #$ff ; 2
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ldy #39 ; 2
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ldy #39 ; 2
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white_loop:
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white_loop:
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sta $7d0,Y ; hline 24 (46+47) ; 3
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sta (BASL),Y ; hline 23 (46+47) ; 2
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dey ; 1
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dey ; 1
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bpl white_loop ; 2
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bpl white_loop ; 2
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;============
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;============
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; 10
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; 9
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fire_loop:
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fire_loop:
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@ -32,6 +32,9 @@
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; 109 bytes -- replace BIT/OR in low calc with an ADC
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; 109 bytes -- replace BIT/OR in low calc with an ADC
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; 107 bytes -- replace self-modifying load/store absolute with Y-indirect
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; 107 bytes -- replace self-modifying load/store absolute with Y-indirect
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; 106 bytes -- assume bit 8 is as random as bit 0
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; 106 bytes -- assume bit 8 is as random as bit 0
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; 105 bytes -- qkumba points out that GR leaves BASL:BASH pointing at line 23
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; so we can use Y-indirect of BASL to draw the bottom white line
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; Zero Page
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; Zero Page
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SEEDL = $4E
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SEEDL = $4E
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@ -41,6 +44,7 @@ OUTL = $02
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OUTH = $03
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OUTH = $03
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INL = $04
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INL = $04
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INH = $05
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INH = $05
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BASL = $28
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; 100 = $64
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; 100 = $64
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@ -64,10 +68,12 @@ fire_demo:
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; Setup white line on bottom
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; Setup white line on bottom
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; GR leaves BASL pointing at hline 23
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lda #$ff ; 2
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lda #$ff ; 2
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ldy #39 ; 2
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ldy #39 ; 2
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white_loop:
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white_loop:
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sta $7d0,Y ; hline 24 (46+47) ; 3
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sta (BASL),Y ; hline 23 (46+47) ; 3
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dey ; 1
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dey ; 1
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bpl white_loop ; 2
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bpl white_loop ; 2
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;============
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;============
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