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chiptune: update timings

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This commit is contained in:
Vince Weaver 2018-03-11 00:46:16 -05:00
parent 5dcf33ec03
commit 4bb387fac5
2 changed files with 9 additions and 10 deletions
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16
chiptune_player/README.chiptune
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@ -463,21 +463,21 @@ lzma/diff: 7257 bytes
Timing:
=======
Interrupt Timing / AY write latency:
====================================
Originally roughly 1500 cycles from start of interrupt
to all registers being written.
to all AY registers being written.
1500
Moved clock to after, near the visualization stuff, more like
1378 = 13+ (105*13)
Moved to load frame data at end of IRQ instead of begin
Load frame data for next time at end of IRQ, instead of begin
1029 = 13+2+(78*13)
Moved to load frame data at end of IRQ instead of begin
Inlined the mockingboard write routine
873 = 13+2+(66*13)
Only write registers than change. Added 6 per loop
951 worst case
299 if only one reg changed = 13+2+(18*13)+50
Only write registers that change. Added 6 cycles per loop
951 worst case = 13+2+(10+5+50+7)*13
304 if only one reg changed = 13+2+(18*13)+55

3
chiptune_player/interrupt_handler.s
View File

@ -50,7 +50,7 @@ mb_write_frame:
mb_write_loop:
lda REGISTER_DUMP,X ; load register value ; 4
cmp REGISTER_OLD,X ; compare with old values ; 4
beq mb_no_write ; 2/3nt
beq mb_no_write ; 3/2nt
;=============
; typ 11
@ -66,7 +66,6 @@ mb_write_loop:
mb_not_13:
sta MB_VALUE ; 3
; inlined "write_ay_both" to save 12 cycles
; address