From 4bb387fac5c7f277605335852340376d82fd013c Mon Sep 17 00:00:00 2001 From: Vince Weaver Date: Sun, 11 Mar 2018 00:46:16 -0500 Subject: [PATCH] chiptune: update timings --- chiptune_player/README.chiptune | 16 ++++++++-------- chiptune_player/interrupt_handler.s | 3 +-- 2 files changed, 9 insertions(+), 10 deletions(-) diff --git a/chiptune_player/README.chiptune b/chiptune_player/README.chiptune index efb8536b..630661ce 100644 --- a/chiptune_player/README.chiptune +++ b/chiptune_player/README.chiptune @@ -463,21 +463,21 @@ lzma/diff: 7257 bytes -Timing: -======= +Interrupt Timing / AY write latency: +==================================== Originally roughly 1500 cycles from start of interrupt - to all registers being written. + to all AY registers being written. 1500 Moved clock to after, near the visualization stuff, more like 1378 = 13+ (105*13) - Moved to load frame data at end of IRQ instead of begin + Load frame data for next time at end of IRQ, instead of begin 1029 = 13+2+(78*13) - Moved to load frame data at end of IRQ instead of begin + Inlined the mockingboard write routine 873 = 13+2+(66*13) - Only write registers than change. Added 6 per loop - 951 worst case - 299 if only one reg changed = 13+2+(18*13)+50 + Only write registers that change. Added 6 cycles per loop + 951 worst case = 13+2+(10+5+50+7)*13 + 304 if only one reg changed = 13+2+(18*13)+55 diff --git a/chiptune_player/interrupt_handler.s b/chiptune_player/interrupt_handler.s index e0912514..2c21091d 100644 --- a/chiptune_player/interrupt_handler.s +++ b/chiptune_player/interrupt_handler.s @@ -50,7 +50,7 @@ mb_write_frame: mb_write_loop: lda REGISTER_DUMP,X ; load register value ; 4 cmp REGISTER_OLD,X ; compare with old values ; 4 - beq mb_no_write ; 2/3nt + beq mb_no_write ; 3/2nt ;============= ; typ 11 @@ -66,7 +66,6 @@ mb_write_loop: mb_not_13: sta MB_VALUE ; 3 - ; inlined "write_ay_both" to save 12 cycles ; address