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chiptune: update timings
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@ -463,21 +463,21 @@ lzma/diff: 7257 bytes
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Timing:
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Interrupt Timing / AY write latency:
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=======
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====================================
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Originally roughly 1500 cycles from start of interrupt
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Originally roughly 1500 cycles from start of interrupt
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to all registers being written.
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to all AY registers being written.
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1500
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1500
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Moved clock to after, near the visualization stuff, more like
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Moved clock to after, near the visualization stuff, more like
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1378 = 13+ (105*13)
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1378 = 13+ (105*13)
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Moved to load frame data at end of IRQ instead of begin
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Load frame data for next time at end of IRQ, instead of begin
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1029 = 13+2+(78*13)
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1029 = 13+2+(78*13)
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Moved to load frame data at end of IRQ instead of begin
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Inlined the mockingboard write routine
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873 = 13+2+(66*13)
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873 = 13+2+(66*13)
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Only write registers than change. Added 6 per loop
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Only write registers that change. Added 6 cycles per loop
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951 worst case
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951 worst case = 13+2+(10+5+50+7)*13
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299 if only one reg changed = 13+2+(18*13)+50
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304 if only one reg changed = 13+2+(18*13)+55
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@ -50,7 +50,7 @@ mb_write_frame:
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mb_write_loop:
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mb_write_loop:
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lda REGISTER_DUMP,X ; load register value ; 4
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lda REGISTER_DUMP,X ; load register value ; 4
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cmp REGISTER_OLD,X ; compare with old values ; 4
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cmp REGISTER_OLD,X ; compare with old values ; 4
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beq mb_no_write ; 2/3nt
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beq mb_no_write ; 3/2nt
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;=============
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;=============
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; typ 11
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; typ 11
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@ -66,7 +66,6 @@ mb_write_loop:
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mb_not_13:
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mb_not_13:
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sta MB_VALUE ; 3
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sta MB_VALUE ; 3
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; inlined "write_ay_both" to save 12 cycles
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; inlined "write_ay_both" to save 12 cycles
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; address
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; address
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