diff --git a/kfest2018/kfest18.dsk b/kfest2018/kfest18.dsk index 66cb6013..19733cec 100644 Binary files a/kfest2018/kfest18.dsk and b/kfest2018/kfest18.dsk differ diff --git a/kfest2018/muda.tfv b/kfest2018/muda.tfv new file mode 100644 index 00000000..a7d8598a Binary files /dev/null and b/kfest2018/muda.tfv differ diff --git a/kfest2018/raster.s b/kfest2018/raster.s index 4fc3de18..51d68b6a 100644 --- a/kfest2018/raster.s +++ b/kfest2018/raster.s @@ -5,6 +5,13 @@ FRAMEBUFFER = $00 ; $00 - $0F YPOS = $10 YPOS_SIN = $11 +FRAME = $60 +BLARGH = $69 +MB_VALUE = $91 +MB_ADDRL = $93 +MB_ADDRH = $94 +MBASE = $97 +MBOFFSET = $98 DRAW_PAGE = $EE CURRENT_OFFSET = $EF OFFSET_GOVERNOR = $F0 @@ -31,10 +38,22 @@ WAIT = $FCA8 ;; delay 1/2(26+27A+5A^2) us jsr TEXT jsr HOME + ;=================== + ; init vars + lda #0 sta DRAW_PAGE sta CURRENT_OFFSET sta OFFSET_GOVERNOR + sta MBOFFSET + lda #>music + sta MBASE + + ;========================== + ; setup mockingboard + + jsr mockingboard_init + ; Clear Page0 lda #$00 @@ -387,17 +406,21 @@ loop2: ; we have 4518-6 = 4512 to work with rasterbars: - ; delay 547 (4512, -3725 draw_rasterbars - ; - 147 clear - 93 set_rasterbar + ; delay 31 (4512, -3725 draw_rasterbars + ; - 147 clear - 93 set_rasterbar - 516 ; Try X=8 Y=35 cycles=1611 ; Try X=3 Y=26 cycles=547 + ; Try X=4 Y=2 cycles=53 R2 + ; Try X=4 Y=1 cycles=27 R4 + nop + nop - ldy #26 ; 2 + ldy #1 ; 2 loop3: - ldx #3 ; 2 + ldx #4 ; 2 loop4: dex ; 2 bne loop4 ; 2nt/3 @@ -617,11 +640,120 @@ raster_loop2: all_done: + + ;========================= + ; play mockingboard + ;========================= + ; 11+ 84*5 + 10*4 + 21 = 492 + ; + 24 for loop = 516 + + lda MBASE ; 3 + sta MB_ADDRH ; 3 + lda #0 ; 2 + sta MB_ADDRL ; 3 + ;============= + ; 11 + + ldx #0 ; 2 + ldy MBOFFSET ; 3 + lda (MB_ADDRL),Y ; 5 + sta MB_VALUE ; 3 + jsr write_ay_both ; 6+65 + ;=============== + ; 84 + + clc ; 2 + lda #4 ; 2 + adc MB_ADDRH ; 3 + sta MB_ADDRH ; 3 + ;============== + ; 10 + ldx #2 + ldy MBOFFSET + lda (MB_ADDRL),Y + sta MB_VALUE + jsr write_ay_both + + clc + lda #4 + adc MB_ADDRH + sta MB_ADDRH + + ldx #3 + ldy MBOFFSET + lda (MB_ADDRL),y + sta MB_VALUE + jsr write_ay_both + + clc + lda #4 + adc MB_ADDRH + sta MB_ADDRH + ldx #8 + ldy MBOFFSET + lda (MB_ADDRL),y + sta MB_VALUE + jsr write_ay_both + + clc + lda #4 + adc MB_ADDRH + sta MB_ADDRH + + ldx #9 + ldy MBOFFSET + lda (MB_ADDRL),y + sta MB_VALUE + jsr write_ay_both + + lda FRAME ; 3 + lda #1 ; 2 + clc ; 2 + adc MBOFFSET ; 3 + sta MBOFFSET ; 3 + + lda MBASE ; 3 + adc #0 ; 2 + sta MBASE ; 3 + ;============= + ; 21 + + ; 2=2 not loop + ; 2+7+3= 12 = last page + ; 2+7+15=24 = loop + + ; Loop mushc + + cmp #>music+3 ; 2 + bne waste_7 ; + ; 2 + lda MBOFFSET ; 3 + cmp #$90 ; 2 + bne waste_12 ; + ; 2 + lda #>music ; 2 ; loop to 0:90 + sta MBASE ; 3 + lda #$90 ; 2 + sta MBOFFSET ; 3 + jmp not_ready_to_loop ; 3 +waste_7: + lda #0 ; 2 + inc BLARGH ; 5 +waste_12: + ; 3 + lda #0 ; 2 + inc BLARGH ; 5 + inc BLARGH ; 5 + +not_ready_to_loop: + rts ; 6 + + .align $100 words: ; H E L L O @@ -790,4 +922,156 @@ sine_table: .byte 8 ; 7.790432 30 .byte 10 ; 9.853951 31 +.align $100 +music: +.incbin "muda.tfv" +; ZP addresses + +; left channel +MOCK_6522_1_ORB = $C400 ; 6522 #1 port b data +MOCK_6522_1_ORA = $C401 ; 6522 #1 port a data +MOCK_6522_1_DDRB = $C402 ; 6522 #1 data direction port B +MOCK_6522_1_DDRA = $C403 ; 6522 #1 data direction port A +MOCK_6522_1_T1C_L = $C404 ; 6522 #1 Low-order counter +MOCK_6522_1_T1C_H = $C405 ; 6522 #1 High-order counter +MOCK_6522_1_T1L_L = $C406 ; 6522 #1 Low-order latch +MOCK_6522_1_T1L_H = $C407 ; 6522 #1 High-order latch +MOCK_6522_1_T2C_L = $C408 ; 6522 #1 Timer2 Low-order Latch/Counter +MOCK_6522_1_T2C_H = $C409 ; 6522 #1 Timer2 High-order Latch/Counter +MOCK_6522_1_SR = $C40A ; 6522 #1 Shift Register +MOCK_6522_1_ACR = $C40B ; 6522 #1 Auxiliary Control Register +MOCK_6522_1_PCR = $C40C ; 6522 #1 Peripheral Control Register +MOCK_6522_1_IFR = $C40D ; 6522 #1 Interrupt Flag Register +MOCK_6522_1_IER = $C40E ; 6522 #1 Interrupt Enable Register +MOCK_6522_1_ORAN = $C40F ; 6522 #1 port a data, no handshake + +; right channel +MOCK_6522_2_ORB = $C480 ; 6522 #2 port b data +MOCK_6522_2_ORA = $C481 ; 6522 #2 port a data +MOCK_6522_2_DDRB = $C482 ; 6522 #2 data direction port B +MOCK_6522_2_DDRA = $C483 ; 6522 #2 data direction port A +MOCK_6522_2_T1C_L = $C484 ; 6522 #2 Low-order counter +MOCK_6522_2_T1C_H = $C485 ; 6522 #2 High-order counter +MOCK_6522_2_T1L_L = $C486 ; 6522 #2 Low-order latch +MOCK_6522_2_T1L_H = $C487 ; 6522 #2 High-order latch +MOCK_6522_2_T2C_L = $C488 ; 6522 #2 Timer2 Low-order Latch/Counter +MOCK_6522_2_T2C_H = $C489 ; 6522 #2 Timer2 High-order Latch/Counter +MOCK_6522_2_SR = $C48A ; 6522 #2 Shift Register +MOCK_6522_2_ACR = $C48B ; 6522 #2 Auxiliary Control Register +MOCK_6522_2_PCR = $C48C ; 6522 #2 Peripheral Control Register +MOCK_6522_2_IFR = $C48D ; 6522 #2 Interrupt Flag Register +MOCK_6522_2_IER = $C48E ; 6522 #2 Interrupt Enable Register +MOCK_6522_2_ORAN = $C48F ; 6522 #2 port a data, no handshake + + +; AY-3-8910 commands on port B +; RESET BDIR BC1 +MOCK_AY_RESET = $0 ; 0 0 0 +MOCK_AY_INACTIVE = $4 ; 1 0 0 +MOCK_AY_READ = $5 ; 1 0 1 +MOCK_AY_WRITE = $6 ; 1 1 0 +MOCK_AY_LATCH_ADDR = $7 ; 1 1 1 + + + ;======================== + ; Mockingboard Init + ;======================== + ; Initialize the 6522s + ; set the data direction for all pins of PortA/PortB to be output + +mockingboard_init: + lda #$ff ; all 8 pins output (1), portA + + sta MOCK_6522_1_DDRA + sta MOCK_6522_2_DDRA + ; only 3 pins output (1), port B + lda #$7 + sta MOCK_6522_1_DDRB + + sta MOCK_6522_2_DDRB + + +reset_ay_both: + ;====================== + ; Reset Left AY-3-8910 + ;====================== +reset_ay_left: + lda #MOCK_AY_RESET + sta MOCK_6522_1_ORB + lda #MOCK_AY_INACTIVE + sta MOCK_6522_1_ORB + + ; AY-3-8913: Wait 5 us + nop + nop + nop + nop + nop + + ;====================== + ; Reset Right AY-3-8910 + ;====================== +reset_ay_right: + lda #MOCK_AY_RESET + sta MOCK_6522_2_ORB + lda #MOCK_AY_INACTIVE + sta MOCK_6522_2_ORB + + ; AY-3-8913: Wait 5 us + nop + nop + nop + nop + nop + + ;========================= + ; Setup initial conditions + ;========================= + + + ; 7: ENABLE + ldx #7 + lda #$38 ; noise disabled, ABC enabled + sta MB_VALUE + jsr write_ay_both + + rts + + + + ;========================================= + ; Write Right/Left to save value AY-3-8910 + ;========================================= + ; register in X + ; value in MB_VALUE + +write_ay_both: + ; address + stx MOCK_6522_1_ORA ; put address on PA1 ; 4 + stx MOCK_6522_2_ORA ; put address on PA2 ; 4 + lda #MOCK_AY_LATCH_ADDR ; latch_address on PB1 ; 2 + sta MOCK_6522_1_ORB ; latch_address on PB1 ; 4 + sta MOCK_6522_2_ORB ; latch_address on PB2 ; 4 + lda #MOCK_AY_INACTIVE ; go inactive ; 2 + sta MOCK_6522_1_ORB ; 4 + sta MOCK_6522_2_ORB ; 4 + ;=========== + ; 28 + ; value + lda MB_VALUE ; 3 + sta MOCK_6522_1_ORA ; put value on PA1 ; 4 + sta MOCK_6522_2_ORA ; put value on PA2 ; 4 + lda #MOCK_AY_WRITE ; ; 2 + sta MOCK_6522_1_ORB ; write on PB1 ; 4 + sta MOCK_6522_2_ORB ; write on PB2 ; 4 + lda #MOCK_AY_INACTIVE ; go inactive ; 2 + sta MOCK_6522_1_ORB ; 4 + sta MOCK_6522_2_ORB ; 4 + ;=========== + ; 31 + + rts ; 6 + ;=========== + ; 65 +