14 Commits

Author	SHA1	Message	Date
Vince Weaver	a8970f761b	tfv: have RLE image loading working ... forgot how much I hate 6502 assembler	2017-05-06 19:29:19 -04:00
Vince Weaver	2bedb2b369	gr-sim: vlin support is working	2017-05-04 15:16:42 -04:00
Vince Weaver	2b3f766c70	gr-sim: use actual code for gr	2017-05-04 14:59:25 -04:00
Vince Weaver	d87eac3693	gr-sim: add text test	2017-05-04 14:34:57 -04:00
Vince Weaver	0aa9a3727a	tfv: add inline rle image	2017-05-04 14:32:41 -04:00
Vince Weaver	b7e225212c	gr-sim: add home() support	2017-05-04 14:32:23 -04:00
Vince Weaver	8024a2bad4	gr-sim: fix zero page addresses ... somehow read the monitor listing wrong	2017-05-04 09:14:44 -04:00
Vince Weaver	2587d829bf	gr-sim: actually model the RAM layout properly	2017-05-03 12:20:53 -04:00
Vince Weaver	3fd760912e	gr-sim: add tfv	2017-05-03 10:53:27 -04:00
Vince Weaver	737c56cfd0	gr-sim: add bload support	2017-05-03 10:50:15 -04:00
Vince Weaver	ab1c70b37c	tfv: more commenting of the duet "source"	2017-05-02 17:11:27 -04:00
Vince Weaver	453ca6bdb2	gr-sim: add another demo	2017-05-02 15:21:32 -04:00
Vince Weaver	f75da270f7	gr-sim: make it a library	2017-05-02 10:56:59 -04:00
Vince Weaver	10e10a2576	gr-sim: add SDL GR simulator	2017-05-02 09:59:39 -04:00