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Fixed hardware detection.

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The previous chip detection was inspired by the old IP65 driver code. For some reason it didn't work as expected. The new code is simpler and based on this statement in the chip datasheet: "The upper byte always reads as 33h and can be used to help determine the I/O location of the LAN91C96."
This commit is contained in:
Oliver Schmidt 2014-07-12 11:27:01 +02:00
parent a0bd7e819a
commit 6178e51148
1 changed files with 18 additions and 19 deletions
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35
drivers/lan91c96.s
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@ -168,16 +168,24 @@ init:
inc ptr+1 inc ptr+1
bcs :- ; Always bcs :- ; Always
; Check bank select register upper byte to always read as $33
: ldy #$00
fixup01:sty ethbsr+1
fixup02:lda ethbsr+1
cmp #$33
beq :+
sec
rts
; Reset ETH card ; Reset ETH card
: lda #$00 ; Bank 0 : ; Bank 0
fixup01:sta ethbsr fixup03:sty ethbsr
lda #%10000000 ; Software reset lda #%10000000 ; Software reset
fixup02:sta ethrcr+1 fixup04:sta ethrcr+1
ldy #$00 fixup05:sty ethrcr
fixup03:sty ethrcr fixup06:sty ethrcr+1
fixup04:sty ethrcr+1
; Delay ; Delay
: cmp ($FF,x) ; 6 cycles : cmp ($FF,x) ; 6 cycles
@ -189,21 +197,12 @@ fixup04:sty ethrcr+1
; Enable transmit and receive ; Enable transmit and receive
lda #%10000001 ; Enable transmit TXENA, PAD_EN lda #%10000001 ; Enable transmit TXENA, PAD_EN
ldx #%00000011 ; Enable receive, strip CRC ??? ldx #%00000011 ; Enable receive, strip CRC ???
fixup05:sta ethtcr fixup07:sta ethtcr
fixup06:stx ethrcr+1 fixup08:stx ethrcr+1
lda #$01 ; Bank 1 lda #$01 ; Bank 1
fixup07:sta ethbsr fixup09:sta ethbsr
; Check ISA mode base address register for reset values
lda #$18^67 ; I/O base $300 + ROM $CC000
fixup08:eor ethbar
fixup09:eor ethbar+1
beq :+
sec
rts
:
fixup10:lda ethcr+1 fixup10:lda ethcr+1
ora #%00010000 ; No wait (IOCHRDY) ora #%00010000 ; No wait (IOCHRDY)
fixup11:sta ethcr+1 fixup11:sta ethcr+1