Now that we have per-target Ethernet drivers we can omit initialization code necessary only for a certain card/cart from all the other drivers for the same Ethernet chip. This is especially true for the code self-modification only necessary on the Apple II to accommodate to the multiple slots.
Note: The whole chip base address handling will be overhauled in subsequent changes.
This commit is contained in:
Oliver Schmidt
parent
43d7d33c31
commit
6f0e4a97b1
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@ -1,4 +1,4 @@
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__CBM__ = 1
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__C64__ = 1
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.include "ethernetcombo.s"
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@ -74,8 +74,45 @@ cnt := ptr4 ; Frame length counter
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.endif
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;=====================================================================
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.ifdef __CBM__
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.ifdef __C64__
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rxtxreg := $DE08
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txcmd := $DE0C
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txlen := $DE0E
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isq := $DE00
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packetpp := $DE02
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ppdata := $DE04
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.endif
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.ifdef __VIC20__
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rxtxreg := $9808
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txcmd := $980C
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txlen := $980E
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isq := $9800
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packetpp := $9802
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ppdata := $9804
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.endif
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;---------------------------------------------------------------------
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.code
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init:
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; Activate C64 RR clockport in order to operate RR-Net
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; (RR config register overlays unused CS8900A ISQ register)
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lda isq+1
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ora #$01 ; Set clockport bit
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sta isq+1
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.endif
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;=====================================================================
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.ifdef __APPLE2__
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.rodata
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fixup: .byte fixup02-fixup01, fixup03-fixup02, fixup04-fixup03
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@ -85,8 +122,7 @@ fixup: .byte fixup02-fixup01, fixup03-fixup02, fixup04-fixup03
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.byte fixup14-fixup13, fixup15-fixup14, fixup16-fixup15
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.byte fixup17-fixup16, fixup18-fixup17, fixup19-fixup18
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.byte fixup20-fixup19, fixup21-fixup20, fixup22-fixup21
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.byte fixup23-fixup22, fixup24-fixup23, fixup25-fixup24
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.byte fixup26-fixup25
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.byte fixup23-fixup22, fixup24-fixup23
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fixups = * - fixup
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@ -100,10 +136,10 @@ isq := $FFF8
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packetpp := $FFFA
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ppdata := $FFFC
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.data
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;---------------------------------------------------------------------
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.data
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init:
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; Save address of rxtxreg
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sta reg
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@ -120,7 +156,7 @@ init:
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; Fixup address at location
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: lda (ptr),y
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and #$0F
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eor reg ; Use XOR to support C64 RR-Net
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ora reg
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sta (ptr),y
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iny
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lda reg+1
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@ -138,14 +174,30 @@ init:
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bcc :-
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inc ptr+1
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bcs :- ; Always
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; Activate C64 RR clockport in order to operate RR-Net
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; - RR config register overlays CS8900A ISQ register
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; - No need to distinguish as ISQ access doesn't hurt
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:
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fixup01:lda isq+1
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ora #$01 ; Set clockport bit
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fixup02:sta isq+1
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.endif
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;=====================================================================
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.ifdef __ATARI__
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rxtxreg := $D500
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txcmd := $D504
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txlen := $D506
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isq := $D508
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packetpp := $D50A
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ppdata := $D50C
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;---------------------------------------------------------------------
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.code
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init:
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.endif
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;=====================================================================
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; Check EISA registration number of Crystal Semiconductor
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; PACKETPP = $0000, PPDATA == $630E ?
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@ -153,8 +205,8 @@ fixup02:sta isq+1
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tax
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jsr packetpp_ax
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lda #$63^$0E
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fixup03:eor ppdata
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fixup04:eor ppdata+1
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fixup01:eor ppdata
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fixup02:eor ppdata+1
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beq :+
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sec
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rts
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@ -164,9 +216,9 @@ fixup04:eor ppdata+1
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: lda #$14
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jsr packetpp_a1
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ldy #$40
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fixup05:sty ppdata
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fixup03:sty ppdata
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: jsr packetpp_a1
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fixup06:ldy ppdata
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fixup04:ldy ppdata
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and #$40
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bne :-
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@ -212,7 +264,7 @@ poll:
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; PACKETPP = $0124, PPDATA & $0D00 ?
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lda #$24
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jsr packetpp_a1
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fixup07:lda ppdata+1
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fixup05:lda ppdata+1
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and #$0D
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beq :+
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@ -221,13 +273,13 @@ fixup07:lda ppdata+1
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; Read receiver event and discard it
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; RXTXREG
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fixup08:ldx rxtxreg+1
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fixup09:lda rxtxreg
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fixup06:ldx rxtxreg+1
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fixup07:lda rxtxreg
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; Read frame length
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; cnt = len = RXTXREG
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fixup10:ldx rxtxreg+1
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fixup11:lda rxtxreg
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fixup08:ldx rxtxreg+1
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fixup09:lda rxtxreg
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sta len
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stx len+1
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sta cnt
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@ -255,10 +307,10 @@ fixup11:lda rxtxreg
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; Read bytes into buffer
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: jsr adjustptr
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:
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fixup12:lda rxtxreg
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fixup10:lda rxtxreg
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sta (ptr),y
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iny
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fixup13:lda rxtxreg+1
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fixup11:lda rxtxreg+1
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sta (ptr),y
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iny
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bne :-
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@ -282,12 +334,12 @@ send:
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; Transmit command
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lda #$C9
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ldx #$00
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fixup14:sta txcmd
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fixup15:stx txcmd+1
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fixup12:sta txcmd
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fixup13:stx txcmd+1
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lda cnt
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ldx cnt+1
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fixup16:sta txlen
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fixup17:stx txlen+1
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fixup14:sta txlen
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fixup15:stx txlen+1
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; Adjust odd frame length
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jsr adjustcnt
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@ -299,7 +351,7 @@ fixup17:stx txlen+1
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; PACKETPP = $0138, PPDATA & $0100 ?
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: lda #$38
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jsr packetpp_a1
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fixup18:lda ppdata+1
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fixup16:lda ppdata+1
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and #$01
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bne :+
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@ -318,10 +370,10 @@ fixup18:lda ppdata+1
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; Write bytes from buffer
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: jsr adjustptr
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: lda (ptr),y
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fixup19:sta rxtxreg
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fixup17:sta rxtxreg
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iny
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lda (ptr),y
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fixup20:sta rxtxreg+1
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fixup18:sta rxtxreg+1
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iny
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bne :-
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inc ptr+1
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@ -340,15 +392,15 @@ exit:
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packetpp_a1:
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ldx #$01
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packetpp_ax:
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fixup21:sta packetpp
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fixup22:stx packetpp+1
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fixup19:sta packetpp
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fixup20:stx packetpp+1
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rts
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;---------------------------------------------------------------------
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ppdata_ax:
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fixup23:sta ppdata
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fixup24:stx ppdata+1
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fixup21:sta ppdata
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fixup22:stx ppdata+1
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rts
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;---------------------------------------------------------------------
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; PACKETPP = $0102, PPDATA = PPDATA | $0040
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lda #$02
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jsr packetpp_a1
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fixup25:lda ppdata
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fixup23:lda ppdata
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ora #$40
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fixup26:sta ppdata
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fixup24:sta ppdata
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rts
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;---------------------------------------------------------------------
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@ -4,7 +4,7 @@
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.export _lan91c96_driver_io_base
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__CBM__ = 1
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__C64__ = 1
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DYN_DRV = 0
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.include "lan91c96.s"
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@ -73,8 +73,57 @@ len := ptr3 ; Frame length
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.endif
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;=====================================================================
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.ifdef __C64__
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ethbsr := $DE0E ; Bank select register R/W (2B)
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; Register bank 0
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ethtcr := $DE00 ; Transmition control register R/W (2B)
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ethephsr := $DE02 ; EPH status register R/O (2B)
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ethrcr := $DE04 ; Receive control register R/W (2B)
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ethecr := $DE06 ; Counter register R/O (2B)
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ethmir := $DE08 ; Memory information register R/O (2B)
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ethmcr := $DE0A ; Memory Config. reg. +0 R/W +1 R/O (2B)
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; Register bank 1
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ethcr := $DE00 ; Configuration register R/W (2B)
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ethbar := $DE02 ; Base address register R/W (2B)
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ethiar := $DE04 ; Individual address register R/W (6B)
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ethgpr := $DE0A ; General address register R/W (2B)
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ethctr := $DE0C ; Control register R/W (2B)
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; Register bank 2
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ethmmucr := $DE00 ; MMU command register W/O (1B)
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ethautotx := $DE01 ; AUTO TX start register R/W (1B)
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ethpnr := $DE02 ; Packet number register R/W (1B)
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etharr := $DE03 ; Allocation result register R/O (1B)
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ethfifo := $DE04 ; FIFO ports register R/O (2B)
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ethptr := $DE06 ; Pointer register R/W (2B)
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ethdata := $DE08 ; Data register R/W (4B)
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ethist := $DE0C ; Interrupt status register R/O (1B)
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ethack := $DE0C ; Interrupt acknowledge register W/O (1B)
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ethmsk := $DE0D ; Interrupt mask register R/W (1B)
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; Register bank 3
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ethmt := $DE00 ; Multicast table R/W (8B)
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ethmgmt := $DE08 ; Management interface R/W (2B)
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ethrev := $DE0A ; Revision register R/W (2B)
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ethercv := $DE0C ; Early RCV register R/W (2B)
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;---------------------------------------------------------------------
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.code
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init:
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.endif
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;=====================================================================
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.ifdef __APPLE2__
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.rodata
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fixup: .byte fixup02-fixup01, fixup03-fixup02, fixup04-fixup03
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@ -169,9 +218,14 @@ init:
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bcc :-
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inc ptr+1
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bcs :- ; Always
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:
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.endif
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;=====================================================================
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; Check bank select register upper byte to always read as $33
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: ldy #$00
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ldy #$00
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fixup01:sty ethbsr+1
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fixup02:lda ethbsr+1
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cmp #$33
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@ -5,6 +5,7 @@
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__CBM__ = 1
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__C64__ = 1
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DYN_DRV = 0
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.include "cs8900a.s"
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@ -5,6 +5,7 @@
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__CBM__ = 1
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__VIC20__ = 1
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DYN_DRV = 0
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.include "cs8900a.s"
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