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Code Issues Projects Releases Wiki Activity

1. Replaced IP65 Ethernet drivers with Contiki drivers.

Browse Source 
* CS8900A
The Contiki driver allows to adjust the chip base addr at runtime (which  allows to support different slots in the Apple II) and removes received frames from the chip if there's no room to send frames.

* LAN91C96
The Contiki driver was used by IP65 more or less unchanged in the first place.

* W5100
The Contiki driver allows to adjust the chip base addr at runtime (which  allows to support different slots in the Apple II) and stays clear from the W5100 hybrid mode. It presumes a fully functional W5100 register auto-increment and pre-calculates necessary W5100 frame buffer wrap-arounds and thus achieves the maximal 6502 <-> W5100 transfer speed.
This commit is contained in:
Oliver Schmidt 2014-06-13 00:00:53 +02:00
parent 5c95d03c48
commit e06c02e4a3
15 changed files with 1598 additions and 2122 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

70
drivers/Makefile
View File

@ -1,46 +1,68 @@
AS = ca65
LD = ld65
AFLAGS =
%.o: %.c
$(CC) -c $(CFLAGS) $<
%.o: %.s
$(AS) $(AFLAGS) $<
# c64rrnet.lib : C64 with RR-NET or clone at $de0x
# c64wiznet.lib : C64 with Wiznet W5100 addressed at $df2x
# a2uther.lib : Apple ][ with Uthernet in slot #3
# a2lancegs.lib : Apple ][ with LANceGS
# vic20rrnet.lib : VIC20 with RR-NET or clone at $980x
# c64rrnet.lib : C64 with RR-Net or clone (default base addr: $de0x)
# c64eth64.lib : C64 with ETH64 (default base addr: $de0x)
# a2uther.lib : Apple ][ with Uthernet (default slot: #3)
# a2lancegs.lib : Apple ][ with LANceGS (default slot: #3)
# a2uther2.lib : Apple ][ with Uthernet II (default slot: #3)
# vic20rrnet.lib : VIC20 with RR-Net or clone (default base addr: $980x)
DRIVERS=\
c64rrnet.lib \
c64wiznet.lib \
c64eth64.lib \
a2uther.lib \
a2lancegs.lib \
a2uther2.lib \
vic20rrnet.lib
all: $(DRIVERS)
c64rrnet.lib: rr-net.o cs8900a.o c64zeropage.o c64print.o c64timer.o c64kernal.o c64input.o cbmcharconv.o
%.o: %.s
ca65 -D DYN_DRV=0 $<
C64OBJS=\
contiki.o \
c64zeropage.o \
c64print.o \
c64timer.o \
c64kernal.o \
c64input.o \
cbmcharconv.o
A2OBJS=\
contiki.o \
a2zeropage.o \
a2print.o \
a2timer.o \
a2kernal.o \
a2input.o \
a2charconv.o
VIC20OBJS=\
contiki.o \
vic20zeropage.o \
vic20print.o \
vic20timer.o \
vic20kernal.o \
vic20input.o \
cbmcharconv.o
c64rrnet.lib: rr-net.o cs8900a.o $(C64OBJS)
ar65 a $@ $^
c64wiznet.lib: w5100.o c64zeropage.o c64print.o c64timer.o c64kernal.o c64input.o cbmcharconv.o
c64eth64.lib: eth64.o lan91c96.o $(C64OBJS)
ar65 a $@ $^
a2lancegs.lib: lan91c96.o a2zeropage.o a2print.o a2timer.o a2kernal.o a2input.o a2charconv.o
a2uther.lib: uthernet.o cs8900a.o $(A2OBJS)
ar65 a $@ $^
a2uther.lib: uthernet.o cs8900a.o a2zeropage.o a2print.o a2timer.o a2kernal.o a2input.o a2charconv.o
a2lancegs.lib: lancegs.o lan91c96.o $(A2OBJS)
ar65 a $@ $^
vic20rrnet.lib: vic20-rr-net.o cs8900a.o vic20zeropage.o vic20print.o vic20timer.o vic20kernal.o vic20input.o cbmcharconv.o
a2uther2.lib: uthernet2.o w5100.o $(A2OBJS)
ar65 a $@ $^
vic20rrnet.lib: vic20-rr-net.o cs8900a.o $(VIC20OBJS)
ar65 a $@ $^
clean:
-rm -f *.o
-rm -f *.lib
distclean: clean
-rm -f *~

96
drivers/contiki.s Normal file
View File

@ -0,0 +1,96 @@
; Contiki driver wrapper
.include "../inc/common.i"
.export eth_init
.export eth_rx
.export eth_tx
.import eth_inp
.import eth_inp_len
.import eth_outp
.import eth_outp_len
.import eth_driver_io_base
.import cfg_mac
.import eth
.struct driver
drvtype .byte 3
apiver .byte
mac .byte 6
bufaddr .addr
bufsize .word
init .byte 3
poll .byte 3
send .byte 3
exit .byte 3
.endstruct
.code
; initialize the ethernet adaptor
; inputs: none
; outputs: carry flag is set if there was an error, clear otherwise
eth_init:
ldax #1518
stax eth+driver::bufsize
ldax eth_driver_io_base
jsr eth+driver::init
ldx #5
: lda eth+driver::mac,x
sta cfg_mac,x
dex
bpl :-
rts
; receive a packet
; inputs: none
; outputs:
; if there was an error receiving the packet (or no packet was ready) then carry flag is set
; if packet was received correctly then carry flag is clear,
; eth_inp contains the received packet,
; and eth_inp_len contains the length of the packet
eth_rx:
ldax #eth_inp
stax eth+driver::bufaddr
jsr eth+driver::poll
stax eth_inp_len
rts
; send a packet
; inputs:
; eth_outp: packet to send
; eth_outp_len: length of packet to send
; outputs:
; if there was an error sending the packet then carry flag is set
; otherwise carry flag is cleared
eth_tx:
ldax #eth_outp
stax eth+driver::bufaddr
ldax eth_outp_len
jmp eth+driver::send
; -- LICENSE FOR contiki.s --
; The contents of this file are subject to the Mozilla Public License
; Version 1.1 (the "License"); you may not use this file except in
; compliance with the License. You may obtain a copy of the License at
; http://www.mozilla.org/MPL/
;
; Software distributed under the License is distributed on an "AS IS"
; basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See the
; License for the specific language governing rights and limitations
; under the License.
;
; The Original Code is ip65.
;
; The Initial Developer of the Original Code is Jonno Downes,
; jonno@jamtronix.com.
; Portions created by the Initial Developer are Copyright (C) 2009
; Jonno Downes. All Rights Reserved.
; -- LICENSE END --

665
drivers/cs8900a.s
View File

@ -1,282 +1,391 @@
; Ethernet driver for CS8900A chip (as used in RR-NET and Uthernet adapters)
;
; Based on Doc Bacardi's tftp source
.ifndef KPR_API_VERSION_NUMBER
.define EQU =
.include "../inc/kipper_constants.i"
.endif
.include "../inc/common.i"
.include "cs8900a.i"
.export eth_init
.export eth_rx
.export eth_tx
.import eth_inp
.import eth_inp_len
.import eth_outp
.import eth_outp_len
.importzp eth_dest
.importzp eth_src
.importzp eth_type
.importzp eth_data
.import cs_init
.import cs_packet_page
.import cs_packet_data
.import cs_rxtx_data
.import cs_tx_cmd
.import cs_tx_len
.import cfg_mac
.importzp eth_packet
.import ip65_error
.macro write_page page, value
lda #page/2
ldx #<value
ldy #>value
jsr cs_write_page
.endmacro
.code
; initialize the ethernet adaptor
; inputs: none
; outputs: carry flag is set if there was an error, clear otherwise
eth_init:
jsr cs_init
lda #0 ; check magic signature
jsr cs_read_page
cpx #$0e
bne @notfound
cpy #$63
bne @notfound
lda #1
jsr cs_read_page
cpx #0
bne @notfound
; y contains chip rev
write_page pp_self_ctl, $0055 ; $0114, reset chip
write_page pp_rx_ctl, $0d05 ; $0104, accept individual and broadcast packets
lda #pp_ia/2 ; $0158, write mac address
ldx cfg_mac
ldy cfg_mac + 1
jsr cs_write_page
lda #pp_ia/2 + 1
ldx cfg_mac + 2
ldy cfg_mac + 3
jsr cs_write_page
lda #pp_ia/2 + 2
ldx cfg_mac + 4
ldy cfg_mac + 5
jsr cs_write_page
write_page pp_line_ctl, $00d3 ; $0112, enable rx and tx
clc
rts
@notfound:
sec
rts
; receive a packet
; inputs: none
; outputs:
; if there was an error receiving the packet (or no packet was ready) then carry flag is set
; if packet was received correctly then carry flag is clear,
; eth_inp contains the received packet,
; and eth_inp_len contains the length of the packet
eth_rx:
lda #$24 ; check rx status
sta cs_packet_page
lda #$01
sta cs_packet_page + 1
lda cs_packet_data + 1
and #$0d
bne :+
sec ; no packet ready
rts
: lda cs_rxtx_data + 1 ; ignore status
lda cs_rxtx_data
lda cs_rxtx_data + 1 ; read packet length
sta eth_inp_len + 1
tax ; save
lda cs_rxtx_data
sta eth_inp_len
lda #<eth_inp ; set packet pointer
sta eth_packet
lda #>eth_inp
sta eth_packet + 1
ldy #0
cpx #0 ; < 256 bytes left?
beq @tail
@get256:
lda cs_rxtx_data
sta (eth_packet),y
iny
lda cs_rxtx_data + 1
sta (eth_packet),y
iny
bne @get256
inc eth_packet + 1
dex
bne @get256
@tail:
lda eth_inp_len ; bytes left / 2, round up
lsr
adc #0
beq @done
tax
@get:
lda cs_rxtx_data
sta (eth_packet),y
iny
lda cs_rxtx_data + 1
sta (eth_packet),y
iny
dex
bne @get
@done:
clc
rts
; send a packet
; inputs:
; eth_outp: packet to send
; eth_outp_len: length of packet to send
; outputs:
; if there was an error sending the packet then carry flag is set
; otherwise carry flag is cleared
eth_tx:
lda #$c9 ; ask for buffer space
sta cs_tx_cmd
lda #0
sta cs_tx_cmd + 1
lda eth_outp_len ; set length
sta cs_tx_len
lda eth_outp_len + 1
sta cs_tx_len + 1
cmp #6
bmi :+
lda #KPR_ERROR_INPUT_TOO_LARGE
sta ip65_error
sec ; oversized packet
rts
: lda #<pp_bus_status ; select bus status register
sta cs_packet_page
lda #>pp_bus_status
sta cs_packet_page + 1
@waitspace:
lda cs_packet_data + 1 ; wait for space
ldx cs_packet_data
lsr
bcs @gotspace
jsr @done ; polling too fast doesn't work, delay added by David Schmidt
jmp @waitspace
@gotspace:
ldax #eth_outp ; send packet
stax eth_packet
ldy #0
ldx eth_outp_len + 1
beq @tail
@send256:
lda (eth_packet),y
sta cs_rxtx_data
iny
lda (eth_packet),y
sta cs_rxtx_data + 1
iny
bne @send256
inc eth_packet + 1
dex
bne @send256
@tail:
ldx eth_outp_len
beq @done
@send:
lda (eth_packet),y
sta cs_rxtx_data
dex
beq @done
iny
lda (eth_packet),y
sta cs_rxtx_data + 1
iny
dex
bne @send
@done: ; also used by timeout code above
clc
rts
; read X/Y from page A * 2
cs_read_page:
asl
sta cs_packet_page
lda #0
rol
sta cs_packet_page + 1
ldx cs_packet_data
ldy cs_packet_data + 1
rts
; write X/Y to page A * 2
cs_write_page:
asl
sta cs_packet_page
lda #0
rol
sta cs_packet_page + 1
stx cs_packet_data
sty cs_packet_data + 1
rts
; -- LICENSE FOR cs8900a.s --
; The contents of this file are subject to the Mozilla Public License
; Version 1.1 (the "License"); you may not use this file except in
; compliance with the License. You may obtain a copy of the License at
; http://www.mozilla.org/MPL/
; Copyright (c) 2007, Adam Dunkels and Oliver Schmidt
; All rights reserved.
;
; Software distributed under the License is distributed on an "AS IS"
; basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See the
; License for the specific language governing rights and limitations
; under the License.
; Redistribution and use in source and binary forms, with or without
; modification, are permitted provided that the following conditions
; are met:
; 1. Redistributions of source code must retain the above copyright
; notice, this list of conditions and the following disclaimer.
; 2. Redistributions in binary form must reproduce the above copyright
; notice, this list of conditions and the following disclaimer in the
; documentation and/or other materials provided with the distribution.
; 3. Neither the name of the Institute nor the names of its contributors
; may be used to endorse or promote products derived from this software
; without specific prior written permission.
;
; The Original Code is ip65.
; THIS SOFTWARE IS PROVIDED BY THE INSTITUTE AND CONTRIBUTORS ``AS IS'' AND
; ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
; ARE DISCLAIMED. IN NO EVENT SHALL THE INSTITUTE OR CONTRIBUTORS BE LIABLE
; FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
; DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
; OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
; HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
; LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
; OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
; SUCH DAMAGE.
;
; The Initial Developer of the Original Code is Per Olofsson,
; MagerValp@gmail.com.
; Portions created by the Initial Developer are Copyright (C) 2009
; Per Olofsson. All Rights Reserved.
; -- LICENSE END --
; This file is part of the Contiki operating system.
;
; Author: Adam Dunkels <adam@sics.se>, Oliver Schmidt <ol.sc@web.de>
;
;---------------------------------------------------------------------
.macpack module
module_header _cs8900a
; Driver signature
.byte $65, $74, $68 ; "eth"
.byte $01 ; Ethernet driver API version number
; Ethernet address
mac: .byte $00, $0E, $3A ; OUI of Cirrus Logic
.byte $11, $11, $11
; Buffer attributes
bufaddr:.res 2 ; Address
bufsize:.res 2 ; Size
; Jump table.
jmp init
jmp poll
jmp send
jmp exit
;---------------------------------------------------------------------
.if DYN_DRV
.zeropage
sp: .res 2 ; Stack pointer (Do not trash !)
reg: .res 2 ; Address of rxtxreg
ptr: .res 2 ; Indirect addressing pointer
len: .res 2 ; Frame length
cnt: .res 2 ; Frame length counter
.else
.include "zeropage.inc"
reg := ptr1 ; Address of rxtxreg
ptr := ptr2 ; Indirect addressing pointer
len := ptr3 ; Frame length
cnt := ptr4 ; Frame length counter
.endif
;---------------------------------------------------------------------
.rodata
fixup: .byte fixup02-fixup01, fixup03-fixup02, fixup04-fixup03
.byte fixup05-fixup04, fixup06-fixup05, fixup07-fixup06
.byte fixup08-fixup07, fixup09-fixup08, fixup10-fixup09
.byte fixup11-fixup10, fixup12-fixup11, fixup13-fixup12
.byte fixup14-fixup13, fixup15-fixup14, fixup16-fixup15
.byte fixup17-fixup16, fixup18-fixup17, fixup19-fixup18
.byte fixup20-fixup19, fixup21-fixup20, fixup22-fixup21
.byte fixup23-fixup22, fixup24-fixup23, fixup25-fixup24
.byte fixup26-fixup25
fixups = * - fixup
;---------------------------------------------------------------------
rxtxreg := $FF00 ; High byte patched at runtime
txcmd := $FF04 ; High byte patched at runtime
txlen := $FF06 ; High byte patched at runtime
isq := $FF08 ; High byte patched at runtime
packetpp := $FF0A ; High byte patched at runtime
ppdata := $FF0C ; High byte patched at runtime
.data
;---------------------------------------------------------------------
init:
; Save address of rxtxreg
sta reg
stx reg+1
; Start with first fixup location
lda #<(fixup01+1)
ldx #>(fixup01+1)
sta ptr
stx ptr+1
ldx #$FF
ldy #$00
; Fixup address at location
: lda reg
eor (ptr),y ; Use XOR to support C64 RR-Net
sta (ptr),y
iny
lda reg+1
sta (ptr),y
dey
; Advance to next fixup location
inx
cpx #fixups
bcs :+
lda ptr
clc
adc fixup,x
sta ptr
bcc :-
inc ptr+1
bcs :- ; Always
; Activate C64 RR clockport in order to operate RR-Net
; - RR config register overlays CS8900A ISQ register
; - No need to distinguish as ISQ access doesn't hurt
:
fixup01:lda isq+1
ora #$01 ; Set clockport bit
fixup02:sta isq+1
; Check EISA registration number of Crystal Semiconductor
; PACKETPP = $0000, PPDATA == $630E ?
lda #$00
tax
jsr packetpp_ax
lda #$63^$0E
fixup03:eor ppdata
fixup04:eor ppdata+1
beq :+
sec
rts
; Initiate a chip-wide reset
; PACKETPP = $0114, PPDATA = $0040
: lda #$14
jsr packetpp_a1
ldy #$40
fixup05:sty ppdata
: jsr packetpp_a1
fixup06:ldy ppdata
and #$40
bne :-
; Accept valid unicast + broadcast frames
; PACKETPP = $0104, PPDATA = $0D05
lda #$04
jsr packetpp_a1
lda #$05
ldx #$0D
jsr ppdata_ax
; Set MAC address
; PACKETPP = $0158, PPDATA = MAC[0], MAC[1]
; PACKETPP = $015A, PPDATA = MAC[2], MAC[3]
; PACKETPP = $015C, PPDATA = MAC[4], MAC[5]
ldy #$58
: tya
jsr packetpp_a1
lda mac-$58,y
ldx mac-$58+1,y
jsr ppdata_ax
iny
iny
cpy #$58+6
bcc :-
; Turn on transmission and reception of frames
; PACKETPP = $0112, PPDATA = $00D3
lda #$12
jsr packetpp_a1
lda #$D3
ldx #$00
jsr ppdata_ax
txa
clc
rts
;---------------------------------------------------------------------
poll:
; Check receiver event register to see if there
; are any valid unicast frames avaliable
; PACKETPP = $0124, PPDATA & $0D00 ?
lda #$24
jsr packetpp_a1
fixup07:lda ppdata+1
and #$0D
beq :+
; Process the incoming frame
; --------------------------
; Read receiver event and discard it
; RXTXREG
fixup08:ldx rxtxreg+1
fixup09:lda rxtxreg
; Read frame length
; cnt = len = RXTXREG
fixup10:ldx rxtxreg+1
fixup11:lda rxtxreg
sta len
stx len+1
sta cnt
stx cnt+1
; Adjust odd frame length
jsr adjustcnt
; Is bufsize < cnt ?
lda bufsize
cmp cnt
lda bufsize+1
sbc cnt+1
bcs :++
; Yes, skip frame
jsr skipframe
; No frame ready
lda #$00
: tax
sec
rts
; Read bytes into buffer
: jsr adjustptr
:
fixup12:lda rxtxreg
sta (ptr),y
iny
fixup13:lda rxtxreg+1
sta (ptr),y
iny
bne :-
inc ptr+1
dex
bpl :-
; Return frame length
lda len
ldx len+1
clc
rts
;---------------------------------------------------------------------
send:
; Save frame length
sta cnt
stx cnt+1
; Transmit command
lda #$C9
ldx #$00
fixup14:sta txcmd
fixup15:stx txcmd+1
lda cnt
ldx cnt+1
fixup16:sta txlen
fixup17:stx txlen+1
; Adjust odd frame length
jsr adjustcnt
; 8 retries
ldy #$08
; Check for avaliable buffer space
; PACKETPP = $0138, PPDATA & $0100 ?
: lda #$38
jsr packetpp_a1
fixup18:lda ppdata+1
and #$01
bne :+
; No space avaliable, skip a received frame
jsr skipframe
; And try again
dey
bne :-
sec
rts
; Send the frame
; --------------
; Write bytes from buffer
: jsr adjustptr
: lda (ptr),y
fixup19:sta rxtxreg
iny
lda (ptr),y
fixup20:sta rxtxreg+1
iny
bne :-
inc ptr+1
dex
bpl :-
clc
rts
;---------------------------------------------------------------------
exit:
rts
;---------------------------------------------------------------------
packetpp_a1:
ldx #$01
packetpp_ax:
fixup21:sta packetpp
fixup22:stx packetpp+1
rts
;---------------------------------------------------------------------
ppdata_ax:
fixup23:sta ppdata
fixup24:stx ppdata+1
rts
;---------------------------------------------------------------------
skipframe:
; PACKETPP = $0102, PPDATA = PPDATA | $0040
lda #$02
jsr packetpp_a1
fixup25:lda ppdata
ora #$40
fixup26:sta ppdata
rts
;---------------------------------------------------------------------
adjustcnt:
lsr
bcc :+
inc cnt
bne :+
inc cnt+1
: rts
;---------------------------------------------------------------------
adjustptr:
lda cnt
ldx cnt+1
eor #$FF ; Two's complement part 1
tay
iny ; Two's complement part 2
sty reg
sec
lda bufaddr
sbc reg
sta ptr
lda bufaddr+1
sbc #$00
sta ptr+1
rts
;---------------------------------------------------------------------

26
drivers/cs8900a.i → drivers/eth64.s
View File

@ -1,14 +1,26 @@
; originally from Per Olofsson's IP65 library - http://www.paradroid.net/ip65
; ETH64 driver
pp_rx_ctl = $0104
pp_line_ctl = $0112
pp_self_ctl = $0114
pp_bus_status = $0138
pp_ia = $0158
.import _lan91c96
.export eth = _lan91c96
.export eth_driver_name
.export eth_driver_io_base
.rodata
eth_driver_name:
.byte "ETH64",0
.data
eth_driver_io_base:
.word $de00
; -- LICENSE FOR cs8900a.i --
; -- LICENSE FOR eth64.s --
; The contents of this file are subject to the Mozilla Public License
; Version 1.1 (the "License"); you may not use this file except in
; compliance with the License. You may obtain a copy of the License at

751
drivers/lan91c96.s
View File

@ -1,458 +1,427 @@
; Ethernet driver for SMC LAN91C96 chip
;
; Copyright (c) 2003-2007, Adam Dunkels, Josef Soucek and Oliver Schmidt
; All rights reserved.
;
; Redistribution and use in source and binary forms, with or without
; modification, are permitted provided that the following conditions
; are met:
; 1. Redistributions of source code must retain the above copyright
; notice, this list of conditions and the following disclaimer.
; 2. Redistributions in binary form must reproduce the above copyright
; notice, this list of conditions and the following disclaimer in the
; documentation and/or other materials provided with the distribution.
; 3. Neither the name of the Institute nor the names of its contributors
; may be used to endorse or promote products derived from this software
; without specific prior written permission.
;
; THIS SOFTWARE IS PROVIDED BY THE INSTITUTE AND CONTRIBUTORS ``AS IS'' AND
; ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
; ARE DISCLAIMED. IN NO EVENT SHALL THE INSTITUTE OR CONTRIBUTORS BE LIABLE
; FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
; DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
; OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
; HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
; LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
; OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
; SUCH DAMAGE.
;
; This file is part of the Contiki operating system.
;
; Author: Adam Dunkels <adam@sics.se>, Josef Soucek <josef.soucek@ide64.org>,
; Oliver Schmidt <ol.sc@web.de>
;
;---------------------------------------------------------------------
.ifndef KPR_API_VERSION_NUMBER
.define EQU =
.include "../inc/kipper_constants.i"
.endif
.macpack module
module_header _lan91c96
.include "../inc/common.i"
; Driver signature
.byte $65, $74, $68 ; "eth"
.byte $01 ; Ethernet driver API version number
.export eth_init
.export eth_rx
.export eth_tx
.export eth_driver_name
.export eth_driver_io_base
.import eth_inp
.import eth_inp_len
.import eth_outp
.import eth_outp_len
; Ethernet address
mac: .byte $00, $80, $0F ; OUI of Standard Microsystems
.byte $11, $11, $11
.import cfg_mac
.importzp eth_packet
; Buffer attributes
bufaddr:.res 2 ; Address
bufsize:.res 2 ; Size
; LANceGS hardware addresses
ethbsr := $c00E ; Bank select register R/W (2B)
; Jump table.
jmp init
jmp poll
jmp send
jmp exit
;---------------------------------------------------------------------
.if DYN_DRV
.zeropage
sp: .res 2 ; Stack pointer (Do not trash !)
reg: .res 2 ; Address of register base
ptr: .res 2 ; Indirect addressing pointer
len: .res 2 ; Frame length
.else
.include "zeropage.inc"
reg := ptr1 ; Address of register base
ptr := ptr2 ; Indirect addressing pointer
len := ptr3 ; Frame length
.endif
;---------------------------------------------------------------------
.rodata
fixup: .byte fixup02-fixup01, fixup03-fixup02, fixup04-fixup03
.byte fixup05-fixup04, fixup06-fixup05, fixup07-fixup06
.byte fixup08-fixup07, fixup09-fixup08, fixup10-fixup09
.byte fixup11-fixup10, fixup12-fixup11, fixup13-fixup12
.byte fixup14-fixup13, fixup15-fixup14, fixup16-fixup15
.byte fixup17-fixup16, fixup18-fixup17, fixup19-fixup18
.byte fixup20-fixup19, fixup21-fixup20, fixup22-fixup21
.byte fixup23-fixup22, fixup24-fixup23, fixup25-fixup24
.byte fixup26-fixup25, fixup27-fixup26, fixup28-fixup27
.byte fixup29-fixup28, fixup30-fixup29, fixup31-fixup30
.byte fixup32-fixup31, fixup33-fixup32, fixup34-fixup33
.byte fixup35-fixup34, fixup36-fixup35, fixup37-fixup36
.byte fixup38-fixup37, fixup39-fixup38, fixup40-fixup39
fixups = * - fixup
;---------------------------------------------------------------------
ethbsr := $FF0E ; Bank select register R/W (2B)
; Register bank 0
ethtcr := $c000 ; Transmission control register R/W (2B)
ethephsr := $c002 ; EPH status register R/O (2B)
ethrcr := $c004 ; Receive control register R/W (2B)
ethecr := $c006 ; Counter register R/O (2B)
ethmir := $c008 ; Memory information register R/O (2B)
ethmcr := $c00A ; Memory Config. reg. +0 R/W +1 R/O (2B)
ethtcr := $FF00 ; Transmition control register R/W (2B)
ethephsr := $FF02 ; EPH status register R/O (2B)
ethrcr := $FF04 ; Receive control register R/W (2B)
ethecr := $FF06 ; Counter register R/O (2B)
ethmir := $FF08 ; Memory information register R/O (2B)
ethmcr := $FF0A ; Memory Config. reg. +0 R/W +1 R/O (2B)
; Register bank 1
ethcr := $c000 ; Configuration register R/W (2B)
ethbar := $c002 ; Base address register R/W (2B)
ethiar := $c004 ; Individual address register R/W (6B)
ethgpr := $c00A ; General address register R/W (2B)
ethctr := $c00C ; Control register R/W (2B)
ethcr := $FF00 ; Configuration register R/W (2B)
ethbar := $FF02 ; Base address register R/W (2B)
ethiar := $FF04 ; Individual address register R/W (6B)
ethgpr := $FF0A ; General address register R/W (2B)
ethctr := $FF0C ; Control register R/W (2B)
; Register bank 2
ethmmucr := $c000 ; MMU command register W/O (1B)
ethautotx := $c001 ; AUTO TX start register R/W (1B)
ethpnr := $c002 ; Packet number register R/W (1B)
etharr := $c003 ; Allocation result register R/O (1B)
ethfifo := $c004 ; FIFO ports register R/O (2B)
ethptr := $c006 ; Pointer register R/W (2B)
ethdata := $c008 ; Data register R/W (4B)
ethist := $c00C ; Interrupt status register R/O (1B)
ethack := $c00C ; Interrupt acknowledge register W/O (1B)
ethmsk := $c00D ; Interrupt mask register R/W (1B)
ethmmucr := $FF00 ; MMU command register W/O (1B)
ethautotx := $FF01 ; AUTO TX start register R/W (1B)
ethpnr := $FF02 ; Packet number register R/W (1B)
etharr := $FF03 ; Allocation result register R/O (1B)
ethfifo := $FF04 ; FIFO ports register R/O (2B)
ethptr := $FF06 ; Pointer register R/W (2B)
ethdata := $FF08 ; Data register R/W (4B)
ethist := $FF0C ; Interrupt status register R/O (1B)
ethack := $FF0C ; Interrupt acknowledge register W/O (1B)
ethmsk := $FF0D ; Interrupt mask register R/W (1B)
; Register bank 3
ethmt := $c000 ; Multicast table R/W (8B)
ethmgmt := $c008 ; Management interface R/W (2B)
ethrev := $c00A ; Revision register R/W (2B)
ethercv := $c00C ; Early RCV register R/W (2B)
ethmt := $FF00 ; Multicast table R/W (8B)
ethmgmt := $FF08 ; Management interface R/W (2B)
ethrev := $FF0A ; Revision register R/W (2B)
ethercv := $FF0C ; Early RCV register R/W (2B)
.data
.data
;---------------------------------------------------------------------
; initialize the ethernet adaptor
; inputs: none
; outputs: carry flag is set if there was an error, clear otherwise
eth_init:
jsr lan_self_modify
lda #$01
fixlan00:
sta ethbsr ; Select register bank 1
fixlan01:
lda ethcr ; Read first four bytes - $31, $20, $67, $18
cmp #$31
bne lanerror
fixlan03:
lda ethbar
cmp #$67
bne lanerror
fixlan04:
lda ethbar+1
cmp #$18
bne lanerror
; we have the magic signature
init:
; Save address of register base
sta reg
stx reg+1
; Reset ETH card
lda #$00 ; Bank 0
fixlan05:
sta ethbsr
lda #%10000000 ; Software reset
fixlan06:
sta ethrcr+1
; Start with first fixup location
lda #<(fixup01+1)
ldx #>(fixup01+1)
sta ptr
stx ptr+1
ldx #$FF
ldy #$00
ldy #$00
fixlan07:
sty ethrcr
fixlan08:
sty ethrcr+1
; Fixup address at location
: lda reg
ora (ptr),y
sta (ptr),y
iny
lda reg+1
sta (ptr),y
dey
; Delay
: cmp ($FF,x) ; 6 cycles
cmp ($FF,x) ; 6 cycles
iny ; 2 cycles
bne :- ; 3 cycles
; 17 * 256 = 4352 -> 4,4 ms
; Advance to next fixup location
inx
cpx #fixups
bcs :+
lda ptr
clc
adc fixup,x
sta ptr
bcc :-
inc ptr+1
bcs :- ; Always
; Enable transmit and receive
lda #%10000001 ; Enable transmit TXENA, PAD_EN
ldx #%00000011 ; Enable receive, strip CRC ???
fixlan09:
sta ethtcr
fixlan10:
stx ethrcr+1
; Reset ETH card
: lda #$00 ; Bank 0
fixup01:sta ethbsr
lda #$01 ; Bank 1
fixlan11:
sta ethbsr
lda #%10000000 ; Software reset
fixup02:sta ethrcr+1
fixlan12:
lda ethcr+1
ora #%00010000 ; No wait (IOCHRDY)
fixlan13:
sta ethcr+1
ldy #$00
fixup03:sty ethrcr
fixup04:sty ethrcr+1
lda #%00001001 ; Auto release
fixlan14:
sta ethctr+1
; Delay
: cmp ($FF,x) ; 6 cycles
cmp ($FF,x) ; 6 cycles
iny ; 2 cycles
bne :- ; 3 cycles
; 17 * 256 = 4352 -> 4,4 ms
; Set MAC address
lda cfg_mac
ldx cfg_mac + 1
fixlan15:
sta ethiar
fixlan16:
stx ethiar + 1
lda cfg_mac + 2
ldx cfg_mac + 3
fixlan17:
sta ethiar + 2
fixlan18:
stx ethiar + 3
lda cfg_mac + 4
ldx cfg_mac + 5
fixlan19:
sta ethiar + 4
fixlan20:
stx ethiar + 5
; Enable transmit and receive
lda #%10000001 ; Enable transmit TXENA, PAD_EN
ldx #%00000011 ; Enable receive, strip CRC ???
fixup05:sta ethtcr
fixup06:stx ethrcr+1
; Set interrupt mask
lda #$02 ; Bank 2
fixlan21:
sta ethbsr
lda #$01 ; Bank 1
fixup07:sta ethbsr
lda #%00000000 ; No interrupts
fixlan22:
sta ethmsk
clc
rts
; Check ISA mode base address register for reset values
lda #$18^67 ; I/O base $300 + ROM $CC000
fixup08:eor ethbar
fixup09:eor ethbar+1
beq :+
sec
rts
lanerror:
sec
rts
:
fixup10:lda ethcr+1
ora #%00010000 ; No wait (IOCHRDY)
fixup11:sta ethcr+1
; receive a packet
; inputs: none
; outputs:
; if there was an error receiving the packet (or no packet was ready) then carry flag is set
; if packet was received correctly then carry flag is clear,
; eth_inp contains the received packet,
; and eth_inp_len contains the length of the packet
eth_rx:
fixlan38:
lda ethist
and #%00000001 ; Check receive interrupt
bne :+
sec ; No packet available
rts
lda #%00001001 ; Auto release
fixup12:sta ethctr+1
: lda #$00
ldx #%11100000 ; Receive, Auto Increment, Read
fixlan39:
sta ethptr
fixlan40:
stx ethptr + 1
; Set MAC address
ldy #$00
: lda mac,y
fixup13:sta ethiar,y
iny
cpy #$06
bcc :-
; Last word contains 'last data byte' and $60 or 'fill byte' and $40
fixlan41:
lda ethdata ; Status word
fixlan42:
lda ethdata ; Only need high byte
; Set interrupt mask
lda #$02 ; Bank 2
fixup14:sta ethbsr
; Move ODDFRM bit into carry:
; - Even packet length -> carry clear -> subtract 6 bytes
; - Odd packet length -> carry set -> subtract 5 bytes
lsr
lsr
lsr
lsr
lsr
lda #%00000000 ; No interrupts
fixup15:sta ethmsk
tax
clc
rts
; The packet contains 3 extra words
fixlan43:
lda ethdata ; Total number of bytes
sbc #$05 ; Actually 5 or 6 depending on carry
sta eth_inp_len
fixlan44:
lda ethdata
sbc #$00
sta eth_inp_len+1
;---------------------------------------------------------------------
; Read bytes into buffer
lda #<eth_inp
ldx #>eth_inp
sta eth_packet
stx eth_packet+1
ldx eth_inp_len+1
ldy #$00
lanread:
fixlan46:
lda ethdata
sta (eth_packet),y
iny
bne :+
inc eth_packet+1
: cpy eth_inp_len
bne lanread
dex
bpl lanread
poll:
fixup16:lda ethist
and #%00000001 ; RCV INT
beq :+
; Remove and release RX packet from the FIFO
lda #%10000000
fixlan47:
sta ethmmucr
; Process the incoming packet
; ---------------------------
lda #$00
ldx #%11100000 ; RCV, AUTO INCR., READ
fixup17:sta ethptr
fixup18:stx ethptr+1
clc
rts
; Last word contains 'last data byte' and $60 or 'fill byte' and $40
fixup19:lda ethdata ; Status word
fixup20:lda ethdata ; Need high byte only
; send a packet
; inputs:
; eth_outp: packet to send
; eth_outp_len: length of packet to send
; outputs:
; if there was an error sending the packet then carry flag is set
; otherwise carry flag is cleared
eth_tx:
lda eth_outp_len + 1
ora #%00100000
fixlan23:
sta ethmmucr ; Allocate memory for transmission
fixlan24:
lda ethist
and #%00001000 ; Allocation interrupt
bne :+
sec
rts ; Not able to allocate; bail
; Move ODDFRM bit into carry:
; - Even packet length -> carry clear -> subtract 6 bytes
; - Odd packet length -> carry set -> subtract 5 bytes
lsr
lsr
lsr
lsr
lsr
: lda #%00001000
fixlan25:
sta ethack ; Acknowledge interrupt
; The packet contains 3 extra words
fixup21:lda ethdata ; Total number of bytes
sbc #$05 ; Actually 5 or 6 depending on carry
sta len
fixup22:lda ethdata
sbc #$00
sta len+1
fixlan26:
lda etharr
fixlan27:
sta ethpnr ; Set packet number
; Is bufsize < len ?
lda bufsize
cmp len
lda bufsize+1
sbc len+1
bcs :++
lda #$00
ldx #%01000000 ; Auto increment
fixlan28:
sta ethptr
fixlan29:
stx ethptr + 1
; Yes, skip packet
; Remove and release RX packet from the FIFO
lda #%10000000
fixup23:sta ethmmucr
lda #$00 ; Status written by CSMA
fixlan30:
sta ethdata
fixlan31:
sta ethdata
; No packet available
lda #$00
: tax
sec
rts
lda eth_outp_len
eor #$01
lsr
lda eth_outp_len
adc #$05 ; Actually will be 5 or 6 depending on carry
fixlan32:
sta ethdata
lda eth_outp_len + 1
adc #$00
fixlan33:
sta ethdata
; Read bytes into buffer
: jsr adjustptr
:
fixup24:lda ethdata
sta (ptr),y
iny
bne :-
inc ptr+1
dex
bpl :-
lda #<eth_outp ; Send the packet
ldx #>eth_outp
sta eth_packet
stx eth_packet + 1
ldx eth_outp_len + 1
ldy #$00
lanwrite:
lda (eth_packet),y
fixlan34:
sta ethdata
iny
bne :+
inc eth_packet + 1
: cpy eth_outp_len
bne lanwrite
dex
bpl lanwrite
; Remove and release RX packet from the FIFO
lda #%10000000
fixup25:sta ethmmucr
lda eth_outp_len ; Odd packet length?
lsr
bcc :+
; Return packet length
lda len
ldx len+1
clc
rts
lda #%001000000 ; Yes, Odd
bne fixlan36 ; Always
;---------------------------------------------------------------------
: lda #$00 ; No
fixlan35:
sta ethdata ; Fill byte
fixlan36:
sta ethdata ; Control byte
lda #%11000000 ; Enqueue packet - transmit
fixlan37:
sta ethmmucr
send:
; Save packet length
sta len
stx len+1
clc
rts
; Allocate memory for TX
txa
ora #%00100000
fixup26:sta ethmmucr
;
; lan_self_modify - make all entry points variable so we can move the
; LANceGS card around in the Apple
;
lan_self_modify:
lda #$C0 ; FIXME - hardcoded to slot 4
clc ; We'll be adding later, so clear carry
; Make the accumulator contain slot number plus $80
; i.e. Slot 1 = $90
; i.e. Slot 2 = $A0
; i.e. Slot 3 = $B0
; i.e. Slot 4 = $C0
; i.e. Slot 5 = $D0
; i.e. Slot 6 = $E0
; i.e. Slot 7 = $F0
; $C0s0: Save off all ethtcr, ethcr, ethmmucr, and ethmt mods
sta fixlan01 + 1
sta fixlan09 + 1
sta fixlan23 + 1
sta fixlan37 + 1
; sta fixlan45 + 1 ; Removed
sta fixlan47 + 1
; 8 retries
ldy #$08
; $C0s1: Save off all ethtcr+1, ethcr+1, ethmmucr+1, and ethmt+1 mods
adc #$01
; sta fixlan02 + 1 ; Removed
sta fixlan12 + 1
sta fixlan13 + 1
; Wait for allocation ready
:
fixup27:lda ethist
and #%00001000 ; ALLOC INT
bne :+
; $C0s2: Save off all ethephsr, ethbar, and ethpnr mods
adc #$01
sta fixlan03 + 1
sta fixlan27 + 1
; Shouldn't we do something here to actively free memory,
; maybe removing and releasing an RX packet from the FIFO ???
; $C0s3: Save off all ethephsr+1, ethbar+1, ethpnr+1, and etharr mods
adc #$01
sta fixlan04 + 1
sta fixlan26 + 1
; And try again
dey
bne :-
sec
rts
; $C0s4: Save off all ethrcr, ethiar, and ethfifo mods
adc #$01
sta fixlan07 + 1
sta fixlan15 + 1
; Acknowledge interrupt, is it necessary ???
: lda #%00001000
fixup28:sta ethack
; $C0s5: Save off all ethrcr+1, ethiar+1, and ethfifo+1 mods
adc #$01
sta fixlan06 + 1
sta fixlan08 + 1
sta fixlan10 + 1
sta fixlan16 + 1
; Set packet address
fixup29:lda etharr
fixup30:sta ethpnr
; $C0s6: Save off all ethecr, ethptr, and ethiar+2 mods
adc #$01
sta fixlan17 + 1
sta fixlan28 + 1
sta fixlan39 + 1
lda #$00
ldx #%01000000 ; AUTO INCR.
fixup31:sta ethptr
fixup32:stx ethptr+1
; $C0s7: Save off all ethecr+1, ethptr+1, and ethiar+3 mods
adc #$01
sta fixlan18 + 1
sta fixlan29 + 1
sta fixlan40 + 1
; Status written by CSMA
lda #$00
fixup33:sta ethdata
fixup34:sta ethdata
; $C0s8: Save off all ethmir, ethdata, ethmgmt, and ethiar+4 mods
adc #$01
sta fixlan19 + 1
sta fixlan30 + 1
sta fixlan31 + 1
sta fixlan32 + 1
sta fixlan33 + 1
sta fixlan34 + 1
sta fixlan35 + 1
sta fixlan36 + 1
sta fixlan41 + 1
sta fixlan42 + 1
sta fixlan43 + 1
sta fixlan44 + 1
sta fixlan46 + 1
; Check packet length parity:
; - Even packet length -> carry set -> add 6 bytes
; - Odd packet length -> carry clear -> add 5 bytes
lda len
eor #$01
lsr
; The packet contains 3 extra words
lda len
adc #$05 ; Actually 5 or 6 depending on carry
fixup35:sta ethdata
lda len+1
adc #$00
fixup36:sta ethdata
; $C0s9: Save off all ethmir+1, ethdata+1, ethmgmt+1, and ethiar+5 mods
adc #$01
sta fixlan20 + 1
; Send the packet
; ---------------
; $C0sA: Save off all ethmcr, ethgpr, and ethrev mods
; $C0sB: Save off all ethmcr+1, ethgpr+1, and ethrev+1 mods
; None
; Write bytes from buffer
jsr adjustptr
: lda (ptr),y
fixup37:sta ethdata
iny
bne :-
inc ptr+1
dex
bpl :-
; $C0sC: Save off all ethctr, ethist, ethack, and ethercv mods
adc #$03 ; Because there were no a or b mods
sta fixlan24 + 1
sta fixlan25 + 1
sta fixlan38 + 1
; Odd packet length ?
lda len
lsr
bcc :+
; $C0sD: Save off all ethmsk, ethctr+1 mods
adc #$01
sta fixlan14 + 1
sta fixlan22 + 1
; Yes
lda #%00100000 ; ODD
bne :++ ; Always
; $C0sE: Save off all ethbsr mods
adc #$01
sta fixlan00 + 1
sta fixlan05 + 1
sta fixlan11 + 1
sta fixlan21 + 1
rts
; No
: lda #$00
fixup38:sta ethdata ; Fill byte
:
fixup39:sta ethdata ; Control byte
; Add packet to FIFO
lda #%11000000 ; ENQUEUE PACKET - transmit packet
fixup40:sta ethmmucr
clc
rts
.rodata
;---------------------------------------------------------------------
eth_driver_name:
.asciiz "LANceGS (91C96)"
exit:
rts
eth_driver_io_base = fixlan01+1
;---------------------------------------------------------------------
adjustptr:
lda len
ldx len+1
eor #$FF ; Two's complement part 1
tay
iny ; Two's complement part 2
sty reg
sec
lda bufaddr
sbc reg
sta ptr
lda bufaddr+1
sbc #$00
sta ptr+1
rts
; The contents of this file are subject to the Mozilla Public License
; Version 1.1 (the "License"); you may not use this file except in
; compliance with the License. You may obtain a copy of the License at
; http://www.mozilla.org/MPL/
;
; Software distributed under the License is distributed on an "AS IS"
; basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See the
; License for the specific language governing rights and limitations
; under the License.
;
; The Original Code is ip65.
;
; The Initial Developer of the Original Code is David Schmidt
; Portions created by the Initial Developer is Copyright (C) 2011
; All Rights Reserved.
; -- LICENSE END --
;---------------------------------------------------------------------

40
drivers/lancegs.s Normal file
View File

@ -0,0 +1,40 @@
; LANceGS driver
.import _lan91c96
.export eth = _lan91c96
.export eth_driver_name
.export eth_driver_io_base
.rodata
eth_driver_name:
.byte "LANceGS",0
.data
eth_driver_io_base:
.word $c0b0
; -- LICENSE FOR lancegs.s --
; The contents of this file are subject to the Mozilla Public License
; Version 1.1 (the "License"); you may not use this file except in
; compliance with the License. You may obtain a copy of the License at
; http://www.mozilla.org/MPL/
;
; Software distributed under the License is distributed on an "AS IS"
; basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See the
; License for the specific language governing rights and limitations
; under the License.
;
; The Original Code is ip65.
;
; The Initial Developer of the Original Code is Jonno Downes,
; jonno@jamtronix.com.
; Portions created by the Initial Developer are Copyright (C) 2009
; Jonno Downes. All Rights Reserved.
; -- LICENSE END --

39
drivers/rr-net.s
View File

@ -1,47 +1,22 @@
; RR-Net driver
.export cs_init
.import _cs8900a
.export cs_packet_page
.export cs_packet_data
.export cs_rxtx_data
.export cs_tx_cmd
.export cs_tx_len
.export eth = _cs8900a
.export eth_driver_name
.export eth_driver_io_base
IO_BASE = $de00
rr_ctl = IO_BASE+$01 ; address of 'control' port on Retro-Replay
cs_packet_page = IO_BASE+$02 ; address of 'packet page' port on RR-Net
cs_packet_data = IO_BASE+$04 ; address of 'packet data' port on RR-Net
cs_rxtx_data = IO_BASE+$08 ; address of 'recieve/transmit data' port on RR-Net
cs_tx_cmd = IO_BASE+$0c ; address of 'transmit command' port on RR-Net
cs_tx_len = IO_BASE+$0e ; address of 'transmission length' port on RR-Net
.code
; initialise Retro Replay so we can access the network adapter
; inputs: none
; outputs: none
cs_init:
lda rr_ctl
ora #1
sta rr_ctl
rts
.rodata
eth_driver_name:
.if IO_BASE=$de00
.byte "RR-NET",0
.else
.byte "64NIC+",0
.endif
.byte "RR-Net",0
.data
eth_driver_io_base:
.word IO_BASE
.word $de08

31
drivers/uthernet.s
View File

@ -1,35 +1,22 @@
; uthernet driver
; currently hardcoded to use slot 3 addresses only
; Uthernet driver
.export cs_init
.import _cs8900a
.export cs_packet_page
.export cs_packet_data
.export cs_rxtx_data
.export cs_tx_cmd
.export cs_tx_len
.export eth = _cs8900a
.export eth_driver_name
.export eth_driver_io_base
cs_rxtx_data = $c0b0 ; address of 'recieve/transmit data' port on Uthernet
cs_tx_cmd = $c0b4 ; address of 'transmit command' port on Uthernet
cs_tx_len = $c0b6 ; address of 'transmission length' port on Uthernet
cs_packet_page = $c0ba ; address of 'packet page' port on Uthernet
cs_packet_data = $c0bc ; address of 'packet data' port on Uthernet
.code
cs_init:
rts
.rodata
eth_driver_name:
.byte "UTHERNET",0
.byte "Uthernet",0
.data
eth_driver_io_base:
.word cs_rxtx_data
.word $c0b0

40
drivers/uthernet2.s Normal file
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@ -0,0 +1,40 @@
; Uthernet II driver
.import _w5100
.export eth = _w5100
.export eth_driver_name
.export eth_driver_io_base
.rodata
eth_driver_name:
.byte "Uthernet II",0
.data
eth_driver_io_base:
.word $c0b4
; -- LICENSE FOR uthernet2.s --
; The contents of this file are subject to the Mozilla Public License
; Version 1.1 (the "License"); you may not use this file except in
; compliance with the License. You may obtain a copy of the License at
; http://www.mozilla.org/MPL/
;
; Software distributed under the License is distributed on an "AS IS"
; basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See the
; License for the specific language governing rights and limitations
; under the License.
;
; The Original Code is ip65.
;
; The Initial Developer of the Original Code is Jonno Downes,
; jonno@jamtronix.com.
; Portions created by the Initial Developer are Copyright (C) 2009
; Jonno Downes. All Rights Reserved.
; -- LICENSE END --

35
drivers/vic20-rr-net.s
View File

@ -1,41 +1,22 @@
; RR-Net driver, as seen on a VIC-20 (i.e. using a Masquerade adapter)
.export cs_init
.import _cs8900a
.export cs_packet_page
.export cs_packet_data
.export cs_rxtx_data
.export cs_tx_cmd
.export cs_tx_len
.export eth = _cs8900a
.export eth_driver_name
.export eth_driver_io_base
rr_ctl = $9801 ; address of 'control' port on Retro-Replay
cs_packet_page = $9802 ; address of 'packet page' port on RR-Net
cs_packet_data = $9804 ; address of 'packet data' port on RR-Net
cs_rxtx_data = $9808 ; address of 'recieve/transmit data' port on RR-Net
cs_tx_cmd = $980c ; address of 'transmit command' port on RR-Net
cs_tx_len = $980e ; address of 'transmission length' port on RR-Net
.code
; initialise Retro Replay so we can access the network adapter
; inputs: none
; outputs: none
cs_init:
lda rr_ctl
ora #1
sta rr_ctl
rts
.rodata
eth_driver_name:
.asciiz "VIC20 RR-NET"
.asciiz "VIC20 RR-Net"
.data
eth_driver_io_base:
.word rr_ctl-1
.word $9808

226
drivers/w5100.i
View File

@ -1,226 +0,0 @@
; Common Registers
W5100_MR = $0000 ; Mode Register
W5100_GAR0 = $0001 ; Gateway Address Byte 0
W5100_GAR1 = $0002 ; Gateway Address Byte 1
W5100_GAR2 = $0003 ; Gateway Address Byte 2
W5100_GAR3 = $0004 ; Gateway Address Byte 3
W5100_SUBR0 = $0005 ; Subnet Mask Address 0
W5100_SUBR1 = $0006 ; Subnet Mask Address 1
W5100_SUBR2 = $0007 ; Subnet Mask Address 2
W5100_SUBR3 = $0008 ; Subnet Mask Address 3
W5100_SHAR0 = $0009 ; Local MAC Address 0
W5100_SHAR1 = $000A ; Local MAC Address 1
W5100_SHAR2 = $000B ; Local MAC Address 2
W5100_SHAR3 = $000C ; Local MAC Address 3
W5100_SHAR4 = $000D ; Local MAC Address 4
W5100_SHAR5 = $000E ; Local MAC Address 5
W5100_SIPR0 = $000F ; Source IP Address 0
W5100_SIPR1 = $0010 ; Source IP Address 0
W5100_SIPR2 = $0011 ; Source IP Address 0
W5100_SIPR3 = $0012 ; Source IP Address 0
W5100_IR = $0015 ; Interrupt
W5100_IMR = $0016 ; Interrupt Mask
W5100_RTR0 = $0017 ; Retry Time High Byte
W5100_RTR1 = $0018 ; Retry Time Low Byte
W5100_RCR = $0019 ; Retry Count
W5100_RMSR = $001A ; RX Memory Size (per socket)
W5100_TMSR = $001B ; TX Memory Size (per socket)
W5100_PATR0 = $001C ; PPPoE Auth Type High
W5100_PART1 = $001D ; PPPoE Auth Type Low
W5100_PTIMER = $0028 ; PPP LCP Request Timer
W5100_PMAGIC = $0029 ; PPP LCP Magic Number
W5100_UIPR0 = $002A ; Unreachable IP Address 0
W5100_UIPR1 = $002B ; Unreachable IP Address 1
W5100_UIPR2 = $002C ; Unreachable IP Address 2
W5100_UIPR3 = $002D ; Unreachable IP Address 3
W5100_UPORT0 = $002E ; Unreachable Port High
W5100_UPORT1 = $002F ; Unreachable Port Low
; Socket Registers
W5100_S0_BASE = $0400 ; Base for socket 0
W5100_S0_MR = $0400 ; Socket 0 Mode
W5100_S0_CR = $0401 ; Socket 0 Command
W5100_S0_IR = $0402 ; Socket 0 Interrupt
W5100_S0_SR = $0403 ; Socket 0 Status
W5100_S0_PORT0 = $0404 ; Socket 0 Source Port High
W5100_S0_PORT1 = $0405 ; Socket 0 Source Port Low
W5100_S0_DHAR0 = $0406 ; Socket 0 Dest Mac 0
W5100_S0_DHAR1 = $0407 ; Socket 0 Dest Mac 1
W5100_S0_DHAR2 = $0408 ; Socket 0 Dest Mac 2
W5100_S0_DHAR3 = $0409 ; Socket 0 Dest Mac 3
W5100_S0_DHAR4 = $040A ; Socket 0 Dest Mac 4
W5100_S0_DHAR5 = $040B ; Socket 0 Dest Mac 5
W5100_S0_DIPR0 = $040C ; Socket 0 Dest IP 0
W5100_S0_DIPR1 = $040D ; Socket 0 Dest IP 1
W5100_S0_DIPR2 = $040E ; Socket 0 Dest IP 2
W5100_S0_DIPR3 = $040F ; Socket 0 Dest IP 3
W5100_S0_DPORT0 = $0410 ; Socket 0 Dest Port High
W5100_S0_DPORT1 = $0411 ; Socket 0 Dest Port Low
W5100_S0_MSSR0 = $0412 ; Socket 0 Max Segment High
W5100_S0_MSSR1 = $0413 ; Socket 0 Max Segment Low
W5100_S0_PROTO = $0414 ; Socket 0 Protocol (Raw Mode)
W5100_S0_TOS = $0415 ; Socket 0 IP TOS
W5100_S0_TTL = $0416 ; Socket 0 IP TTL
W5100_S0_TX_FSR0 = $0420 ; Socket 0 TX Free Size High
W5100_S0_TX_FSR1 = $0421 ; Socket 0 TX Free Size Low
W5100_S0_TX_RD0 = $0422 ; Socket 0 TX Read Pointer High
W5100_S0_TX_RD1 = $0423 ; Socket 0 TX Read Pointer Low
W5100_S0_TX_WR0 = $0424 ; Socket 0 TX Write Pointer High
W5100_S0_TX_WR1 = $0425 ; Socket 0 TX Write Pointer Low
W5100_S0_RX_RSR0 = $0426 ; Socket 0 RX Received Size High
W5100_S0_RX_RSR1 = $0427 ; Socket 0 RX Received Size Low
W5100_S0_RX_RD0 = $0428 ; Socket 0 RX Read Pointer High
W5100_S0_RX_RD1 = $0429 ; Socket 0 RX Read Pointer Low
W5100_S1_BASE = $0500 ; Base for socket 1
W5100_S1_MR = $0500 ; Socket 1 Mode
W5100_S1_CR = $0501 ; Socket 1 Command
W5100_S1_IR = $0502 ; Socket 1 Interrupt
W5100_S1_SR = $0503 ; Socket 1 Status
W5100_S1_PORT0 = $0504 ; Socket 1 Source Port High
W5100_S1_PORT1 = $0505 ; Socket 1 Source Port Low
W5100_S1_DHAR0 = $0506 ; Socket 1 Dest Mac 0
W5100_S1_DHAR1 = $0507 ; Socket 1 Dest Mac 1
W5100_S1_DHAR2 = $0508 ; Socket 1 Dest Mac 2
W5100_S1_DHAR3 = $0509 ; Socket 1 Dest Mac 3
W5100_S1_DHAR4 = $050A ; Socket 1 Dest Mac 4
W5100_S1_DHAR5 = $050B ; Socket 1 Dest Mac 5
W5100_S1_DIPR0 = $050C ; Socket 1 Dest IP 0
W5100_S1_DIPR1 = $050D ; Socket 1 Dest IP 1
W5100_S1_DIPR2 = $050E ; Socket 1 Dest IP 2
W5100_S1_DIPR3 = $050F ; Socket 1 Dest IP 3
W5100_S1_DPORT0 = $0510 ; Socket 1 Dest Port High
W5100_S1_DPORT1 = $0511 ; Socket 1 Dest Port Low
W5100_S1_MSSR0 = $0512 ; Socket 1 Max Segment High
W5100_S1_MSSR1 = $0513 ; Socket 1 Max Segment Low
W5100_S1_PROTO = $0514 ; Socket 1 Protocol (Raw Mode)
W5100_S1_TOS = $0515 ; Socket 1 IP TOS
W5100_S1_TTL = $0516 ; Socket 1 IP TTL
W5100_S1_TX_FSR0 = $0520 ; Socket 1 TX Free Size High
W5100_S1_TX_FSR1 = $0521 ; Socket 1 TX Free Size Low
W5100_S1_TX_RD0 = $0522 ; Socket 1 TX Read Pointer High
W5100_S1_TX_RD1 = $0523 ; Socket 1 TX Read Pointer Low
W5100_S1_TX_WR0 = $0524 ; Socket 1 TX Write Pointer High
W5100_S1_TX_WR1 = $0525 ; Socket 1 TX Write Pointer Low
W5100_S1_RX_RSR0 = $0526 ; Socket 1 RX Received Size High
W5100_S1_RX_RSR1 = $0527 ; Socket 1 RX Received Size Low
W5100_S1_RX_RD0 = $0528 ; Socket 1 RX Read Pointer High
W5100_S1_RX_RD1 = $0529 ; Socket 1 RX Read Pointer Low
W5100_S2_BASE = $0600 ; Base for socket 2
W5100_S2_MR = $0600 ; Socket 2 Mode
W5100_S2_CR = $0601 ; Socket 2 Command
W5100_S2_IR = $0602 ; Socket 2 Interrupt
W5100_S2_SR = $0603 ; Socket 2 Status
W5100_S2_PORT0 = $0604 ; Socket 2 Source Port High
W5100_S2_PORT1 = $0605 ; Socket 2 Source Port Low
W5100_S2_DHAR0 = $0606 ; Socket 2 Dest Mac 0
W5100_S2_DHAR1 = $0607 ; Socket 2 Dest Mac 1
W5100_S2_DHAR2 = $0608 ; Socket 2 Dest Mac 2
W5100_S2_DHAR3 = $0609 ; Socket 2 Dest Mac 3
W5100_S2_DHAR4 = $060A ; Socket 2 Dest Mac 4
W5100_S2_DHAR5 = $060B ; Socket 2 Dest Mac 5
W5100_S2_DIPR0 = $060C ; Socket 2 Dest IP 0
W5100_S2_DIPR1 = $060D ; Socket 2 Dest IP 1
W5100_S2_DIPR2 = $060E ; Socket 2 Dest IP 2
W5100_S2_DIPR3 = $060F ; Socket 2 Dest IP 3
W5100_S2_DPORT0 = $0610 ; Socket 2 Dest Port High
W5100_S2_DPORT1 = $0611 ; Socket 2 Dest Port Low
W5100_S2_MSSR0 = $0612 ; Socket 2 Max Segment High
W5100_S2_MSSR1 = $0613 ; Socket 2 Max Segment Low
W5100_S2_PROTO = $0614 ; Socket 2 Protocol (Raw Mode)
W5100_S2_TOS = $0615 ; Socket 2 IP TOS
W5100_S2_TTL = $0616 ; Socket 2 IP TTL
W5100_S2_TX_FSR0 = $0620 ; Socket 2 TX Free Size High
W5100_S2_TX_FSR1 = $0621 ; Socket 2 TX Free Size Low
W5100_S2_TX_RD0 = $0622 ; Socket 2 TX Read Pointer High
W5100_S2_TX_RD1 = $0623 ; Socket 2 TX Read Pointer Low
W5100_S2_TX_WR0 = $0624 ; Socket 2 TX Write Pointer High
W5100_S2_TX_WR1 = $0625 ; Socket 2 TX Write Pointer Low
W5100_S2_RX_RSR0 = $0626 ; Socket 2 RX Received Size High
W5100_S2_RX_RSR1 = $0627 ; Socket 2 RX Received Size Low
W5100_S2_RX_RD0 = $0628 ; Socket 2 RX Read Pointer High
W5100_S2_RX_RD1 = $0629 ; Socket 2 RX Read Pointer Low
W5100_S3_BASE = $0700 ; Base for socket 3
W5100_S3_MR = $0700 ; Socket 3 Mode
W5100_S3_CR = $0701 ; Socket 3 Command
W5100_S3_IR = $0702 ; Socket 3 Interrupt
W5100_S3_SR = $0703 ; Socket 3 Status
W5100_S3_PORT0 = $0704 ; Socket 3 Source Port High
W5100_S3_PORT1 = $0705 ; Socket 3 Source Port Low
W5100_S3_DHAR0 = $0706 ; Socket 3 Dest Mac 0
W5100_S3_DHAR1 = $0707 ; Socket 3 Dest Mac 1
W5100_S3_DHAR2 = $0708 ; Socket 3 Dest Mac 2
W5100_S3_DHAR3 = $0709 ; Socket 3 Dest Mac 3
W5100_S3_DHAR4 = $070A ; Socket 3 Dest Mac 4
W5100_S3_DHAR5 = $070B ; Socket 3 Dest Mac 5
W5100_S3_DIPR0 = $070C ; Socket 3 Dest IP 0
W5100_S3_DIPR1 = $070D ; Socket 3 Dest IP 1
W5100_S3_DIPR2 = $070E ; Socket 3 Dest IP 2
W5100_S3_DIPR3 = $070F ; Socket 3 Dest IP 3
W5100_S3_DPORT0 = $0710 ; Socket 3 Dest Port High
W5100_S3_DPORT1 = $0711 ; Socket 3 Dest Port Low
W5100_S3_MSSR0 = $0712 ; Socket 3 Max Segment High
W5100_S3_MSSR1 = $0713 ; Socket 3 Max Segment Low
W5100_S3_PROTO = $0714 ; Socket 3 Protocol (Raw Mode)
W5100_S3_TOS = $0715 ; Socket 3 IP TOS
W5100_S3_TTL = $0716 ; Socket 3 IP TTL
W5100_S3_TX_FSR0 = $0720 ; Socket 3 TX Free Size High
W5100_S3_TX_FSR1 = $0721 ; Socket 3 TX Free Size Low
W5100_S3_TX_RD0 = $0722 ; Socket 3 TX Read Pointer High
W5100_S3_TX_RD1 = $0723 ; Socket 3 TX Read Pointer Low
W5100_S3_TX_WR0 = $0724 ; Socket 3 TX Write Pointer High
W5100_S3_TX_WR1 = $0725 ; Socket 3 TX Write Pointer Low
W5100_S3_RX_RSR0 = $0726 ; Socket 3 RX Received Size High
W5100_S3_RX_RSR1 = $0727 ; Socket 3 RX Received Size Low
W5100_S3_RX_RD0 = $0728 ; Socket 3 RX Read Pointer High
W5100_S3_RX_RD1 = $0729 ; Socket 3 RX Read Pointer Low
; Commands
W5100_CMD_OPEN = $01
W5100_CMD_LISTEN = $02
W5100_CMD_CONNECT = $04
W5100_CMD_DISCONNECT = $08
W5100_CMD_CLOSE = $10
W5100_CMD_SEND = $20
W5100_CMD_SEND_MAC = $21
W5100_CMD_SEND_KEEP = $22
W5100_CMD_RECV = $40
; Modes
W5100_MODE_CLOSED = $00
W5100_MODE_TCP = $01
W5100_MODE_UDP = $02
W5100_MODE_IP_RAW = $03
W5100_MODE_MAC_RAW = $04
W5100_MODE_PPPOE = $05
; Status
W5100_STATUS_SOCK_CLOSED = $00
W5100_STATUS_SOCK_INIT = $13
W5100_STATUS_SOCK_LISTEN = $14
W5100_STATUS_SOCK_SYNSENT = $15
W5100_STATUS_SOCK_SYNRECV = $16
W5100_STATUS_SOCK_ESTABLISHED = $17
W5100_STATUS_SOCK_FIN_WAIT = $18
W5100_STATUS_SOCK_CLOSING = $1A
W5100_STATUS_SOCK_TIME_WAIT = $1B
W5100_STATUS_SOCK_CLOSE_WAIT = $1C
W5100_STATUS_SOCK_LAST_ACK = $1D
W5100_STATUS_SOCK_UDP = $22
W5100_STATUS_SOCK_IPRAW = $32
W5100_STATUS_SOCK_MACRAW = $42
W5100_STATUS_SOCK_PPPOE = $5F

1492
drivers/w5100.s
View File

File diff suppressed because it is too large Load Diff

71
ip65/Makefile
View File

@ -1,66 +1,45 @@
AS=ca65
LD=ld65
AFLAGS=
# ip65.lib : minimal IP stack (UDP only)
# ip65_tcp.lib : full featured TCP/IP stack
# ip65_wiznet.lib : hybrid stack for use with the w5100 chip : UDP,ICMP & ARP is done on host, TCP is on w5100
%.o: %.c
$(CC) -c $(CFLAGS) $<
all: ip65.lib ip65_tcp.lib
%.o: %.s
$(AS) $(AFLAGS) $<
ca65 $<
ETHOBJS=\
copymem.o \
config.o \
timer.o \
eth.o \
%_tcp.o: %.s
ca65 -DTCP -o $@ $<
IP65OBJS=\
arithmetic.o\
arp.o \
ip65.o \
printf.o \
cifs.o \
config.o \
copymem.o \
debug.o \
http.o \
httpd.o \
dhcp.o \
dns.o \
dottedquad.o \
output_buffer.o\
eth.o \
http.o \
httpd.o \
ip65.o \
tftp.o \
timer.o \
output_buffer.o\
parser.o \
printf.o \
sntp.o \
string_utils.o \
telnet.o \
url.o \
arithmetic.o\
ip.o \
sntp.o \
icmp.o \
cifs.o \
udp.o
udp.o \
url.o
all: ip65.lib ip65_tcp.lib ip65_wiznet.lib
ip65.lib: $(IP65OBJS) ip.o icmp.o
ar65 a $@ $^
ip65.lib: $(ETHOBJS)
$(AS) $(AFLAGS) ip.s
$(AS) $(AFLAGS) icmp.s
ar65 a ip65.lib $(ETHOBJS)
ip65_tcp.lib: tcp.o $(ETHOBJS) tcp.s
$(AS) $(AFLAGS) ip.s -DTCP
$(AS) $(AFLAGS) icmp.s -DTCP
ar65 a ip65_tcp.lib $(ETHOBJS) tcp.o
ip65_wiznet.lib: $(ETHOBJS)
$(AS) $(AFLAGS) ip.s
$(AS) $(AFLAGS) icmp.s -DTCP
ar65 a ip65_wiznet.lib $(ETHOBJS)
ip65_tcp.lib: $(IP65OBJS) ip_tcp.o icmp_tcp.o tcp.o
ar65 a $@ $^
clean:
-rm -f *.o
-rm -f ip65.lib
-rm -f ip65_tcp.lib
-rm -f ip65_wiznet.lib
distclean: clean
-rm -f *~
-rm -f *.lib

9
ip65/config.s
View File

@ -8,13 +8,10 @@
.export cfg_netmask
.export cfg_gateway
.export cfg_dns
.export cfg_tftp_server
.export cfg_get_configuration_ptr
.export dhcp_server
.import copymem
.importzp copy_src
.importzp copy_dest
.export cfg_tftp_server
.export cfg_get_configuration_ptr
.data

129
test/Makefile
View File

@ -7,106 +7,78 @@
# Build for WIZnet W5100 based devices:
# make eth=wn
CC = cl65
AS = ca65
LD = ld65
CFLAGS = -Oirs -t $(TARGET)
AFLAGS =
ifeq ($(eth),sm)
C64DRIVERLIB = ../drivers/c64eth64.lib
A2DRIVERLIB = ../drivers/a2lancegs.lib
else ifeq ($(eth),wn)
A2DRIVERLIB = ../drivers/a2uther2.lib
else
C64DRIVERLIB = ../drivers/c64rrnet.lib
A2DRIVERLIB = ../drivers/a2uther.lib
VICDRIVERLIB = ../drivers/vic20rrnet.lib
endif
IP65LIB = ../ip65/ip65.lib
IP65TCPLIB = ../ip65/ip65_tcp.lib
UDP =\
dns \
dottedquad \
parsequerystring \
sntp \
tftp
INCFILES = \
../inc/common.i\
../inc/commonprint.i\
../inc/net.i\
TCP =\
cifs \
geturl \
httpd \
parser \
ping \
tcp
all: prg bin
all: $(UDP) $(TCP)
.PHONY: $(UDP) $(TCP)
prg: \
ip65 \
drivers \
cifs_tcp.prg \
dns.prg \
dottedquad.prg \
geturl_tcp.prg \
httpd_tcp.prg \
parsequerystring.prg \
parser_tcp.prg \
ping_tcp.prg \
sntp.prg \
tcp_tcp.prg \
tftp.prg
$(addsuffix .prg,$(UDP)): IP65LIB = ../ip65/ip65.lib
$(addsuffix .prg,$(TCP)): IP65LIB = ../ip65/ip65_tcp.lib
bin: \
ip65 \
drivers \
cifs_tcp.bin \
dns.bin \
dottedquad.bin \
geturl_tcp.bin \
httpd_tcp.bin \
parsequerystring.bin \
parser_tcp.bin \
ping_tcp.bin \
sntp.bin \
tcp_tcp.bin \
tftp.bin
$(addsuffix .bin,$(UDP)): IP65LIB = ../ip65/ip65.lib
$(addsuffix .bin,$(TCP)): IP65LIB = ../ip65/ip65_tcp.lib
vicprg: \
ip65 \
drivers \
cifs_tcp.vicprg \
dns.vicprg \
dottedquad.vicprg \
geturl_tcp.vicprg \
httpd_tcp.vicprg \
parsequerystring.vicprg \
parser_tcp.vicprg \
ping_tcp.vicprg \
sntp.vicprg \
tcp_tcp.vicprg \
tftp.vicprg
$(addsuffix .vicprg,$(UDP)): IP65LIB = ../ip65/ip65.lib
$(addsuffix .vicprg,$(TCP)): IP65LIB = ../ip65/ip65_tcp.lib
ip65:
make -C ../ip65 all
$(foreach pgm,$(UDP) $(TCP),$(eval $(pgm): $(pgm).prg $(pgm).bin $(pgm).vicprg))
drivers:
make -C ../drivers all
INCFILES =\
../inc/common.i \
../inc/commonprint.i \
../inc/net.i
prg: $(addsuffix .prg,$(UDP) $(TCP))
bin: $(addsuffix .bin,$(UDP) $(TCP))
vicprg: $(addsuffix .vicprg,$(UDP) $(TCP))
d64: ip65.d64
dsk: ip65.dsk
ip65:
make -C ../ip65
drivers:
make -C ../drivers
%.o: %.s
$(AS) $(AFLAGS) $<
ca65 $<
%.prg: %.o $(IP65LIB) $(C64DRIVERLIB) $(INCFILES)
$(LD) -o $*.prg -t c64 -m $*.c64.map -vm $< $(IP65LIB) $(C64DRIVERLIB) c64.lib
%.prg: %.o ip65 drivers $(INCFILES)
ld65 -o $*.prg -C c64.cfg -m $*.c64.map -vm $< $(IP65LIB) $(C64DRIVERLIB) c64.lib
%_tcp.prg: %.o $(IP65TCPLIB) $(C64DRIVERLIB) $(INCFILES)
$(LD) -o $(subst _tcp,,$*).prg -t c64 -m $(subst _tcp,,$*).c64.map -vm $< $(IP65TCPLIB) $(C64DRIVERLIB) c64.lib
%.bin: %.o ip65 drivers $(INCFILES)
ld65 -o $*.bin -C apple2.cfg -m $*.a2.map -vm $< $(IP65LIB) $(A2DRIVERLIB) apple2.lib
%.bin: %.o $(IP65LIB) $(A2DRIVERLIB) $(INCFILES)
$(LD) -o $*.bin -t apple2 -m $*.a2.map -vm $< $(IP65LIB) $(A2DRIVERLIB) apple2.lib
%_tcp.bin: %.o $(IP65TCPLIB) $(A2DRIVERLIB) $(INCFILES)
$(LD) -o $(subst _tcp,,$*).bin -t apple2 -m $(subst _tcp,,$*).a2.map -vm $< $(IP65TCPLIB) $(A2DRIVERLIB) apple2.lib
%.vicprg: %.o $(IP65LIB) $(VICDRIVERLIB) $(INCFILES)
$(LD) -o $*.vicprg -C vic20-32k.cfg -m $*.vic.map -vm $< $(IP65LIB) $(VICDRIVERLIB) vic20.lib
%_tcp.vicprg: %.o $(IP65TCPLIB) $(VICDRIVERLIB) $(INCFILES)
$(LD) -o $(subst _tcp,,$*).vicprg -C vic20-32k.cfg -m $(subst _tcp,,$*).vic.map -vm $< $(IP65TCPLIB) $(VICDRIVERLIB) vic20.lib
%.vicprg: %.o ip65 drivers $(INCFILES)
ld65 -o $*.vicprg -C vic20-32k.cfg -m $*.vic.map -vm $< $(IP65LIB) $(VICDRIVERLIB) vic20.lib
ip65.d64: prg
$(C1541) -format ip65,00 d64 $@
@ -133,8 +105,7 @@ ip65.dsk: bin
java -jar $(AC) -cc65 $@ tftp bin 0 < tftp.bin
clean:
-rm -f *.o *.prg *.bin *.vicprg *.map
make -C ../ip65 clean
make -C ../drivers clean
-rm -f *.prg *.bin *.vicprg *.map
-rm -f ip65.d64 ip65.dsk
distclean: clean
-rm -f *~