mirror of
https://github.com/bobbimanners/emailler.git
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4577c2ab19
So far the base address of the Ethernet chip was a general property of all Ethernet drivers. It served two purposes: 1. Allowing to use a single Ethernet driver for a certain Ethernet chip, no matter what machine was connected to the chip. 2. Allowing use an Ethernet card in all Apple II slots. However, we now use customized Ethernet drivers for the individual machines so 1.) isn't relevant anymore. In fact one wants to omit the overhead of a runtime-adjustable base address where it isn't needed. So only the Apple II slots are left. But this should rather be a driver-internal approach then. We should just hand the driver the slot number the user wants to use and have the driver do its thing. Independently from the aspect if the driver parameter is a base address or a slot number the parameter handling was changed too. For asm programs there was so far a specific init function to be called prior to the main init function if it was desired to chnage the parameter default. This was done to keep the main init function backward compatible. But now that the parameter (now the slot number) is only used on the Apple II anyhow it seems reasonable to drop the specific init function again and just provide the parameter to the main init function. All C64-only user code can stay as-is. Only Apple II user code needs to by adjusted. Please note that this change only affects asm programs, C programs always used a single init function with the Apple II slot number as parameter.
534 lines
11 KiB
ArmAsm
534 lines
11 KiB
ArmAsm
;
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; Copyright (c) 2013, Oliver Schmidt
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; All rights reserved.
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;
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; Redistribution and use in source and binary forms, with or without
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; modification, are permitted provided that the following conditions
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; are met:
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; 1. Redistributions of source code must retain the above copyright
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; notice, this list of conditions and the following disclaimer.
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; 2. Redistributions in binary form must reproduce the above copyright
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; notice, this list of conditions and the following disclaimer in the
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; documentation and/or other materials provided with the distribution.
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; 3. Neither the name of the Institute nor the names of its contributors
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; may be used to endorse or promote products derived from this software
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; without specific prior written permission.
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;
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; THIS SOFTWARE IS PROVIDED BY THE INSTITUTE AND CONTRIBUTORS ``AS IS'' AND
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; ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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; ARE DISCLAIMED. IN NO EVENT SHALL THE INSTITUTE OR CONTRIBUTORS BE LIABLE
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; FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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; DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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; OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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; HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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; LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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; OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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; SUCH DAMAGE.
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;
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; This file is part of the Contiki operating system.
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;
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; Author: Oliver Schmidt <ol.sc@web.de>
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;
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;---------------------------------------------------------------------
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.macpack module
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module_header _w5100
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; Driver signature
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.byte $65, $74, $68 ; "eth"
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.byte $01 ; Ethernet driver API version number
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; Ethernet address
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mac: .byte $00, $08, $DC ; OUI of WIZnet
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.byte $11, $11, $11
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; Buffer attributes
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bufaddr:.res 2 ; Address
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bufsize:.res 2 ; Size
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; Jump table.
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jmp init
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jmp poll
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jmp send
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jmp exit
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;---------------------------------------------------------------------
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.if DYN_DRV
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.zeropage
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sp: .res 2 ; Stack pointer (Do not trash !)
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reg: .res 2 ; Pointer Register content
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ptr: .res 2 ; Indirect addressing pointer
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len: .res 2 ; Data length
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cnt: .res 2 ; Data length counter
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adv: .res 2 ; Data pointer advancement
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dir: .res 1 ; Transfer direction
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bas: .res 1 ; Socket 0 Base Address (hibyte)
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lim: .res 1 ; Socket 0 memory limit (hibyte)
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tmp: .res 1 ; Temporary value
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.else
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.include "zeropage.inc"
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reg := ptr1 ; Pointer Register content
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ptr := ptr2 ; Indirect addressing pointer
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len := ptr3 ; Data length
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cnt := ptr4 ; Data length counter
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adv := sreg ; Data pointer advancement
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dir := tmp1 ; Transfer direction
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bas := tmp2 ; Socket 0 Base Address (hibyte)
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lim := tmp3 ; Socket 0 memory limit (hibyte)
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tmp := tmp4 ; Temporary value
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.endif
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;---------------------------------------------------------------------
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.rodata
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fixup: .byte fixup02-fixup01, fixup03-fixup02, fixup04-fixup03
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.byte fixup05-fixup04, fixup06-fixup05, fixup07-fixup06
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.byte fixup08-fixup07, fixup09-fixup08, fixup10-fixup09
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.byte fixup11-fixup10, fixup12-fixup11, fixup13-fixup12
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.byte fixup14-fixup13, fixup15-fixup14, fixup16-fixup15
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.byte fixup17-fixup16, fixup18-fixup17, fixup19-fixup18
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.byte fixup20-fixup19, fixup21-fixup20, fixup22-fixup21
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.byte fixup23-fixup22, fixup24-fixup23, fixup25-fixup24
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.byte fixup26-fixup25, fixup27-fixup26, fixup28-fixup27
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.byte fixup29-fixup28, fixup30-fixup29, fixup31-fixup30
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.byte fixup32-fixup31
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fixups = * - fixup
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;---------------------------------------------------------------------
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; The addresses are fixed up at runtime
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mode := $C084
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addr := $C085
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data := $C087
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;---------------------------------------------------------------------
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.data
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init:
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; Convert slot number to slot I/O offset
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asl
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asl
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asl
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asl
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sta reg
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; Start with first fixup location
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lda #<(fixup01+1)
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ldx #>(fixup01+1)
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sta ptr
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stx ptr+1
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ldx #$FF
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ldy #$00
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; Fixup address at location
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: lda (ptr),y
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and #%10001111 ; Allow for re-init
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ora reg
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sta (ptr),y
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; Advance to next fixup location
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inx
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cpx #fixups
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bcs :+
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lda ptr
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clc
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adc fixup,x
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sta ptr
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bcc :-
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inc ptr+1
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bcs :- ; Always
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:
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; Indirect Bus I/F mode, Address Auto-Increment
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fixup01:lda mode
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ora #$03
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fixup02:sta mode
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; Retry Time-value Register: = 2000 ?
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ldx #$00 ; Hibyte
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ldy #$17 ; Lobyte
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jsr set_addr
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lda #$07^$D0
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fixup03:eor data
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fixup04:eor data
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beq :+
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sec
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rts
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; Check for W5100 shared access
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; RX Memory Size Register: Assign 4+2+1+1KB to socket 0 to 3 ?
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: ; ldx #$00 ; Hibyte
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ldy #$1A ; Lobyte
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jsr set_addr
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fixup05:lda data
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cmp #$06
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beq :+++
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; S/W Reset
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lda #$80
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fixup06:sta mode
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:
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fixup07:lda mode
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bmi :-
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; Indirect Bus I/F mode, Address Auto-Increment, Ping Block
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lda #$13
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fixup08:sta mode
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; Source Hardware Address Register: MAC Address
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ldx #$00 ; Hibyte
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ldy #$09 ; Lobyte
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jsr set_addr
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: lda mac,x
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fixup09:sta data
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inx
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cpx #$06
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bcc :-
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; RX Memory Size Register: Assign 4KB each to socket 0 and 1
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; TX Memory Size Register: Assign 4KB each to socket 0 and 1
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ldx #$00 ; Hibyte
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ldy #$1A ; Lobyte
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jsr set_addr
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lda #$0A
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fixup10:sta data
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fixup11:sta data
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; MAC Address: Source Hardware Address Register
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: ; ldx #$00 ; Hibyte
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ldy #$09 ; Lobyte
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jsr set_addr
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:
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fixup12:lda data
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sta mac,x
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inx
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cpx #$06
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bcc :-
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; Socket 0 Mode Register: MACRAW, MAC Filter
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; Socket 0 Command Register: OPEN
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ldy #$00
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jsr set_addrsocket0
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lda #$44
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fixup13:sta data
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lda #$01
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fixup14:sta data
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tya
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tax
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clc
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rts
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;---------------------------------------------------------------------
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poll:
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; Check for completion of previous command
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; Socket 0 Command Register: = 0 ?
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jsr set_addrcmdreg0
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fixup15:lda data
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beq :++
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; No data available
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lda #$00
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: tax
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sec
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rts
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; Socket 0 RX Received Size Register: != 0 ?
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: ldy #$26 ; Socket RX Received Size Register
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jsr set_addrsocket0
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fixup16:lda data ; Hibyte
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fixup17:ora data ; Lobyte
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beq :--
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; Process the incoming data
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; -------------------------
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; Set parameters for receiving data
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lda #>$6000 ; Socket 0 RX Base Address
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ldx #$00 ; Read
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jsr set_parameters
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; ldy #$28 ; Socket RX Read Pointer Register
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; jsr set_addrsocket0
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; Calculate and set physical address
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jsr set_addrphysical
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; Move physical address shadow to $F000-$FFFF
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ora #>$F000
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tax
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; Read MAC raw 2byte packet size header
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jsr get_datacheckaddr ; Hibyte
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sta adv+1
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jsr get_datacheckaddr ; Lobyte
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sta adv
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; Subtract 2byte header and set length
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sec
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sbc #<$0002
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sta len
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sta cnt
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lda adv+1
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sbc #>$0002
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sta len+1
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sta cnt+1
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; Is bufsize < length ?
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lda bufsize
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cmp len
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lda bufsize+1
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sbc len+1
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bcs :+
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; Set data length = 0 and skip read
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lda #$00
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sta len
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sta len+1
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beq :++ ; Always
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; Read data
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: jsr mov_data
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; Set parameters for common code
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: lda #$40 ; RECV
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ldy #$28 ; Socket 0 RX Read Pointer Register
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; Advance pointer register
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common: jsr set_addrsocket0
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tay ; Save command
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clc
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lda reg
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adc adv
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tax
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lda reg+1
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adc adv+1
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fixup18:sta data ; Hibyte
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fixup19:stx data ; Lobyte
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; Set command register
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tya ; Restore command
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jsr set_addrcmdreg0
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fixup20:sta data
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; Return data length (will be ignored for send)
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lda len
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ldx len+1
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clc
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rts
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;---------------------------------------------------------------------
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send:
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; Save data length
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sta len
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stx len+1
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sta cnt
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stx cnt+1
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sta adv
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stx adv+1
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; Set parameters for transmitting data
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lda #>$4000 ; Socket 0 TX Base Address
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ldx #$01 ; Write
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jsr set_parameters
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; Wait for completion of previous command
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; Socket 0 Command Register: = 0 ?
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: jsr set_addrcmdreg0
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fixup21:lda data
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bne :-
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; Socket 0 TX Free Size Register: < length ?
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: ldy #$20 ; Socket TX Free Size Register
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jsr set_addrsocket0
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fixup22:lda data ; Hibyte
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fixup23:ldx data ; Lobyte
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cpx len
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sbc len+1
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bcc :-
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; Send the data
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; -------------
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ldy #$24 ; Socket TX Write Pointer Register
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jsr set_addrsocket0
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; Calculate and set pyhsical address
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jsr set_addrphysical
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; Write data
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jsr mov_data
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; Set parameters for common code
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lda #$20 ; SEND
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ldy #$24 ; Socket TX Write Pointer Register
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bne common ; Always
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;---------------------------------------------------------------------
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exit:
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rts
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;---------------------------------------------------------------------
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set_addrphysical:
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fixup24:lda data ; Hibyte
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fixup25:ldy data ; Lobyte
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sty reg
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sta reg+1
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and #>$0FFF ; Socket Mask Address (hibyte)
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ora bas ; Socket Base Address (hibyte)
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tax
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set_addr:
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fixup26:stx addr ; Hibyte
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fixup27:sty addr+1 ; Lobyte
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rts
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set_addrcmdreg0:
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ldy #$01 ; Socket Command Register
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set_addrsocket0:
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ldx #>$0400 ; Socket 0 register base address
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bne set_addr ; Always
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set_addrbase:
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ldx bas ; Socket Base Address (hibyte)
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ldy #<$0000 ; Socket Base Address (lobyte)
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beq set_addr ; Always
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get_datacheckaddr:
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fixup28:lda data
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iny ; Physical address shadow (lobyte)
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bne :+
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inx ; Physical address shadow (hibyte)
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beq set_addrbase
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: rts
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;---------------------------------------------------------------------
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set_parameters:
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; Setup variables in zero page
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sta bas ; Socket Base Address
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clc
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adc #>$1000 ; Socket memory size
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sta lim ; Socket memory limit
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stx dir ; Transfer direction
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; Set indirect addressing pointer
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lda bufaddr
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ldx bufaddr+1
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sta ptr
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stx ptr+1
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rts
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;---------------------------------------------------------------------
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mov_data:
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; Calculate highest R/W address allowing
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; to R/W without address wraparound
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sec
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lda #<$0000 ; Socket memory limit (lobyte)
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sbc len
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tay
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lda lim ; Socket memory limit (hibyte)
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sbc len+1
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tax
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tya
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; R/W without address wraparound possible because
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; highest R/W address > actual R/W address ?
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; sec
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fixup29:sbc addr+1 ; Lobyte
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tay
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txa
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fixup30:sbc addr ; Hibyte
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tax
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tya
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bcs :+
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; Calculate length of first chunk
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; clc
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adc len
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sta cnt
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tay
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txa
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adc len+1
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sta cnt+1
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tax
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tya
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; R/W first chunk
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jsr rw_data
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; Wraparound R/W address
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jsr set_addrbase
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; Set buffer pointer for second chunk
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clc
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lda bufaddr
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adc cnt
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sta ptr
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lda bufaddr+1
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adc cnt+1
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sta ptr+1
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; Calculate length of second chunk
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sec
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lda len
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sbc cnt
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sta cnt
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lda len+1
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sbc cnt+1
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sta cnt+1
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; Get length of (second) chunk
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: lda cnt
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ldx cnt+1
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; R/W (second) chunk
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rw_data:eor #$FF ; Two's complement part 1
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tay
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iny ; Two's complement part 2
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sty tmp
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sec
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lda ptr
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sbc tmp
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sta ptr
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lda ptr+1
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sbc #$00
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sta ptr+1
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lda dir ; Transfer direction
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bne :++
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; Read data
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:
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fixup31:lda data
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sta (ptr),y
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iny
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bne :-
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inc ptr+1
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dex
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bpl :-
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rts
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; Write data
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: lda (ptr),y
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fixup32:sta data
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iny
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bne :-
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inc ptr+1
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dex
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bpl :-
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rts
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;---------------------------------------------------------------------
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