From f9b604c5bab4c9ffcfb6a28ff6ec51c0e0850884 Mon Sep 17 00:00:00 2001
From: Michel Pollet <buserror@gmail.com>
Date: Mon, 12 Feb 2024 16:55:37 +0000
Subject: [PATCH] cpu: Sprinkled a few cycles

Missing cycles were a problem for timing critical disk read/writes

Signed-off-by: Michel Pollet <buserror@gmail.com>
---
 src/mii_65c02.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/src/mii_65c02.c b/src/mii_65c02.c
index 74bb4f0..db25b51 100644
--- a/src/mii_65c02.c
+++ b/src/mii_65c02.c
@@ -380,6 +380,7 @@ next_instruction:
 		}	break;
 		case 0x4A:
 		{ // LSR
+			_FETCH(cpu->PC);
 			cpu->P.C = !!(cpu->A & 0x01);
 			cpu->A >>= 1;
 			_NZ(cpu->A);
@@ -534,7 +535,7 @@ next_instruction:
 		case 0x85: case 0x95: case 0x8D: case 0x9D:
 		case 0x99: case 0x81: case 0x91: case 0x92:
 		{ // STA
-			cpu->_D = cpu->A;
+			cpu->_D = cpu->A;cpu->cycle++;
 		}	break;
 		case 0x86: case 0x96: case 0x8E:
 		{ // STX