2021-06-01 19:21:33 +00:00
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package prog8tests
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2021-07-11 17:04:53 +00:00
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import org.junit.jupiter.api.TestInstance
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import org.junit.jupiter.api.Test
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2021-07-11 16:18:27 +00:00
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import kotlin.test.*
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import prog8tests.helpers.*
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2021-06-01 19:21:33 +00:00
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import prog8.ast.Module
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import prog8.ast.Program
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import prog8.ast.base.DataType
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import prog8.ast.base.ParentSentinel
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import prog8.ast.base.Position
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import prog8.ast.base.VarDeclType
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import prog8.ast.expressions.*
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import prog8.ast.statements.*
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import prog8.compiler.target.C64Target
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2021-07-11 17:04:53 +00:00
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2021-07-11 16:18:27 +00:00
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@TestInstance(TestInstance.Lifecycle.PER_CLASS)
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2021-06-01 19:21:33 +00:00
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class TestMemory {
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2021-06-01 19:21:33 +00:00
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@Test
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fun testInValidRamC64_memory_addresses() {
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var memexpr = NumericLiteralValue.optimalInteger(0x0000, Position.DUMMY)
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var target = AssignTarget(null, null, DirectMemoryWrite(memexpr, Position.DUMMY), Position.DUMMY)
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2021-08-01 20:47:11 +00:00
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val program = Program("test", DummyFunctions, DummyMemsizer)
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2021-06-01 19:21:33 +00:00
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assertTrue(C64Target.isInRegularRAM(target, program))
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memexpr = NumericLiteralValue.optimalInteger(0x1000, Position.DUMMY)
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target = AssignTarget(null, null, DirectMemoryWrite(memexpr, Position.DUMMY), Position.DUMMY)
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assertTrue(C64Target.isInRegularRAM(target, program))
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memexpr = NumericLiteralValue.optimalInteger(0x9fff, Position.DUMMY)
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target = AssignTarget(null, null, DirectMemoryWrite(memexpr, Position.DUMMY), Position.DUMMY)
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assertTrue(C64Target.isInRegularRAM(target, program))
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memexpr = NumericLiteralValue.optimalInteger(0xc000, Position.DUMMY)
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target = AssignTarget(null, null, DirectMemoryWrite(memexpr, Position.DUMMY), Position.DUMMY)
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assertTrue(C64Target.isInRegularRAM(target, program))
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memexpr = NumericLiteralValue.optimalInteger(0xcfff, Position.DUMMY)
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target = AssignTarget(null, null, DirectMemoryWrite(memexpr, Position.DUMMY), Position.DUMMY)
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assertTrue(C64Target.isInRegularRAM(target, program))
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}
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@Test
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fun testNotInValidRamC64_memory_addresses() {
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var memexpr = NumericLiteralValue.optimalInteger(0xa000, Position.DUMMY)
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var target = AssignTarget(null, null, DirectMemoryWrite(memexpr, Position.DUMMY), Position.DUMMY)
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val program = Program("test", DummyFunctions, DummyMemsizer)
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assertFalse(C64Target.isInRegularRAM(target, program))
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memexpr = NumericLiteralValue.optimalInteger(0xafff, Position.DUMMY)
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target = AssignTarget(null, null, DirectMemoryWrite(memexpr, Position.DUMMY), Position.DUMMY)
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assertFalse(C64Target.isInRegularRAM(target, program))
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memexpr = NumericLiteralValue.optimalInteger(0xd000, Position.DUMMY)
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target = AssignTarget(null, null, DirectMemoryWrite(memexpr, Position.DUMMY), Position.DUMMY)
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assertFalse(C64Target.isInRegularRAM(target, program))
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memexpr = NumericLiteralValue.optimalInteger(0xffff, Position.DUMMY)
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target = AssignTarget(null, null, DirectMemoryWrite(memexpr, Position.DUMMY), Position.DUMMY)
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assertFalse(C64Target.isInRegularRAM(target, program))
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}
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@Test
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fun testInValidRamC64_memory_identifiers() {
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var target = createTestProgramForMemoryRefViaVar(0x1000, VarDeclType.VAR)
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val program = Program("test", DummyFunctions, DummyMemsizer)
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assertTrue(C64Target.isInRegularRAM(target, program))
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target = createTestProgramForMemoryRefViaVar(0xd020, VarDeclType.VAR)
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assertFalse(C64Target.isInRegularRAM(target, program))
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target = createTestProgramForMemoryRefViaVar(0x1000, VarDeclType.CONST)
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assertTrue(C64Target.isInRegularRAM(target, program))
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target = createTestProgramForMemoryRefViaVar(0xd020, VarDeclType.CONST)
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assertFalse(C64Target.isInRegularRAM(target, program))
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target = createTestProgramForMemoryRefViaVar(0x1000, VarDeclType.MEMORY)
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assertFalse(C64Target.isInRegularRAM(target, program))
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}
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@Test
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private fun createTestProgramForMemoryRefViaVar(address: Int, vartype: VarDeclType): AssignTarget {
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val decl = VarDecl(vartype, DataType.BYTE, ZeropageWish.DONTCARE, null, "address", NumericLiteralValue.optimalInteger(address, Position.DUMMY), false, false, false, Position.DUMMY)
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val memexpr = IdentifierReference(listOf("address"), Position.DUMMY)
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val target = AssignTarget(null, null, DirectMemoryWrite(memexpr, Position.DUMMY), Position.DUMMY)
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val assignment = Assignment(target, NumericLiteralValue.optimalInteger(0, Position.DUMMY), Position.DUMMY)
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val subroutine = Subroutine("test", emptyList(), emptyList(), emptyList(), emptyList(), emptySet(), null, false, false, mutableListOf(decl, assignment), Position.DUMMY)
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val module = Module("test", mutableListOf(subroutine), Position.DUMMY, null)
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module.linkParents(ParentSentinel)
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return target
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}
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@Test
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fun testInValidRamC64_memory_expression() {
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val memexpr = PrefixExpression("+", NumericLiteralValue.optimalInteger(0x1000, Position.DUMMY), Position.DUMMY)
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val target = AssignTarget(null, null, DirectMemoryWrite(memexpr, Position.DUMMY), Position.DUMMY)
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2021-08-01 20:47:11 +00:00
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val program = Program("test", DummyFunctions, DummyMemsizer)
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2021-06-01 19:21:33 +00:00
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assertFalse(C64Target.isInRegularRAM(target, program))
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}
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@Test
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fun testInValidRamC64_variable() {
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val decl = VarDecl(VarDeclType.VAR, DataType.BYTE, ZeropageWish.DONTCARE, null, "address", null, false, false, false, Position.DUMMY)
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val target = AssignTarget(IdentifierReference(listOf("address"), Position.DUMMY), null, null, Position.DUMMY)
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val assignment = Assignment(target, NumericLiteralValue.optimalInteger(0, Position.DUMMY), Position.DUMMY)
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val subroutine = Subroutine("test", emptyList(), emptyList(), emptyList(), emptyList(), emptySet(), null, false, false, mutableListOf(decl, assignment), Position.DUMMY)
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val module = Module("test", mutableListOf(subroutine), Position.DUMMY, null)
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val program = Program("test", DummyFunctions, DummyMemsizer)
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.addModule(module)
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module.linkParents(ParentSentinel) // TODO: why not module.linkParents(program) or .linkParents(program.namespace)?
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assertTrue(C64Target.isInRegularRAM(target, program))
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}
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@Test
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fun testInValidRamC64_memmap_variable() {
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val address = 0x1000
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val decl = VarDecl(VarDeclType.MEMORY, DataType.UBYTE, ZeropageWish.DONTCARE, null, "address", NumericLiteralValue.optimalInteger(address, Position.DUMMY), false, false, false, Position.DUMMY)
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val target = AssignTarget(IdentifierReference(listOf("address"), Position.DUMMY), null, null, Position.DUMMY)
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val assignment = Assignment(target, NumericLiteralValue.optimalInteger(0, Position.DUMMY), Position.DUMMY)
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val subroutine = Subroutine("test", emptyList(), emptyList(), emptyList(), emptyList(), emptySet(), null, false, false, mutableListOf(decl, assignment), Position.DUMMY)
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val module = Module("test", mutableListOf(subroutine), Position.DUMMY, null)
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val program = Program("test", DummyFunctions, DummyMemsizer)
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.addModule(module)
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module.linkParents(ParentSentinel) // TODO: why not module.linkParents(program) or .linkParents(program.namespace)?
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2021-06-01 19:21:33 +00:00
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assertTrue(C64Target.isInRegularRAM(target, program))
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}
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@Test
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fun testNotInValidRamC64_memmap_variable() {
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val address = 0xd020
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val decl = VarDecl(VarDeclType.MEMORY, DataType.UBYTE, ZeropageWish.DONTCARE, null, "address", NumericLiteralValue.optimalInteger(address, Position.DUMMY), false, false, false, Position.DUMMY)
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val target = AssignTarget(IdentifierReference(listOf("address"), Position.DUMMY), null, null, Position.DUMMY)
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val assignment = Assignment(target, NumericLiteralValue.optimalInteger(0, Position.DUMMY), Position.DUMMY)
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val subroutine = Subroutine("test", emptyList(), emptyList(), emptyList(), emptyList(), emptySet(), null, false, false, mutableListOf(decl, assignment), Position.DUMMY)
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2021-07-09 15:32:33 +00:00
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val module = Module("test", mutableListOf(subroutine), Position.DUMMY, null)
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val program = Program("test", DummyFunctions, DummyMemsizer)
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.addModule(module)
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module.linkParents(ParentSentinel) // TODO: why not module.linkParents(program) or .linkParents(program.namespace)?
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2021-06-01 19:21:33 +00:00
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assertFalse(C64Target.isInRegularRAM(target, program))
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}
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@Test
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fun testInValidRamC64_array() {
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val decl = VarDecl(VarDeclType.VAR, DataType.ARRAY_UB, ZeropageWish.DONTCARE, null, "address", null, false, false, false, Position.DUMMY)
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val arrayindexed = ArrayIndexedExpression(IdentifierReference(listOf("address"), Position.DUMMY), ArrayIndex(NumericLiteralValue.optimalInteger(1, Position.DUMMY), Position.DUMMY), Position.DUMMY)
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val target = AssignTarget(null, arrayindexed, null, Position.DUMMY)
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val assignment = Assignment(target, NumericLiteralValue.optimalInteger(0, Position.DUMMY), Position.DUMMY)
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val subroutine = Subroutine("test", emptyList(), emptyList(), emptyList(), emptyList(), emptySet(), null, false, false, mutableListOf(decl, assignment), Position.DUMMY)
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2021-07-09 15:32:33 +00:00
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val module = Module("test", mutableListOf(subroutine), Position.DUMMY, null)
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2021-08-01 20:47:11 +00:00
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val program = Program("test", DummyFunctions, DummyMemsizer)
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.addModule(module)
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module.linkParents(ParentSentinel) // TODO: why not module.linkParents(program) or .linkParents(program.namespace)?
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2021-06-01 19:21:33 +00:00
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assertTrue(C64Target.isInRegularRAM(target, program))
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}
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@Test
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fun testInValidRamC64_array_memmapped() {
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val address = 0x1000
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val decl = VarDecl(VarDeclType.MEMORY, DataType.ARRAY_UB, ZeropageWish.DONTCARE, null, "address", NumericLiteralValue.optimalInteger(address, Position.DUMMY), false, false, false, Position.DUMMY)
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val arrayindexed = ArrayIndexedExpression(IdentifierReference(listOf("address"), Position.DUMMY), ArrayIndex(NumericLiteralValue.optimalInteger(1, Position.DUMMY), Position.DUMMY), Position.DUMMY)
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val target = AssignTarget(null, arrayindexed, null, Position.DUMMY)
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val assignment = Assignment(target, NumericLiteralValue.optimalInteger(0, Position.DUMMY), Position.DUMMY)
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val subroutine = Subroutine("test", emptyList(), emptyList(), emptyList(), emptyList(), emptySet(), null, false, false, mutableListOf(decl, assignment), Position.DUMMY)
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val module = Module("test", mutableListOf(subroutine), Position.DUMMY, null)
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2021-08-01 20:47:11 +00:00
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val program = Program("test", DummyFunctions, DummyMemsizer)
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.addModule(module)
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module.linkParents(ParentSentinel) // TODO: why not module.linkParents(program) or .linkParents(program.namespace)?
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2021-06-01 19:21:33 +00:00
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assertTrue(C64Target.isInRegularRAM(target, program))
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}
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@Test
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fun testNotValidRamC64_array_memmapped() {
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val address = 0xe000
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val decl = VarDecl(VarDeclType.MEMORY, DataType.ARRAY_UB, ZeropageWish.DONTCARE, null, "address", NumericLiteralValue.optimalInteger(address, Position.DUMMY), false, false, false, Position.DUMMY)
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val arrayindexed = ArrayIndexedExpression(IdentifierReference(listOf("address"), Position.DUMMY), ArrayIndex(NumericLiteralValue.optimalInteger(1, Position.DUMMY), Position.DUMMY), Position.DUMMY)
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val target = AssignTarget(null, arrayindexed, null, Position.DUMMY)
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val assignment = Assignment(target, NumericLiteralValue.optimalInteger(0, Position.DUMMY), Position.DUMMY)
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val subroutine = Subroutine("test", emptyList(), emptyList(), emptyList(), emptyList(), emptySet(), null, false, false, mutableListOf(decl, assignment), Position.DUMMY)
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2021-07-09 15:32:33 +00:00
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val module = Module("test", mutableListOf(subroutine), Position.DUMMY, null)
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2021-08-01 20:47:11 +00:00
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val program = Program("test", DummyFunctions, DummyMemsizer)
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.addModule(module)
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module.linkParents(ParentSentinel) // TODO: why not module.linkParents(program) or .linkParents(program.namespace)?
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2021-06-01 19:21:33 +00:00
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assertFalse(C64Target.isInRegularRAM(target, program))
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}
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}
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