mirror of
https://github.com/irmen/prog8.git
synced 2025-01-11 13:29:45 +00:00
working on vm
This commit is contained in:
Irmen de Jong
parent
3e44620966
commit
0307f6b42c
@ -27,9 +27,9 @@ class CodeGen(internal val program: PtProgram,
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// collect global variables initializers
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program.allBlocks().forEach {
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val chunk = VmCodeChunk()
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it.children.filterIsInstance<PtAssignment>().forEach { assign -> chunk += translate(assign, RegisterUsage(0)) }
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vmprog.addGlobalInits(chunk)
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val code = VmCodeChunk()
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it.children.filterIsInstance<PtAssignment>().forEach { assign -> code += translate(assign, RegisterUsage(0)) }
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vmprog.addGlobalInits(code)
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}
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val regUsage = RegisterUsage(0)
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@ -42,7 +42,7 @@ class CodeGen(internal val program: PtProgram,
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private fun translateNode(node: PtNode, regUsage: RegisterUsage): VmCodeChunk {
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val chunk = when(node) {
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val code = when(node) {
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is PtBlock -> translate(node, regUsage)
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is PtSub -> translate(node, regUsage)
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is PtScopeVarsDecls -> VmCodeChunk() // vars should be looked up via symbol table
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@ -56,13 +56,12 @@ class CodeGen(internal val program: PtProgram,
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is PtNop -> VmCodeChunk()
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is PtReturn -> translate(node)
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is PtJump -> translate(node)
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is PtConditionalBranch -> TODO()
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is PtWhen -> TODO()
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is PtPipe -> TODO()
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is PtForLoop -> TODO()
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is PtIfElse -> TODO()
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is PtIfElse -> translate(node, regUsage)
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is PtPostIncrDecr -> translate(node, regUsage)
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is PtRepeatLoop -> translate(node, regUsage)
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is PtWhen -> TODO()
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is PtLabel -> VmCodeChunk(VmCodeLabel(node.scopedName))
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is PtBreakpoint -> VmCodeChunk(VmCodeInstruction(Instruction(Opcode.BREAKPOINT)))
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is PtAddressOf,
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@ -80,18 +79,60 @@ class CodeGen(internal val program: PtProgram,
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is PtSubroutineParameter,
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is PtNumber,
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is PtArrayLiteral,
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is PtString -> throw AssemblyError("$node should not occur as separate statement node")
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is PtAsmSub -> throw AssemblyError("asmsub not supported on virtual machine target")
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is PtInlineAssembly -> throw AssemblyError("inline assembly not supported on virtual machine target")
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is PtIncludeBinary -> throw AssemblyError("inline binary data not supported on virtual machine target")
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is PtString -> throw AssemblyError("strings should not occur as separate statement node ${node.position}")
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is PtAsmSub -> throw AssemblyError("asmsub not supported on virtual machine target ${node.position}")
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is PtInlineAssembly -> throw AssemblyError("inline assembly not supported on virtual machine target ${node.position}")
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is PtIncludeBinary -> throw AssemblyError("inline binary data not supported on virtual machine target ${node.position}")
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is PtConditionalBranch -> throw AssemblyError("conditional branches not supported in vm target due to lack of cpu flags ${node.position}")
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else -> TODO("missing codegen for $node")
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}
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chunk.lines.add(0, VmCodeComment(node.position.toString()))
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return chunk
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code.lines.add(0, VmCodeComment(node.position.toString()))
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return code
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}
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private fun translate(ifElse: PtIfElse, regUsage: RegisterUsage): VmCodeChunk {
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var branch = Opcode.BZ
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var condition = ifElse.condition
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val cond = ifElse.condition as? PtBinaryExpression
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if((cond?.right as? PtNumber)?.number==0.0) {
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if(cond.operator == "==") {
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// if X==0 ... so we branch on Not-zero instead.
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branch = Opcode.BNZ
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condition = cond.left
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}
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else if(cond.operator == "!=") {
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// if X!=0 ... so we keep branching on Zero.
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condition = cond.left
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}
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}
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val conditionReg = regUsage.nextFree()
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val vmDt = vmType(condition.type)
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val code = VmCodeChunk()
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code += expressionEval.translateExpression(condition, conditionReg, regUsage)
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if(ifElse.elseScope.children.isNotEmpty()) {
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// if and else parts
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val elseLabel = createLabelName()
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val afterIfLabel = createLabelName()
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code += VmCodeInstruction(Instruction(branch, vmDt, reg1=conditionReg), labelArg = elseLabel)
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code += translateNode(ifElse.ifScope, regUsage)
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code += VmCodeInstruction(Instruction(Opcode.JUMP), labelArg = afterIfLabel)
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code += VmCodeLabel(elseLabel)
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code += translateNode(ifElse.elseScope, regUsage)
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code += VmCodeLabel(afterIfLabel)
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} else {
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// only if part
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val afterIfLabel = createLabelName()
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code += VmCodeInstruction(Instruction(branch, vmDt, reg1=conditionReg), labelArg = afterIfLabel)
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code += translateNode(ifElse.ifScope, regUsage)
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code += VmCodeLabel(afterIfLabel)
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}
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return code
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}
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private fun translate(postIncrDecr: PtPostIncrDecr, regUsage: RegisterUsage): VmCodeChunk {
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val chunk = VmCodeChunk()
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val code = VmCodeChunk()
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val operation = when(postIncrDecr.operator) {
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"++" -> Opcode.INC
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"--" -> Opcode.DEC
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@ -104,21 +145,21 @@ class CodeGen(internal val program: PtProgram,
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val resultReg = regUsage.nextFree()
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if(ident!=null) {
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val address = allocations.get(ident.targetName)
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chunk += VmCodeInstruction(Instruction(Opcode.LOADM, vmDt, reg1=resultReg, value = address))
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chunk += VmCodeInstruction(Instruction(operation, vmDt, reg1=resultReg))
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chunk += VmCodeInstruction(Instruction(Opcode.STOREM, vmDt, reg1=resultReg, value = address))
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code += VmCodeInstruction(Instruction(Opcode.LOADM, vmDt, reg1=resultReg, value = address))
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code += VmCodeInstruction(Instruction(operation, vmDt, reg1=resultReg))
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code += VmCodeInstruction(Instruction(Opcode.STOREM, vmDt, reg1=resultReg, value = address))
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} else if(memory!=null) {
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val addressReg = regUsage.nextFree()
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chunk += expressionEval.translateExpression(memory.address, addressReg, regUsage)
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chunk += VmCodeInstruction(Instruction(Opcode.LOADI, vmDt, reg1=resultReg, reg2=addressReg))
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chunk += VmCodeInstruction(Instruction(operation, vmDt, reg1=resultReg))
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chunk += VmCodeInstruction(Instruction(Opcode.STOREI, vmDt, reg1=resultReg, reg2=addressReg))
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code += expressionEval.translateExpression(memory.address, addressReg, regUsage)
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code += VmCodeInstruction(Instruction(Opcode.LOADI, vmDt, reg1=resultReg, reg2=addressReg))
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code += VmCodeInstruction(Instruction(operation, vmDt, reg1=resultReg))
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code += VmCodeInstruction(Instruction(Opcode.STOREI, vmDt, reg1=resultReg, reg2=addressReg))
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} else if (array!=null) {
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TODO("postincrdecr array")
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} else
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throw AssemblyError("weird assigntarget")
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return chunk
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return code
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}
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private fun translate(repeat: PtRepeatLoop, regUsage: RegisterUsage): VmCodeChunk {
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@ -131,43 +172,43 @@ class CodeGen(internal val program: PtProgram,
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repeat.children[0] = PtNumber(DataType.UBYTE, 0.0, repeat.count.position)
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}
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val chunk = VmCodeChunk()
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val code = VmCodeChunk()
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val counterReg = regUsage.nextFree()
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val vmDt = vmType(repeat.count.type)
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chunk += expressionEval.translateExpression(repeat.count, counterReg, regUsage)
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code += expressionEval.translateExpression(repeat.count, counterReg, regUsage)
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val repeatLabel = createLabelName()
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chunk += VmCodeLabel(repeatLabel)
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chunk += translateNode(repeat.statements, regUsage)
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chunk += VmCodeInstruction(Instruction(Opcode.DEC, vmDt, reg1=counterReg))
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chunk += VmCodeInstruction(Instruction(Opcode.BNZ, vmDt, reg1=counterReg), labelArg = repeatLabel)
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return chunk
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code += VmCodeLabel(repeatLabel)
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code += translateNode(repeat.statements, regUsage)
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code += VmCodeInstruction(Instruction(Opcode.DEC, vmDt, reg1=counterReg))
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code += VmCodeInstruction(Instruction(Opcode.BNZ, vmDt, reg1=counterReg), labelArg = repeatLabel)
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return code
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}
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private fun translate(jump: PtJump): VmCodeChunk {
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val chunk = VmCodeChunk()
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val code = VmCodeChunk()
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if(jump.address!=null)
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throw AssemblyError("cannot jump to memory location in the vm target")
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chunk += if(jump.generatedLabel!=null)
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code += if(jump.generatedLabel!=null)
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VmCodeInstruction(Instruction(Opcode.JUMP), labelArg = listOf(jump.generatedLabel!!))
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else if(jump.identifier!=null)
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VmCodeInstruction(Instruction(Opcode.JUMP), labelArg = jump.identifier!!.targetName)
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else
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throw AssemblyError("weird jump")
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return chunk
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return code
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}
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private fun translateGroup(group: List<PtNode>, regUsage: RegisterUsage): VmCodeChunk {
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val chunk = VmCodeChunk()
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group.forEach { chunk += translateNode(it, regUsage) }
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return chunk
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val code = VmCodeChunk()
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group.forEach { code += translateNode(it, regUsage) }
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return code
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}
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private fun translate(assignment: PtAssignment, regUsage: RegisterUsage): VmCodeChunk {
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// TODO optimize in-place assignments (assignment.augmentable = true)
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// TODO can in-place assignments (assignment.augmentable = true) be optimized more?
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val chunk = VmCodeChunk()
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val code = VmCodeChunk()
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val resultRegister = regUsage.nextFree()
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chunk += expressionEval.translateExpression(assignment.value, resultRegister, regUsage)
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code += expressionEval.translateExpression(assignment.value, resultRegister, regUsage)
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val ident = assignment.target.identifier
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val memory = assignment.target.memory
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val array = assignment.target.array
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@ -175,7 +216,7 @@ class CodeGen(internal val program: PtProgram,
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if(ident!=null) {
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val address = allocations.get(ident.targetName)
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val ins = Instruction(Opcode.STOREM, vmDt, reg1=resultRegister, value=address)
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chunk += VmCodeInstruction(ins)
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code += VmCodeInstruction(ins)
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}
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else if(array!=null) {
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TODO("assign to array")
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@ -186,48 +227,48 @@ class CodeGen(internal val program: PtProgram,
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Instruction(Opcode.STOREM, vmDt, reg1=resultRegister, value=(memory.address as PtNumber).number.toInt())
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} else {
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val addressRegister = regUsage.nextFree()
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chunk += expressionEval.translateExpression(assignment.value, addressRegister, regUsage)
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code += expressionEval.translateExpression(assignment.value, addressRegister, regUsage)
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Instruction(Opcode.STOREI, vmDt, reg1=resultRegister, reg2=addressRegister)
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}
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chunk += VmCodeInstruction(ins)
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code += VmCodeInstruction(ins)
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}
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else
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throw AssemblyError("weird assigntarget")
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return chunk
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return code
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}
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private fun translate(ret: PtReturn): VmCodeChunk {
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val chunk = VmCodeChunk()
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val code = VmCodeChunk()
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val value = ret.value
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if(value!=null) {
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// Call Convention: return value is always returned in r0
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chunk += expressionEval.translateExpression(value, 0, RegisterUsage(1))
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code += expressionEval.translateExpression(value, 0, RegisterUsage(1))
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}
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chunk += VmCodeInstruction(Instruction(Opcode.RETURN))
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return chunk
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code += VmCodeInstruction(Instruction(Opcode.RETURN))
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return code
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}
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private fun translate(sub: PtSub, regUsage: RegisterUsage): VmCodeChunk {
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// TODO actually inline subroutines marked as inline
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val chunk = VmCodeChunk()
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chunk += VmCodeComment("SUB: ${sub.scopedName} -> ${sub.returntype}")
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chunk += VmCodeLabel(sub.scopedName)
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val code = VmCodeChunk()
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code += VmCodeComment("SUB: ${sub.scopedName} -> ${sub.returntype}")
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code += VmCodeLabel(sub.scopedName)
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for (child in sub.children) {
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chunk += translateNode(child, regUsage)
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code += translateNode(child, regUsage)
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}
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chunk += VmCodeComment("SUB-END '${sub.name}'")
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return chunk
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code += VmCodeComment("SUB-END '${sub.name}'")
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return code
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}
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private fun translate(block: PtBlock, regUsage: RegisterUsage): VmCodeChunk {
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val chunk = VmCodeChunk()
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chunk += VmCodeComment("BLOCK '${block.name}' addr=${block.address} lib=${block.library}")
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val code = VmCodeChunk()
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code += VmCodeComment("BLOCK '${block.name}' addr=${block.address} lib=${block.library}")
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for (child in block.children) {
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if(child !is PtAssignment) // global variable initialization is done elsewhere
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chunk += translateNode(child, regUsage)
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code += translateNode(child, regUsage)
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}
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chunk += VmCodeComment("BLOCK-END '${block.name}'")
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return chunk
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code += VmCodeComment("BLOCK-END '${block.name}'")
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return code
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}
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@ -23,16 +23,16 @@ internal class ExpressionGen(val codeGen: CodeGen) {
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fun translateExpression(expr: PtExpression, resultRegister: Int, regUsage: RegisterUsage): VmCodeChunk {
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require(regUsage.firstFree > resultRegister)
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val chunk = VmCodeChunk()
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val code = VmCodeChunk()
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val vmDt = codeGen.vmType(expr.type)
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when (expr) {
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is PtNumber -> {
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chunk += VmCodeInstruction(Instruction(Opcode.LOAD, vmDt, reg1=resultRegister, value=expr.number.toInt()))
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code += VmCodeInstruction(Instruction(Opcode.LOAD, vmDt, reg1=resultRegister, value=expr.number.toInt()))
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}
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is PtIdentifier -> {
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val mem = codeGen.allocations.get(expr.targetName)
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chunk += if(expr.type in PassByValueDatatypes) {
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code += if(expr.type in PassByValueDatatypes) {
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VmCodeInstruction(Instruction(Opcode.LOADM, vmDt, reg1=resultRegister, value=mem))
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} else {
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// for strings and arrays etc., load the *address* of the value instead
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@ -41,19 +41,19 @@ internal class ExpressionGen(val codeGen: CodeGen) {
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}
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is PtAddressOf -> {
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val mem = codeGen.allocations.get(expr.identifier.targetName)
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chunk += VmCodeInstruction(Instruction(Opcode.LOAD, vmDt, reg1=resultRegister, value=mem))
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code += VmCodeInstruction(Instruction(Opcode.LOAD, vmDt, reg1=resultRegister, value=mem))
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}
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is PtMemoryByte -> {
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val addressRegister = regUsage.nextFree()
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val addressExprCode = translateExpression(expr.address, addressRegister, regUsage)
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chunk += addressExprCode
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code += addressExprCode
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}
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is PtTypeCast -> chunk += translate(expr, resultRegister, regUsage)
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is PtPrefix -> chunk += translate(expr, resultRegister, regUsage)
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is PtArrayIndexer -> chunk += translate(expr, resultRegister, regUsage)
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is PtBinaryExpression -> chunk += translate(expr, resultRegister, regUsage)
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is PtBuiltinFunctionCall -> chunk += translate(expr, resultRegister, regUsage)
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is PtFunctionCall -> chunk += translate(expr, resultRegister, regUsage)
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is PtTypeCast -> code += translate(expr, resultRegister, regUsage)
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is PtPrefix -> code += translate(expr, resultRegister, regUsage)
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is PtArrayIndexer -> code += translate(expr, resultRegister, regUsage)
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is PtBinaryExpression -> code += translate(expr, resultRegister, regUsage)
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is PtBuiltinFunctionCall -> code += translate(expr, resultRegister, regUsage)
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is PtFunctionCall -> code += translate(expr, resultRegister, regUsage)
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is PtContainmentCheck -> TODO()
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is PtPipe -> TODO()
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is PtRange,
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@ -61,60 +61,59 @@ internal class ExpressionGen(val codeGen: CodeGen) {
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is PtString -> throw AssemblyError("range/arrayliteral/string should no longer occur as expression")
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else -> throw AssemblyError("weird expression")
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}
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return chunk
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return code
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}
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private fun translate(arrayIx: PtArrayIndexer, resultRegister: Int, regUsage: RegisterUsage): VmCodeChunk {
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val eltSize = codeGen.program.memsizer.memorySize(arrayIx.type)
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val vmDt = codeGen.vmType(arrayIx.type)
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val chunk = VmCodeChunk()
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val code = VmCodeChunk()
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val idxReg = regUsage.nextFree()
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chunk += translateExpression(arrayIx.index, idxReg, regUsage)
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code += translateExpression(arrayIx.index, idxReg, regUsage)
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if(eltSize>1) {
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val factorReg = regUsage.nextFree()
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chunk += VmCodeInstruction(Instruction(Opcode.LOAD, VmDataType.BYTE, reg1=factorReg, value=eltSize))
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chunk += VmCodeInstruction(Instruction(Opcode.MUL, VmDataType.BYTE, reg1=idxReg, reg2=factorReg))
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code += VmCodeInstruction(Instruction(Opcode.LOAD, VmDataType.BYTE, reg1=factorReg, value=eltSize))
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code += VmCodeInstruction(Instruction(Opcode.MUL, VmDataType.BYTE, reg1=idxReg, reg2=factorReg))
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}
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val arrayLocation = codeGen.allocations.get(arrayIx.variable.targetName)
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chunk += VmCodeInstruction(Instruction(Opcode.LOADX, vmDt, reg1=resultRegister, reg2=idxReg, value = arrayLocation))
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return chunk
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code += VmCodeInstruction(Instruction(Opcode.LOADX, vmDt, reg1=resultRegister, reg2=idxReg, value = arrayLocation))
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return code
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}
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private fun translate(expr: PtPrefix, resultRegister: Int, regUsage: RegisterUsage): VmCodeChunk {
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// operator can be: +, -, ~, not
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val chunk = VmCodeChunk()
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chunk += translateExpression(expr.value, resultRegister, regUsage)
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val code = VmCodeChunk()
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code += translateExpression(expr.value, resultRegister, regUsage)
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val vmDt = codeGen.vmType(expr.type)
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when(expr.operator) {
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"+" -> { }
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"-" -> {
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chunk += VmCodeInstruction(Instruction(Opcode.NEG, vmDt, reg1=resultRegister))
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code += VmCodeInstruction(Instruction(Opcode.NEG, vmDt, reg1=resultRegister))
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}
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"~" -> {
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val regMask = regUsage.nextFree()
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val mask = if(vmDt==VmDataType.BYTE) 0x00ff else 0xffff
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chunk += VmCodeInstruction(Instruction(Opcode.LOAD, vmDt, reg1=regMask, value=mask))
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chunk += VmCodeInstruction(Instruction(Opcode.XOR, vmDt, reg1=resultRegister, reg2=resultRegister, reg3=regMask))
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code += VmCodeInstruction(Instruction(Opcode.LOAD, vmDt, reg1=regMask, value=mask))
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code += VmCodeInstruction(Instruction(Opcode.XOR, vmDt, reg1=resultRegister, reg2=resultRegister, reg3=regMask))
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}
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"not" -> {
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val label = codeGen.createLabelName()
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chunk += VmCodeInstruction(Instruction(Opcode.BZ, vmDt, reg1=resultRegister), labelArg = label)
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chunk += VmCodeInstruction(Instruction(Opcode.LOAD, vmDt, reg1=resultRegister, value=1))
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chunk += VmCodeLabel(label)
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code += VmCodeInstruction(Instruction(Opcode.BZ, vmDt, reg1=resultRegister), labelArg = label)
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code += VmCodeInstruction(Instruction(Opcode.LOAD, vmDt, reg1=resultRegister, value=1))
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code += VmCodeLabel(label)
|
||||
val regMask = regUsage.nextFree()
|
||||
chunk += VmCodeInstruction(Instruction(Opcode.LOAD, vmDt, reg1=regMask, value=1))
|
||||
chunk += VmCodeInstruction(Instruction(Opcode.XOR, vmDt, reg1=resultRegister, reg2=resultRegister, reg3=regMask))
|
||||
code += VmCodeInstruction(Instruction(Opcode.LOAD, vmDt, reg1=regMask, value=1))
|
||||
code += VmCodeInstruction(Instruction(Opcode.XOR, vmDt, reg1=resultRegister, reg2=resultRegister, reg3=regMask))
|
||||
}
|
||||
else -> throw AssemblyError("weird prefix operator")
|
||||
}
|
||||
return chunk
|
||||
return code
|
||||
}
|
||||
|
||||
private fun translate(cast: PtTypeCast, resultRegister: Int, regUsage: RegisterUsage): VmCodeChunk {
|
||||
val chunk = VmCodeChunk()
|
||||
val code = VmCodeChunk()
|
||||
if(cast.type==cast.value.type)
|
||||
return chunk
|
||||
chunk += translateExpression(cast.value, resultRegister, regUsage)
|
||||
return code
|
||||
code += translateExpression(cast.value, resultRegister, regUsage)
|
||||
when(cast.type) {
|
||||
DataType.UBYTE -> {
|
||||
when(cast.value.type) {
|
||||
@ -138,11 +137,11 @@ internal class ExpressionGen(val codeGen: CodeGen) {
|
||||
when(cast.value.type) {
|
||||
DataType.BYTE -> {
|
||||
// byte -> uword: sign extend
|
||||
chunk += VmCodeInstruction(Instruction(Opcode.EXTS, type = VmDataType.BYTE, reg1 = resultRegister))
|
||||
code += VmCodeInstruction(Instruction(Opcode.EXTS, type = VmDataType.BYTE, reg1 = resultRegister))
|
||||
}
|
||||
DataType.UBYTE -> {
|
||||
// ubyte -> uword: sign extend
|
||||
chunk += VmCodeInstruction(Instruction(Opcode.EXT, type = VmDataType.BYTE, reg1 = resultRegister))
|
||||
code += VmCodeInstruction(Instruction(Opcode.EXT, type = VmDataType.BYTE, reg1 = resultRegister))
|
||||
}
|
||||
DataType.WORD -> { }
|
||||
DataType.FLOAT -> {
|
||||
@ -155,11 +154,11 @@ internal class ExpressionGen(val codeGen: CodeGen) {
|
||||
when(cast.value.type) {
|
||||
DataType.BYTE -> {
|
||||
// byte -> word: sign extend
|
||||
chunk += VmCodeInstruction(Instruction(Opcode.EXTS, type = VmDataType.BYTE, reg1 = resultRegister))
|
||||
code += VmCodeInstruction(Instruction(Opcode.EXTS, type = VmDataType.BYTE, reg1 = resultRegister))
|
||||
}
|
||||
DataType.UBYTE -> {
|
||||
// byte -> word: sign extend
|
||||
chunk += VmCodeInstruction(Instruction(Opcode.EXT, type = VmDataType.BYTE, reg1 = resultRegister))
|
||||
code += VmCodeInstruction(Instruction(Opcode.EXT, type = VmDataType.BYTE, reg1 = resultRegister))
|
||||
}
|
||||
DataType.UWORD -> { }
|
||||
DataType.FLOAT -> {
|
||||
@ -188,105 +187,126 @@ internal class ExpressionGen(val codeGen: CodeGen) {
|
||||
}
|
||||
else -> throw AssemblyError("weird cast type")
|
||||
}
|
||||
return chunk
|
||||
return code
|
||||
}
|
||||
|
||||
private fun translate(binExpr: PtBinaryExpression, resultRegister: Int, regUsage: RegisterUsage): VmCodeChunk {
|
||||
val chunk = VmCodeChunk()
|
||||
val code = VmCodeChunk()
|
||||
val leftResultReg = regUsage.nextFree()
|
||||
val rightResultReg = regUsage.nextFree()
|
||||
val leftCode = translateExpression(binExpr.left, leftResultReg, regUsage)
|
||||
val rightCode = translateExpression(binExpr.right, rightResultReg, regUsage)
|
||||
chunk += leftCode
|
||||
chunk += rightCode
|
||||
// TODO: optimized codegen when left or right operand is known 0 or 1 or whatever.
|
||||
code += leftCode
|
||||
code += rightCode
|
||||
val vmDt = codeGen.vmType(binExpr.type)
|
||||
when(binExpr.operator) {
|
||||
"+" -> {
|
||||
chunk += VmCodeInstruction(Instruction(Opcode.ADD, vmDt, reg1=resultRegister, reg2=leftResultReg, reg3=rightResultReg))
|
||||
code += VmCodeInstruction(Instruction(Opcode.ADD, vmDt, reg1=resultRegister, reg2=leftResultReg, reg3=rightResultReg))
|
||||
}
|
||||
"-" -> {
|
||||
chunk += VmCodeInstruction(Instruction(Opcode.SUB, vmDt, reg1=resultRegister, reg2=leftResultReg, reg3=rightResultReg))
|
||||
code += VmCodeInstruction(Instruction(Opcode.SUB, vmDt, reg1=resultRegister, reg2=leftResultReg, reg3=rightResultReg))
|
||||
}
|
||||
"*" -> {
|
||||
chunk += VmCodeInstruction(Instruction(Opcode.MUL, vmDt, reg1=resultRegister, reg2=leftResultReg, reg3=rightResultReg))
|
||||
code += VmCodeInstruction(Instruction(Opcode.MUL, vmDt, reg1=resultRegister, reg2=leftResultReg, reg3=rightResultReg))
|
||||
}
|
||||
"/" -> {
|
||||
chunk += VmCodeInstruction(Instruction(Opcode.DIV, vmDt, reg1=resultRegister, reg2=leftResultReg, reg3=rightResultReg))
|
||||
code += VmCodeInstruction(Instruction(Opcode.DIV, vmDt, reg1=resultRegister, reg2=leftResultReg, reg3=rightResultReg))
|
||||
}
|
||||
"%" -> {
|
||||
chunk += VmCodeInstruction(Instruction(Opcode.MOD, vmDt, reg1=resultRegister, reg2=leftResultReg, reg3=rightResultReg))
|
||||
code += VmCodeInstruction(Instruction(Opcode.MOD, vmDt, reg1=resultRegister, reg2=leftResultReg, reg3=rightResultReg))
|
||||
}
|
||||
"|", "or" -> {
|
||||
code += VmCodeInstruction(Instruction(Opcode.OR, vmDt, reg1=resultRegister, reg2=leftResultReg, reg3=rightResultReg))
|
||||
}
|
||||
"&", "and" -> {
|
||||
code += VmCodeInstruction(Instruction(Opcode.AND, vmDt, reg1=resultRegister, reg2=leftResultReg, reg3=rightResultReg))
|
||||
}
|
||||
"^", "xor" -> {
|
||||
code += VmCodeInstruction(Instruction(Opcode.XOR, vmDt, reg1=resultRegister, reg2=leftResultReg, reg3=rightResultReg))
|
||||
}
|
||||
"<<" -> {
|
||||
// TODO check if shift amount works
|
||||
code += VmCodeInstruction(Instruction(Opcode.LSL, vmDt, reg1=resultRegister, reg2=leftResultReg, reg3=rightResultReg))
|
||||
}
|
||||
">>" -> {
|
||||
// TODO check if shift amount works
|
||||
code += VmCodeInstruction(Instruction(Opcode.LSR, vmDt, reg1=resultRegister, reg2=leftResultReg, reg3=rightResultReg))
|
||||
}
|
||||
"**" -> throw AssemblyError("** operator requires floating point ${binExpr.position}")
|
||||
// TODO the other operators: "<<", ">>", "==", "!=", "<", ">", "<=", ">="
|
||||
else -> TODO("operator ${binExpr.operator}")
|
||||
}
|
||||
return chunk
|
||||
return code
|
||||
}
|
||||
|
||||
fun translate(fcall: PtFunctionCall, resultRegister: Int, regUsage: RegisterUsage): VmCodeChunk {
|
||||
val subroutine = codeGen.symbolTable.flat.getValue(fcall.functionName) as StSub
|
||||
val chunk = VmCodeChunk()
|
||||
val code = VmCodeChunk()
|
||||
for ((arg, parameter) in fcall.args.zip(subroutine.parameters)) {
|
||||
val argReg = regUsage.nextFree()
|
||||
chunk += translateExpression(arg, argReg, regUsage)
|
||||
code += translateExpression(arg, argReg, regUsage)
|
||||
val vmDt = codeGen.vmType(parameter.type)
|
||||
val mem = codeGen.allocations.get(fcall.functionName + parameter.name)
|
||||
chunk += VmCodeInstruction(Instruction(Opcode.STOREM, vmDt, reg1=argReg, value=mem))
|
||||
code += VmCodeInstruction(Instruction(Opcode.STOREM, vmDt, reg1=argReg, value=mem))
|
||||
}
|
||||
chunk += VmCodeInstruction(Instruction(Opcode.CALL), labelArg=fcall.functionName)
|
||||
code += VmCodeInstruction(Instruction(Opcode.CALL), labelArg=fcall.functionName)
|
||||
if(!fcall.void && resultRegister!=0) {
|
||||
// Call convention: result value is in r0, so put it in the required register instead.
|
||||
chunk += VmCodeInstruction(Instruction(Opcode.LOADR, codeGen.vmType(fcall.type), reg1=resultRegister, reg2=0))
|
||||
code += VmCodeInstruction(Instruction(Opcode.LOADR, codeGen.vmType(fcall.type), reg1=resultRegister, reg2=0))
|
||||
}
|
||||
return chunk
|
||||
return code
|
||||
}
|
||||
|
||||
fun translate(call: PtBuiltinFunctionCall, resultRegister: Int, regUsage: RegisterUsage): VmCodeChunk {
|
||||
val chunk = VmCodeChunk()
|
||||
val code = VmCodeChunk()
|
||||
when(call.name) {
|
||||
"syscall" -> {
|
||||
val vExpr = call.args.single() as PtNumber
|
||||
chunk += VmCodeInstruction(Instruction(Opcode.SYSCALL, value=vExpr.number.toInt()))
|
||||
code += VmCodeInstruction(Instruction(Opcode.SYSCALL, value=vExpr.number.toInt()))
|
||||
}
|
||||
"syscall1" -> {
|
||||
chunk += VmCodeInstruction(Instruction(Opcode.PUSH, VmDataType.BYTE, reg1 = 0))
|
||||
code += VmCodeInstruction(Instruction(Opcode.PUSH, VmDataType.BYTE, reg1 = 0))
|
||||
val callNr = (call.args[0] as PtNumber).number.toInt()
|
||||
chunk += translateExpression(call.args[1], 0, regUsage)
|
||||
chunk += VmCodeInstruction(Instruction(Opcode.SYSCALL, value=callNr))
|
||||
chunk += VmCodeInstruction(Instruction(Opcode.POP, VmDataType.BYTE, reg1 = 0))
|
||||
code += translateExpression(call.args[1], 0, regUsage)
|
||||
code += VmCodeInstruction(Instruction(Opcode.SYSCALL, value=callNr))
|
||||
code += VmCodeInstruction(Instruction(Opcode.POP, VmDataType.BYTE, reg1 = 0))
|
||||
}
|
||||
"syscall2" -> {
|
||||
chunk += VmCodeInstruction(Instruction(Opcode.PUSH, VmDataType.BYTE, reg1 = 0))
|
||||
chunk += VmCodeInstruction(Instruction(Opcode.PUSH, VmDataType.WORD, reg1 = 1))
|
||||
code += VmCodeInstruction(Instruction(Opcode.PUSH, VmDataType.BYTE, reg1 = 0))
|
||||
code += VmCodeInstruction(Instruction(Opcode.PUSH, VmDataType.WORD, reg1 = 1))
|
||||
while(regUsage.firstFree<2) {
|
||||
regUsage.nextFree()
|
||||
}
|
||||
val callNr = (call.args[0] as PtNumber).number.toInt()
|
||||
chunk += translateExpression(call.args[1], 0, regUsage)
|
||||
chunk += translateExpression(call.args[2], 1, regUsage)
|
||||
chunk += VmCodeInstruction(Instruction(Opcode.SYSCALL, value=callNr))
|
||||
chunk += VmCodeInstruction(Instruction(Opcode.POP, VmDataType.WORD, reg1 = 1))
|
||||
chunk += VmCodeInstruction(Instruction(Opcode.POP, VmDataType.BYTE, reg1 = 0))
|
||||
code += translateExpression(call.args[1], 0, regUsage)
|
||||
code += translateExpression(call.args[2], 1, regUsage)
|
||||
code += VmCodeInstruction(Instruction(Opcode.SYSCALL, value=callNr))
|
||||
code += VmCodeInstruction(Instruction(Opcode.POP, VmDataType.WORD, reg1 = 1))
|
||||
code += VmCodeInstruction(Instruction(Opcode.POP, VmDataType.BYTE, reg1 = 0))
|
||||
}
|
||||
"syscall3" -> {
|
||||
chunk += VmCodeInstruction(Instruction(Opcode.PUSH, VmDataType.BYTE, reg1 = 0))
|
||||
chunk += VmCodeInstruction(Instruction(Opcode.PUSH, VmDataType.WORD, reg1 = 1))
|
||||
chunk += VmCodeInstruction(Instruction(Opcode.PUSH, VmDataType.WORD, reg1 = 2))
|
||||
code += VmCodeInstruction(Instruction(Opcode.PUSH, VmDataType.BYTE, reg1 = 0))
|
||||
code += VmCodeInstruction(Instruction(Opcode.PUSH, VmDataType.WORD, reg1 = 1))
|
||||
code += VmCodeInstruction(Instruction(Opcode.PUSH, VmDataType.WORD, reg1 = 2))
|
||||
while(regUsage.firstFree<3) {
|
||||
regUsage.nextFree()
|
||||
}
|
||||
val callNr = (call.args[0] as PtNumber).number.toInt()
|
||||
chunk += translateExpression(call.args[1], 0, regUsage)
|
||||
chunk += translateExpression(call.args[2], 1, regUsage)
|
||||
chunk += translateExpression(call.args[3], 2, regUsage)
|
||||
chunk += VmCodeInstruction(Instruction(Opcode.SYSCALL, value=callNr))
|
||||
chunk += VmCodeInstruction(Instruction(Opcode.POP, VmDataType.WORD, reg1 = 2))
|
||||
chunk += VmCodeInstruction(Instruction(Opcode.POP, VmDataType.WORD, reg1 = 1))
|
||||
chunk += VmCodeInstruction(Instruction(Opcode.POP, VmDataType.BYTE, reg1 = 0))
|
||||
code += translateExpression(call.args[1], 0, regUsage)
|
||||
code += translateExpression(call.args[2], 1, regUsage)
|
||||
code += translateExpression(call.args[3], 2, regUsage)
|
||||
code += VmCodeInstruction(Instruction(Opcode.SYSCALL, value=callNr))
|
||||
code += VmCodeInstruction(Instruction(Opcode.POP, VmDataType.WORD, reg1 = 2))
|
||||
code += VmCodeInstruction(Instruction(Opcode.POP, VmDataType.WORD, reg1 = 1))
|
||||
code += VmCodeInstruction(Instruction(Opcode.POP, VmDataType.BYTE, reg1 = 0))
|
||||
}
|
||||
else -> {
|
||||
// TODO builtin functions...
|
||||
TODO("builtinfunc ${call.name}")
|
||||
}
|
||||
}
|
||||
return chunk
|
||||
return code
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
@ -18,8 +18,8 @@ Future Things and Ideas
|
||||
^^^^^^^^^^^^^^^^^^^^^^^
|
||||
Compiler:
|
||||
|
||||
- vm code gen: don't reuse registers, don't pre allocate variables (except strings + arrays) but instead put them into registers too
|
||||
then we have Static Single Assignment form in the VM code
|
||||
- vm code gen: don't reuse registers and don't pre allocate variables? (except strings + arrays) but instead put them into registers too
|
||||
then we ALMOST have Static Single Assignment form in the VM code. But what can we use that for?
|
||||
- pipe operator: allow non-unary function calls in the pipe that specify the other argument(s) in the calls.
|
||||
- writeAssembly(): make it possible to actually get rid of the VarDecl nodes by fixing the rest of the code mentioned there.
|
||||
- make everything an expression? (get rid of Statements. Statements are expressions with void return types?).
|
||||
|
||||
@ -10,6 +10,8 @@ main {
|
||||
syscall1(8, 0) ; enable lo res creen
|
||||
ubyte shifter
|
||||
|
||||
shifter >>= 1
|
||||
|
||||
repeat {
|
||||
uword xx
|
||||
uword yy = 0
|
||||
@ -22,6 +24,9 @@ main {
|
||||
yy++
|
||||
}
|
||||
shifter+=4
|
||||
|
||||
txt.print_ub(shifter)
|
||||
txt.nl()
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
@ -104,11 +104,12 @@ All have type b or w.
|
||||
and reg1, reg2, reg3 - reg1 = reg2 bitwise and reg3
|
||||
or reg1, reg2, reg3 - reg1 = reg2 bitwise or reg3
|
||||
xor reg1, reg2, reg3 - reg1 = reg2 bitwise xor reg3
|
||||
lsr reg1 - reg1 = shift reg1 right by 1 bit
|
||||
lsl reg1 - reg1 = shift reg1 left by 1 bit
|
||||
ror reg1 - reg1 = rotate reg1 right by 1 bit, not using carry
|
||||
rol reg1 - reg1 = rotate reg1 left by 1 bit, not using carry
|
||||
lsr reg1, reg2, reg3 - reg1 = shift reg2 right by reg3 bits
|
||||
lsl reg1, reg2, reg3 - reg1 = shift reg2 left by reg3 bits
|
||||
ror reg1, reg2, reg3 - reg1 = rotate reg2 right by reg3 bits, not using carry
|
||||
rol reg1, reg2, reg3 - reg1 = rotate reg2 left by reg3 bits, not using carry
|
||||
|
||||
TODO add asr? (arithmetical shift right, so with sign bit)
|
||||
TODO also add ror/rol variants using the carry bit? These do map directly on 6502 and 68k instructions.
|
||||
|
||||
|
||||
@ -285,10 +286,10 @@ val instructionFormats = mutableMapOf(
|
||||
Opcode.AND to InstructionFormat(BW, true, true, true, false),
|
||||
Opcode.OR to InstructionFormat(BW, true, true, true, false),
|
||||
Opcode.XOR to InstructionFormat(BW, true, true, true, false),
|
||||
Opcode.LSR to InstructionFormat(BW, true, false, false, false),
|
||||
Opcode.LSL to InstructionFormat(BW, true, false, false, false),
|
||||
Opcode.ROR to InstructionFormat(BW, true, false, false, false),
|
||||
Opcode.ROL to InstructionFormat(BW, true, false, false, false),
|
||||
Opcode.LSR to InstructionFormat(BW, true, true, true, false),
|
||||
Opcode.LSL to InstructionFormat(BW, true, true, true, false),
|
||||
Opcode.ROR to InstructionFormat(BW, true, true, true, false),
|
||||
Opcode.ROL to InstructionFormat(BW, true, true, true, false),
|
||||
|
||||
Opcode.COPY to InstructionFormat(NN, true, true, false, true ),
|
||||
Opcode.COPYZ to InstructionFormat(NN, true, true, false, false),
|
||||
|
||||
@ -590,33 +590,37 @@ class VirtualMachine(val memory: Memory, program: List<Instruction>) {
|
||||
}
|
||||
|
||||
private fun InsLSR(i: Instruction) {
|
||||
val (left: UInt, right: UInt) = getLogicalOperandsU(i)
|
||||
when(i.type!!) {
|
||||
VmDataType.BYTE -> registers.setB(i.reg1!!, (registers.getB(i.reg2!!).toInt() ushr 1).toUByte())
|
||||
VmDataType.WORD -> registers.setW(i.reg1!!, (registers.getW(i.reg2!!).toInt() ushr 1).toUShort())
|
||||
VmDataType.BYTE -> registers.setB(i.reg1!!, (left shr right.toInt()).toUByte())
|
||||
VmDataType.WORD -> registers.setW(i.reg1!!, (left shr right.toInt()).toUShort())
|
||||
}
|
||||
pc++
|
||||
}
|
||||
|
||||
private fun InsLSL(i: Instruction) {
|
||||
val (left: UInt, right: UInt) = getLogicalOperandsU(i)
|
||||
when(i.type!!) {
|
||||
VmDataType.BYTE -> registers.setB(i.reg1!!, (registers.getB(i.reg2!!).toInt() shl 1).toUByte())
|
||||
VmDataType.WORD -> registers.setW(i.reg1!!, (registers.getW(i.reg2!!).toInt() shl 1).toUShort())
|
||||
VmDataType.BYTE -> registers.setB(i.reg1!!, (left shl right.toInt()).toUByte())
|
||||
VmDataType.WORD -> registers.setW(i.reg1!!, (left shl right.toInt()).toUShort())
|
||||
}
|
||||
pc++
|
||||
}
|
||||
|
||||
private fun InsROR(i: Instruction) {
|
||||
val (left: UInt, right: UInt) = getLogicalOperandsU(i)
|
||||
when(i.type!!) {
|
||||
VmDataType.BYTE -> registers.setB(i.reg1!!, (registers.getB(i.reg2!!).toInt().rotateRight(1).toUByte()))
|
||||
VmDataType.WORD -> registers.setW(i.reg1!!, (registers.getW(i.reg2!!).toInt().rotateRight(1).toUShort()))
|
||||
VmDataType.BYTE -> registers.setB(i.reg1!!, (left.rotateRight(right.toInt()).toUByte()))
|
||||
VmDataType.WORD -> registers.setW(i.reg1!!, (left.rotateRight(right.toInt()).toUShort()))
|
||||
}
|
||||
pc++
|
||||
}
|
||||
|
||||
private fun InsROL(i: Instruction) {
|
||||
val (left: UInt, right: UInt) = getLogicalOperandsU(i)
|
||||
when(i.type!!) {
|
||||
VmDataType.BYTE -> registers.setB(i.reg1!!, (registers.getB(i.reg2!!).toInt().rotateLeft(1).toUByte()))
|
||||
VmDataType.WORD -> registers.setW(i.reg1!!, (registers.getW(i.reg2!!).toInt().rotateLeft(1).toUShort()))
|
||||
VmDataType.BYTE -> registers.setB(i.reg1!!, (left.rotateLeft(right.toInt()).toUByte()))
|
||||
VmDataType.WORD -> registers.setW(i.reg1!!, (left.rotateLeft(right.toInt()).toUShort()))
|
||||
}
|
||||
pc++
|
||||
}
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user