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added palette.get_color() and palette.default_colors[]
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45a9751217
commit
06bedb7adb
@ -14,6 +14,11 @@ palette {
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cx16.vpoke(1, vera_palette_ptr, msb(color))
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cx16.vpoke(1, vera_palette_ptr, msb(color))
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}
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}
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sub get_color(ubyte index) -> uword {
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vera_palette_ptr = $fa00+(index as uword * 2)
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return mkword(cx16.vpeek(1, vera_palette_ptr+1), cx16.vpeek(1, vera_palette_ptr))
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}
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sub set_rgb_be(uword palette_ptr, uword num_colors) {
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sub set_rgb_be(uword palette_ptr, uword num_colors) {
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; 1 word per color entry, $0rgb in big endian format
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; 1 word per color entry, $0rgb in big endian format
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vera_palette_ptr = $fa00
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vera_palette_ptr = $fa00
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@ -147,9 +152,7 @@ palette {
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set_rgb(colors, len(colors))
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set_rgb(colors, len(colors))
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}
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}
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sub set_default16() {
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uword[] default_colors_16 = [
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; set first 16 colors to the defaults on the X16
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uword[] colors = [
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$000, ; 0 = black
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$000, ; 0 = black
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$fff, ; 1 = white
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$fff, ; 1 = white
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$800, ; 2 = red
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$800, ; 2 = red
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@ -167,6 +170,9 @@ palette {
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$08f, ; 14 = light blue
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$08f, ; 14 = light blue
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$bbb ; 15 = light grey
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$bbb ; 15 = light grey
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]
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]
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set_rgb(colors, len(colors))
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sub set_default16() {
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; set first 16 colors to the defaults on the X16
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set_rgb(default_colors_16, len(default_colors_16))
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}
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}
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}
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}
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@ -620,7 +620,6 @@ asmsub vpeek(ubyte bank @A, uword address @XY) -> ubyte @A {
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; note: inefficient when reading multiple sequential bytes!
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; note: inefficient when reading multiple sequential bytes!
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%asm {{
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%asm {{
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stz cx16.VERA_CTRL
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stz cx16.VERA_CTRL
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and #1
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sta cx16.VERA_ADDR_H
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sta cx16.VERA_ADDR_H
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sty cx16.VERA_ADDR_M
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sty cx16.VERA_ADDR_M
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stx cx16.VERA_ADDR_L
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stx cx16.VERA_ADDR_L
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@ -634,7 +633,6 @@ asmsub vaddr(ubyte bank @A, uword address @R0, ubyte addrsel @R1, byte autoIncrO
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; with optional auto increment or decrement of 1.
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; with optional auto increment or decrement of 1.
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; Note that the vaddr_autoincr() and vaddr_autodecr() routines allow to set all possible strides, not just 1.
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; Note that the vaddr_autoincr() and vaddr_autodecr() routines allow to set all possible strides, not just 1.
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%asm {{
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%asm {{
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and #1
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pha
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pha
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lda cx16.r1
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lda cx16.r1
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and #1
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and #1
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@ -690,8 +688,7 @@ asmsub vaddr_autoincr(ubyte bank @A, uword address @R0, ubyte addrsel @R1, uword
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sta cx16.VERA_ADDR_H
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sta cx16.VERA_ADDR_H
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rts
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rts
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_setup and #1
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_setup sta P8ZP_SCRATCH_REG
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sta P8ZP_SCRATCH_REG
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lda cx16.r1
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lda cx16.r1
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and #1
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and #1
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sta cx16.VERA_CTRL
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sta cx16.VERA_CTRL
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@ -761,7 +758,6 @@ asmsub vpoke(ubyte bank @A, uword address @R0, ubyte value @Y) clobbers(A) {
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; note: inefficient when writing multiple sequential bytes!
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; note: inefficient when writing multiple sequential bytes!
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%asm {{
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%asm {{
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stz cx16.VERA_CTRL
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stz cx16.VERA_CTRL
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and #1
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sta cx16.VERA_ADDR_H
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sta cx16.VERA_ADDR_H
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lda cx16.r0
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lda cx16.r0
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sta cx16.VERA_ADDR_L
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sta cx16.VERA_ADDR_L
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@ -777,7 +773,6 @@ asmsub vpoke_or(ubyte bank @A, uword address @R0, ubyte value @Y) clobbers (A) {
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; note: inefficient when writing multiple sequential bytes!
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; note: inefficient when writing multiple sequential bytes!
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%asm {{
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%asm {{
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stz cx16.VERA_CTRL
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stz cx16.VERA_CTRL
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and #1
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sta cx16.VERA_ADDR_H
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sta cx16.VERA_ADDR_H
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lda cx16.r0
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lda cx16.r0
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sta cx16.VERA_ADDR_L
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sta cx16.VERA_ADDR_L
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@ -795,7 +790,6 @@ asmsub vpoke_and(ubyte bank @A, uword address @R0, ubyte value @Y) clobbers(A) {
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; note: inefficient when writing multiple sequential bytes!
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; note: inefficient when writing multiple sequential bytes!
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%asm {{
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%asm {{
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stz cx16.VERA_CTRL
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stz cx16.VERA_CTRL
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and #1
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sta cx16.VERA_ADDR_H
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sta cx16.VERA_ADDR_H
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lda cx16.r0
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lda cx16.r0
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sta cx16.VERA_ADDR_L
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sta cx16.VERA_ADDR_L
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@ -813,7 +807,6 @@ asmsub vpoke_xor(ubyte bank @A, uword address @R0, ubyte value @Y) clobbers (A)
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; note: inefficient when writing multiple sequential bytes!
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; note: inefficient when writing multiple sequential bytes!
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%asm {{
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%asm {{
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stz cx16.VERA_CTRL
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stz cx16.VERA_CTRL
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and #1
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sta cx16.VERA_ADDR_H
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sta cx16.VERA_ADDR_H
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lda cx16.r0
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lda cx16.r0
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sta cx16.VERA_ADDR_L
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sta cx16.VERA_ADDR_L
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@ -832,7 +825,6 @@ asmsub vpoke_mask(ubyte bank @A, uword address @R0, ubyte mask @X, ubyte value @
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%asm {{
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%asm {{
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sty P8ZP_SCRATCH_B1
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sty P8ZP_SCRATCH_B1
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stz cx16.VERA_CTRL
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stz cx16.VERA_CTRL
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and #1
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sta cx16.VERA_ADDR_H
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sta cx16.VERA_ADDR_H
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lda cx16.r0
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lda cx16.r0
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sta cx16.VERA_ADDR_L
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sta cx16.VERA_ADDR_L
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