ir: fix some problem with comparison against zero

This commit is contained in:
Irmen de Jong 2023-07-07 21:17:28 +02:00
parent d2154f5f2e
commit 071a80360f
2 changed files with 57 additions and 20 deletions

View File

@ -1002,10 +1002,10 @@ class IRCodeGen(
val opcode = when (condition.operator) { val opcode = when (condition.operator) {
"==" -> Opcode.BEQ "==" -> Opcode.BEQ
"!=" -> Opcode.BNE "!=" -> Opcode.BNE
"<" -> if (signed) Opcode.BLTS else throw AssemblyError("unsigned < 0 shouldn't occur in codegen") "<" -> if (signed) Opcode.BLTS else Opcode.BLT
">" -> if (signed) Opcode.BGTS else throw AssemblyError("unsigned > 0 shouldn't occur in codegen") ">" -> if (signed) Opcode.BGTS else Opcode.BGT
"<=" -> if (signed) Opcode.BLES else throw AssemblyError("unsigned <= 0 shouldn't occur in codegen") "<=" -> if (signed) Opcode.BLES else Opcode.BLE
">=" -> if (signed) Opcode.BGES else throw AssemblyError("unsigned >= 0 shouldn't occur in codegen") ">=" -> if (signed) Opcode.BGES else Opcode.BGE
else -> throw AssemblyError("invalid comparison operator") else -> throw AssemblyError("invalid comparison operator")
} }
if (goto.address != null) if (goto.address != null)
@ -1139,10 +1139,10 @@ class IRCodeGen(
elseBranch = when (condition.operator) { elseBranch = when (condition.operator) {
"==" -> Opcode.BNE "==" -> Opcode.BNE
"!=" -> Opcode.BEQ "!=" -> Opcode.BEQ
"<" -> if (signed) Opcode.BGES else throw AssemblyError("unsigned < 0 shouldn't occur in codegen") "<" -> if (signed) Opcode.BGES else Opcode.BGE
">" -> if (signed) Opcode.BLES else throw AssemblyError("unsigned > 0 shouldn't occur in codegen") ">" -> if (signed) Opcode.BLES else Opcode.BLE
"<=" -> if (signed) Opcode.BGTS else throw AssemblyError("unsigned <= 0 shouldn't occur in codegen") "<=" -> if (signed) Opcode.BGTS else Opcode.BGT
">=" -> if (signed) Opcode.BLTS else throw AssemblyError("unsigned >= 0 shouldn't occur in codegen") ">=" -> if (signed) Opcode.BLTS else Opcode.BLT
else -> throw AssemblyError("weird operator") else -> throw AssemblyError("weird operator")
} }
} }

View File

@ -1,18 +1,55 @@
%import textio %import textio
%zeropage basicsafe
; TODO this should also compile without optimizations
main { main {
sub start() { sub start() {
cx16.r0 = 2 cx16.r0 = 0
when cx16.r0 { if cx16.r0 < 0
1-> { txt.print(" <0 fail\n")
;nothing else
} txt.print(" <0 ok\n")
2 -> {
txt.print("two") if cx16.r0 <= 0
} txt.print("<=0 ok\n")
0-> { else
;nothing txt.print("<=0 fail\n")
}
} if cx16.r0 > 0
txt.print(" >0 fail\n")
else
txt.print(" >0 ok\n")
if cx16.r0 >= 0
txt.print(">=0 ok\n")
else
txt.print(">=0 fail\n")
bool bb
bb = cx16.r0<0
if bb
txt.print(" <0 fail\n")
else
txt.print(" <0 ok\n")
bb = cx16.r0<=0
if bb
txt.print("<=0 ok\n")
else
txt.print("<=0 fail\n")
bb = cx16.r0>0
if bb
txt.print(" >0 fail\n")
else
txt.print(" >0 ok\n")
bb = cx16.r0>=0
if bb
txt.print(">=0 ok\n")
else
txt.print(">=0 fail\n")
} }
} }