IR: fix various register type mismatches

This commit is contained in:
Irmen de Jong
2025-05-28 22:15:07 +02:00
parent 86da9d3c7e
commit 08b314c37d
5 changed files with 149 additions and 101 deletions

View File

@@ -409,5 +409,68 @@ main {
errors.errors.size shouldBe 0
errors.warnings.size shouldBe 0
}
test("various array indexed assignment scenarios") {
val src="""
%import floats
%import textio
%zeropage basicsafe
main {
bool[10] barray
uword[10] @nosplit warrayns
uword[10] warray
float[10] farray
sub start() {
dump()
; ALL OK
barray[2] = true
warrayns[2] = 1234
warray[2] = 5678
farray[2] = 3.1415
dump()
; ALL OK
cx16.r0L=2
barray[cx16.r0L] = false
warrayns[cx16.r0L] = 0
warray[cx16.r0L] = 0
farray[cx16.r0L] = 0
dump()
; ALL OK
cx16.r0L=2
barray[cx16.r0L] = true
warrayns[cx16.r0L] = 1234
warray[cx16.r0L] = 5678
farray[cx16.r0L] = 3.1415
dump()
; ALL OK
barray[2] = false
warrayns[2] = 0
warray[2] = 0
farray[2] = 0.0
dump()
sub dump() {
txt.print_bool(barray[2])
txt.spc()
txt.print_uw(warrayns[2])
txt.spc()
txt.print_uw(warray[2])
txt.spc()
txt.print_f(farray[2])
txt.nl()
}
}
}"""
compileText(C64Target(), optimize=true, src, outputDir) shouldNotBe null
compileText(VMTarget(), optimize=true, src, outputDir) shouldNotBe null
compileText(C64Target(), optimize=false, src, outputDir) shouldNotBe null
compileText(VMTarget(), optimize=false, src, outputDir) shouldNotBe null
}
})

View File

@@ -615,4 +615,19 @@ main {
compileText(C64Target(), false, src, outputDir, writeAssembly = true) shouldNotBe null
compileText(VMTarget(), false, src, outputDir, writeAssembly = true) shouldNotBe null
}
test("word bitshift with byte operand") {
val src="""
main{
sub start() {
cx16.r0 >>= 4
cx16.r1 <<= 4
}
}"""
compileText(C64Target(), false, src, outputDir) shouldNotBe null
compileText(VMTarget(), false, src, outputDir) shouldNotBe null
compileText(C64Target(), true, src, outputDir) shouldNotBe null
compileText(VMTarget(), true, src, outputDir) shouldNotBe null
}
})