fix c64 zeropage locations of cx16 virtual registers

This commit is contained in:
Irmen de Jong 2022-08-13 00:14:19 +02:00
parent b6eef3612f
commit 0aa0ec5abd
5 changed files with 21 additions and 31 deletions

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@ -56,7 +56,7 @@ class C64Zeropage(options: CompilationOptions) : Zeropage(options) {
if(options.zeropage!= ZeropageType.DONTUSE) { if(options.zeropage!= ZeropageType.DONTUSE) {
// add the free Zp addresses // add the free Zp addresses
// these are valid for the C-64 but allow BASIC to keep running fully *as long as you don't use tape I/O* // these are valid for the C-64 but allow BASIC to keep running fully *as long as you don't use tape I/O*
free.addAll(listOf(0x04, 0x05, 0x06, 0x0a, 0x0e, free.addAll(listOf(0x02, 0x03, 0x04, 0x05, 0x06, 0x0a, 0x0e,
0x92, 0x96, 0x9b, 0x9c, 0x9e, 0x9f, 0xa5, 0xa6, 0x92, 0x96, 0x9b, 0x9c, 0x9e, 0x9f, 0xa5, 0xa6,
0xb0, 0xb1, 0xbe, 0xbf, 0xf9).map{it.toUInt()}) 0xb0, 0xb1, 0xbe, 0xbf, 0xf9).map{it.toUInt()})
} else { } else {

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@ -7,10 +7,7 @@ import prog8.ast.expressions.*
import prog8.ast.statements.* import prog8.ast.statements.*
import prog8.ast.walk.AstWalker import prog8.ast.walk.AstWalker
import prog8.ast.walk.IAstModification import prog8.ast.walk.IAstModification
import prog8.code.core.CompilationOptions import prog8.code.core.*
import prog8.code.core.Encoding
import prog8.code.core.IErrorReporter
import prog8.code.core.NumericDatatypes
import prog8.code.target.C64Target import prog8.code.target.C64Target
import prog8.code.target.Cx16Target import prog8.code.target.Cx16Target
@ -21,7 +18,11 @@ class AstPreprocessor(val program: Program,
override fun before(program: Program): Iterable<IAstModification> { override fun before(program: Program): Iterable<IAstModification> {
if(options.compTarget.name==C64Target.NAME) { if(options.compTarget.name==C64Target.NAME) {
relocateCx16VirtualRegisters(program, 0x0004u) // unfortunately, can't be the same address as CommanderX16 if(options.zeropage==ZeropageType.KERNALSAFE || options.zeropage==ZeropageType.FULL) {
// there is enough space in the zero page to put the cx16 virtual registers there.
// unfortunately, can't be the same address as CommanderX16.
relocateCx16VirtualRegisters(program, 0x0004u)
}
} }
else if(options.compTarget.name!=Cx16Target.NAME) { else if(options.compTarget.name!=Cx16Target.NAME) {
relocateCx16VirtualRegisters(program, options.compTarget.machine.ESTACK_HI) relocateCx16VirtualRegisters(program, options.compTarget.machine.ESTACK_HI)

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@ -3,8 +3,6 @@ TODO
For next release For next release
^^^^^^^^^^^^^^^^ ^^^^^^^^^^^^^^^^
- check that all examples still function correctly
... ...

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@ -17,7 +17,7 @@ main {
uword prime uword prime
uword k uword k
const uword SIZEPL = 8191 const uword SIZEPL = 8191
uword flags_ptr = memory("flags", SIZEPL, $100) uword @zp flags_ptr = memory("flags", SIZEPL, $100)
txt.print("calculating...\n") txt.print("calculating...\n")

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@ -1,30 +1,21 @@
%import textio %import textio
%zeropage basicsafe %zeropage basicsafe
main { main {
sub start() { sub start() {
uword crc = $ffff
if crc & $8000 ; msb(crc) & $80
txt.print("yes")
else
txt.print("fail!")
if crc & $1234 uword @zp flags_ptr = memory("flags", 200, 0)
txt.print("yes") txt.print("calculating...\n")
else txt.print_uwhex(flags_ptr, true)
txt.print("fail!") txt.nl()
repeat 10 {
txt.print("new iter\n")
txt.print_ub(@($06))
sys.memset(flags_ptr, 200, 0)
}
txt.print("done\n")
} }
; sub start2() {
; ubyte[] arr = [1,2,3,4]
; uword pointer
; ubyte ix
;
; arr[ix] = arr[ix]+1
;
;; arr[3] = arr[3]+1
;; pointer[3] = pointer[3]+1
;
; txt.print_ub(arr[3])
; }
} }