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cx16: reorder processing of IRQ handlers
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@ -881,12 +881,37 @@ asmsub enable_irq_handlers(bool disable_all_irq_sources @Pc) clobbers(A,Y) {
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rts
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rts
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_irq_dispatcher
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_irq_dispatcher
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; order of handling: LINE, SPRCOL, AFLOW, VSYNC.
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jsr sys.save_prog8_internals
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jsr sys.save_prog8_internals
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cld
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cld
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lda cx16.VERA_ISR
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lda cx16.VERA_ISR
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and cx16.VERA_IEN ; only consider the bits for sources that can actually raise the IRQ
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and cx16.VERA_IEN ; only consider the bits for sources that can actually raise the IRQ
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lsr a
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bcc +
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bit #2
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beq +
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_mod_line_jump
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jsr _default_line_handler ; modified
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ldy #2
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sty cx16.VERA_ISR
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bra _dispatch_end
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+
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bit #4
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beq +
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_mod_sprcol_jump
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jsr _default_sprcol_handler ; modified
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ldy #4
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sty cx16.VERA_ISR
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bra _dispatch_end
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+
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bit #8
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beq +
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_mod_aflow_jump
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jsr _default_aflow_handler ; modified
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; note: AFLOW can only be cleared by filling the audio FIFO for at least 1/4. Not via the ISR bit.
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bra _dispatch_end
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+
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bit #1
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beq +
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_mod_vsync_jump
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_mod_vsync_jump
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jsr _default_vsync_handler ; modified
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jsr _default_vsync_handler ; modified
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cmp #0
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cmp #0
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@ -894,27 +919,8 @@ _mod_vsync_jump
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ldy #1
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ldy #1
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sty cx16.VERA_ISR
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sty cx16.VERA_ISR
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bra _return_irq
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bra _return_irq
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+ lsr a
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+
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bcc +
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lda #0
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_mod_line_jump
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jsr _default_line_handler ; modified
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ldy #2
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sty cx16.VERA_ISR
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bra _dispatch_end
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+ lsr a
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bcc +
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_mod_sprcol_jump
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jsr _default_sprcol_handler ; modified
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ldy #4
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sty cx16.VERA_ISR
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bra _dispatch_end
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+ lsr a
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bcc +
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_mod_aflow_jump
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jsr _default_aflow_handler ; modified
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; note: AFLOW can only be cleared by filling the audio FIFO for at least 1/4. Not via the ISR bit.
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bra _dispatch_end
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+ lda #0
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_dispatch_end
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_dispatch_end
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cmp #0
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cmp #0
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beq _return_irq
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beq _return_irq
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@ -209,6 +209,7 @@ Here they are, all available in ``cx16``:
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by setting the various handlers), or pass false to not touch this.
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by setting the various handlers), or pass false to not touch this.
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The handlers don't need to clear its ISR bit, but have to return 0 or 1 in A,
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The handlers don't need to clear its ISR bit, but have to return 0 or 1 in A,
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where 1 means: continue with the system IRQ handler, 0 means: don't call that.
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where 1 means: continue with the system IRQ handler, 0 means: don't call that.
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The order in which the handlers are invoked if multiple interrupts occur simultaneously is: LINE, SPRCOL, AFLOW, VSYNC.
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``set_vsync_irq_handler (uword address)``
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``set_vsync_irq_handler (uword address)``
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Sets the verical sync interrupt handler routine. Also enables VSYNC interrupts.
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Sets the verical sync interrupt handler routine. Also enables VSYNC interrupts.
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