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cx16: reorder processing of IRQ handlers

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Irmen de Jong 2023-11-24 01:12:27 +01:00
parent 82a15b5a16
commit 0bee6f6b41
2 changed files with 30 additions and 23 deletions
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52
compiler/res/prog8lib/cx16/syslib.p8
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@ -881,12 +881,37 @@ asmsub enable_irq_handlers(bool disable_all_irq_sources @Pc) clobbers(A,Y) {
rts rts
_irq_dispatcher _irq_dispatcher
; order of handling: LINE, SPRCOL, AFLOW, VSYNC.
jsr sys.save_prog8_internals jsr sys.save_prog8_internals
cld cld
lda cx16.VERA_ISR lda cx16.VERA_ISR
and cx16.VERA_IEN ; only consider the bits for sources that can actually raise the IRQ and cx16.VERA_IEN ; only consider the bits for sources that can actually raise the IRQ
lsr a
bcc + bit #2
beq +
_mod_line_jump
jsr _default_line_handler ; modified
ldy #2
sty cx16.VERA_ISR
bra _dispatch_end
+
bit #4
beq +
_mod_sprcol_jump
jsr _default_sprcol_handler ; modified
ldy #4
sty cx16.VERA_ISR
bra _dispatch_end
+
bit #8
beq +
_mod_aflow_jump
jsr _default_aflow_handler ; modified
; note: AFLOW can only be cleared by filling the audio FIFO for at least 1/4. Not via the ISR bit.
bra _dispatch_end
+
bit #1
beq +
_mod_vsync_jump _mod_vsync_jump
jsr _default_vsync_handler ; modified jsr _default_vsync_handler ; modified
cmp #0 cmp #0
@ -894,27 +919,8 @@ _mod_vsync_jump
ldy #1 ldy #1
sty cx16.VERA_ISR sty cx16.VERA_ISR
bra _return_irq bra _return_irq
+ lsr a +
bcc + lda #0
_mod_line_jump
jsr _default_line_handler ; modified
ldy #2
sty cx16.VERA_ISR
bra _dispatch_end
+ lsr a
bcc +
_mod_sprcol_jump
jsr _default_sprcol_handler ; modified
ldy #4
sty cx16.VERA_ISR
bra _dispatch_end
+ lsr a
bcc +
_mod_aflow_jump
jsr _default_aflow_handler ; modified
; note: AFLOW can only be cleared by filling the audio FIFO for at least 1/4. Not via the ISR bit.
bra _dispatch_end
+ lda #0
_dispatch_end _dispatch_end
cmp #0 cmp #0
beq _return_irq beq _return_irq

1
docs/source/targetsystem.rst
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@ -209,6 +209,7 @@ Here they are, all available in ``cx16``:
by setting the various handlers), or pass false to not touch this. by setting the various handlers), or pass false to not touch this.
The handlers don't need to clear its ISR bit, but have to return 0 or 1 in A, The handlers don't need to clear its ISR bit, but have to return 0 or 1 in A,
where 1 means: continue with the system IRQ handler, 0 means: don't call that. where 1 means: continue with the system IRQ handler, 0 means: don't call that.
The order in which the handlers are invoked if multiple interrupts occur simultaneously is: LINE, SPRCOL, AFLOW, VSYNC.
``set_vsync_irq_handler (uword address)`` ``set_vsync_irq_handler (uword address)``
Sets the verical sync interrupt handler routine. Also enables VSYNC interrupts. Sets the verical sync interrupt handler routine. Also enables VSYNC interrupts.